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1. 发明申请

US20130094308A1 NEGATIVE WORD LINE DRIVER FOR SEMICONDUCTOR MEMORIES 有权
标题翻译：用于半导体存储器的负号线驱动器
公开(公告)号：US20130094308A1
公开(公告)日：2013-04-18
申请号：US13273369
申请日：2011-10-14
申请人： Chen-Lin Yang , Wei Min Chan , Chung-Hsien Hua
发明人： Chen-Lin Yang , Wei Min Chan , Chung-Hsien Hua
IPC分类号： G11C8/08
CPC分类号： G11C8/08 , G11C7/22 , G11C11/418
摘要： A semiconductor memory includes a word line driver and a negative voltage generator. The word line driver includes a first inverter configured to drive a word line at one of a first voltage supplied by a first voltage source and a second voltage supplied by a second voltage source. The negative voltage generator is configured to provide a negative voltage with respect to the second voltage to an input of the first inverter in response to a control signal for performing at least one of a read or a write operation of a memory bit cell coupled to the word line.
摘要翻译：半导体存储器包括字线驱动器和负电压发生器。字线驱动器包括第一反相器，被配置为以由第一电压源提供的第一电压和由第二电压源提供的第二电压中的一个驱动字线。负电压发生器被配置为响应于用于执行耦合到第一反相器的存储器位单元的读取或写入操作中的至少一个的控制信号，将相对于第二电压的负电压提供给第一反相器的输入字线。

2. 发明授权

US08990751B2 Computer system and method of preparing a layout 有权
标题翻译：计算机系统及其布局方法
公开(公告)号：US08990751B2
公开(公告)日：2015-03-24
申请号：US12913949
申请日：2010-10-28
申请人： Chen-Lin Yang , Wei Min Chan
发明人： Chen-Lin Yang , Wei Min Chan
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5009 , G06F17/5068
摘要： The present application discloses a method of preparing a layout for manufacturing an integrated circuit chip according to a circuit design. In at least one embodiment, a pattern for the layout based on the circuit design is generated. After the generation of the pattern, it is determined if at least one layout rule is violated in the layout, the at least one layout rule being specified according to a predetermined maximum value for at least one of an estimated voltage drop along a signal path in the layout or an estimated current density on the signal path. If the at least one layout rule is violated, a violation is indicated.
摘要翻译：本申请公开了根据电路设计制备用于制造集成电路芯片的布局的方法。在至少一个实施例中，生成用于基于电路设计的布局的图案。在生成图案之后，确定在布局中是否违反了至少一个布局规则，根据预定的最大值来指定至少一个布局规则，用于沿着信号路径的估计电压降中的至少一个信号路径上的布局或估计的电流密度。如果违反了至少一个布局规则，则会显示违规。

3. 发明授权

US08830784B2 Negative word line driver for semiconductor memories 有权
标题翻译：用于半导体存储器的负字线驱动器
公开(公告)号：US08830784B2
公开(公告)日：2014-09-09
申请号：US13273369
申请日：2011-10-14
申请人： Chen-Lin Yang , Wei Min Chan , Chung-Hsien Hua
发明人： Chen-Lin Yang , Wei Min Chan , Chung-Hsien Hua
IPC分类号： G11C8/00 , G11C8/08 , G11C7/22 , G11C11/418
CPC分类号： G11C8/08 , G11C7/22 , G11C11/418
摘要： A semiconductor memory includes a word line driver and a negative voltage generator. The word line driver includes a first inverter configured to drive a word line at one of a first voltage supplied by a first voltage source and a second voltage supplied by a second voltage source. The negative voltage generator is configured to provide a negative voltage with respect to the second voltage to an input of the first inverter in response to a control signal for performing at least one of a read or a write operation of a memory bit cell coupled to the word line.
摘要翻译：半导体存储器包括字线驱动器和负电压发生器。字线驱动器包括第一反相器，被配置为以由第一电压源提供的第一电压和由第二电压源提供的第二电压中的一个驱动字线。负电压发生器被配置为响应于用于执行耦合到第一反相器的存储器位单元的读取或写入操作中的至少一个的控制信号，将相对于第二电压的负电压提供给第一反相器的输入字线。

4. 发明授权

US08391097B2 Memory word-line driver having reduced power consumption 有权
标题翻译：存储器字线驱动器具有降低的功耗
公开(公告)号：US08391097B2
公开(公告)日：2013-03-05
申请号：US12786791
申请日：2010-05-25
申请人： Wei Min Chan , Yen-Huei Chen , Chen-Lin Yang , Hsiu-Hui Yang , Shao-Yu Chou
发明人： Wei Min Chan , Yen-Huei Chen , Chen-Lin Yang , Hsiu-Hui Yang , Shao-Yu Chou
IPC分类号： G11C11/34 , G11C7/00
CPC分类号： G11C16/30 , G11C8/08
摘要： A word-line driving circuit for driving a word-line in a memory array includes a NAND circuit having a pair of address inputs and an output, an output inverter circuit having an inverter power supply node, an input coupled to the output of the NAND circuit and an output for providing a word line signal, a power gate coupled between a first power supply node and the inverter power supply node, and a control circuit coupled to the power gate. The control circuit controls the power gate to place the word line driver circuit in active or standby mode in response to the output of the NAND circuit.
摘要翻译：用于驱动存储器阵列中的字线的字线驱动电路包括具有一对地址输入和输出的NAND电路，具有反相器电源节点的输出反相器电路，耦合到NAND的输出的输入电路和用于提供字线信号的输出，耦合在第一电源节点和逆变器电源节点之间的电源栅极以及耦合到电源门的控制电路。控制电路控制电源门以响应于NAND电路的输出将字线驱动电路置于有效或待机模式。

5. 发明申请

US20110292754A1 MEMORY WORD-LINE DRIVER HAVING REDUCED POWER CONSUMPTION 有权
标题翻译：具有降低功耗的存储器字线驱动器
公开(公告)号：US20110292754A1
公开(公告)日：2011-12-01
申请号：US12786791
申请日：2010-05-25
申请人： Wei Min Chan , Yen-Huei Chen , Chen-Lin Yang , Hsiu-Hui Yang , Shao-Yu Chou
发明人： Wei Min Chan , Yen-Huei Chen , Chen-Lin Yang , Hsiu-Hui Yang , Shao-Yu Chou
IPC分类号： G11C8/08
CPC分类号： G11C16/30 , G11C8/08
摘要： A word-line driving circuit for driving a word-line in a memory array includes a NAND circuit having a pair of address inputs and an output, an output inverter circuit having an inverter power supply node, an input coupled to the output of the NAND circuit and an output for providing a word line signal, a power gate coupled between a first power supply node and the inverter power supply node, and a control circuit coupled to the power gate. The control circuit controls the power gate to place the word line driver circuit in active or standby mode in response to the output of the NAND circuit.
摘要翻译：用于驱动存储器阵列中的字线的字线驱动电路包括具有一对地址输入和输出的NAND电路，具有反相器电源节点的输出反相器电路，耦合到NAND的输出的输入电路和用于提供字线信号的输出，耦合在第一电源节点和逆变器电源节点之间的电源栅极以及耦合到电源门的控制电路。控制电路控制电源门以响应于NAND电路的输出将字线驱动电路置于有效或待机模式。

6. 发明授权

US08441885B2 Methods and apparatus for memory word line driver 有权
标题翻译：内存字线驱动程序的方法和装置
公开(公告)号：US08441885B2
公开(公告)日：2013-05-14
申请号：US13051681
申请日：2011-03-18
申请人： Wei Min Chan , Li-Wen Wang , Jihi-Yu Lin , Chen-Lin Yang , Shao-Yu Chou
发明人： Wei Min Chan , Li-Wen Wang , Jihi-Yu Lin , Chen-Lin Yang , Shao-Yu Chou
IPC分类号： G11C8/00
CPC分类号： G11C8/08 , G11C8/18 , G11C11/413
摘要： A word line driver circuit and corresponding methods are disclosed. An apparatus, comprising a decoder circuit coupled to receive address inputs, and having a decoder output; and a word line clock gating circuit coupled to the decoder output and to a word line clock signal, configured to selectively output a word line signal responsive to an edge on the word line clock signal; wherein the address inputs have a set up time requirement relative to the edge of the word line clock signal, and the address inputs have a zero or less hold time requirement relative to the edge of the word line clock signal. Methods for providing a word line signal from a word line driver are disclosed.
摘要翻译：公开了一种字线驱动电路及相应的方法。一种装置，包括被耦合以接收地址输入并具有解码器输出的解码器电路; 以及字线时钟选通电路，其耦合到所述解码器输出和字线时钟信号，被配置为响应于所述字线时钟信号上的边沿选择性地输出字线信号; 其中所述地址输入具有相对于所述字线时钟信号的边缘的建立时间要求，并且所述地址输入相对于所述字线时钟信号的边缘具有零或更小的保持时间要求。公开了从字线驱动器提供字线信号的方法。

7. 发明申请

US20120236675A1 Methods and Apparatus for Memory Word Line Driver 有权
标题翻译：内存字线驱动程序的方法和装置
公开(公告)号：US20120236675A1
公开(公告)日：2012-09-20
申请号：US13051681
申请日：2011-03-18
申请人： Wei Min Chan , Li-Wen Wang , Jihi-Yu Lin , Chen-Lin Yang , Shao-Yu Chou
发明人： Wei Min Chan , Li-Wen Wang , Jihi-Yu Lin , Chen-Lin Yang , Shao-Yu Chou
IPC分类号： G11C8/10
CPC分类号： G11C8/08 , G11C8/18 , G11C11/413
摘要： A word line driver circuit and corresponding methods are disclosed. An apparatus, comprising a decoder circuit coupled to receive address inputs, and having a decoder output; and a word line clock gating circuit coupled to the decoder output and to a word line clock signal, configured to selectively output a word line signal responsive to an edge on the word line clock signal; wherein the address inputs have a set up time requirement relative to the edge of the word line clock signal, and the address inputs have a zero or less hold time requirement relative to the edge of the word line clock signal. Methods for providing a word line signal from a word line driver are disclosed.
摘要翻译：公开了一种字线驱动电路及相应的方法。一种装置，包括被耦合以接收地址输入并具有解码器输出的解码器电路; 以及字线时钟选通电路，其耦合到所述解码器输出和字线时钟信号，被配置为响应于所述字线时钟信号上的边沿选择性地输出字线信号; 其中所述地址输入具有相对于所述字线时钟信号的边缘的建立时间要求，并且所述地址输入相对于所述字线时钟信号的边缘具有零或更小的保持时间要求。公开了从字线驱动器提供字线信号的方法。

8. 发明授权

US08213241B2 Memory readout scheme using separate sense amplifier voltage 有权
标题翻译：存储器读出方案使用单独的读出放大器电压
公开(公告)号：US08213241B2
公开(公告)日：2012-07-03
申请号：US12706099
申请日：2010-02-16
申请人： Chen-Lin Yang
发明人： Chen-Lin Yang
IPC分类号： G11C7/00
CPC分类号： G11C7/08
摘要： A memory includes a memory cell coupled to a data line. A sense amplifier is coupled to the data line. A power supply node has a first voltage. The first voltage is provided to the sense amplifier. A charge pump circuit is coupled to the sense amplifier. The charge pump circuit is configured to provide a second voltage to the sense amplifier when a read operation is performed.
摘要翻译：存储器包括耦合到数据线的存储单元。读出放大器耦合到数据线。电源节点具有第一电压。第一电压被提供给读出放大器。电荷泵电路耦合到读出放大器。电荷泵电路被配置为当执行读取操作时向读出放大器提供第二电压。

9. 发明授权

US08077517B2 Distributed VDC for SRAM memory 有权
标题翻译：分布式VDC用于SRAM存储器
公开(公告)号：US08077517B2
公开(公告)日：2011-12-13
申请号：US12338732
申请日：2008-12-18
申请人： Li-Wen Wang , Yen-Huei Chen , Chen-Lin Yang , Hsien-Yu Pan , Shao-Yu Chou , Hung-Jen Liao
发明人： Li-Wen Wang , Yen-Huei Chen , Chen-Lin Yang , Hsien-Yu Pan , Shao-Yu Chou , Hung-Jen Liao
IPC分类号： G11C11/34
CPC分类号： G11C11/413 , G11C5/04 , G11C5/147
摘要： An integrated circuit structure includes a memory. The memory includes a first memory macro and a second memory macro identical to the first memory macro. A first power block is connected to the first memory macro and is configured to provide a regulated voltage to the first memory macro. The first power block has a first input and a first output. A second power block substantially identical to the first power block is connected to the second memory macro and is configured to provide the regulated voltage to the second memory macro. The second power block has a second input and a second output. The first input and the second input are interconnected. The first output and the second output are interconnected.
摘要翻译：集成电路结构包括存储器。存储器包括与第一存储器宏相同的第一存储器宏和第二存储器宏。第一功率块连接到第一存储器宏，并被配置为向第一存储器宏提供调节电压。第一功率块具有第一输入和第一输出。基本上与第一功率块相同的第二功率块连接到第二存储器宏，并且被配置为向第二存储器宏提供调节电压。第二功率块具有第二输入和第二输出。第一输入和第二输入互连。第一个输出和第二个输出相互连接。

10. 发明授权

US08767494B2 Far end resistance tracking design with near end pre-charge control for faster recovery time 有权
标题翻译：远端电阻跟踪设计，具有近端预充电控制，可实现更快的恢复时间
公开(公告)号：US08767494B2
公开(公告)日：2014-07-01
申请号：US13493118
申请日：2012-06-11
申请人： Chen-Lin Yang , Chung-Yi Wu , Yu-Hao Hsu
发明人： Chen-Lin Yang , Chung-Yi Wu , Yu-Hao Hsu
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C7/12 , G11C7/227 , G11C8/18 , G11C11/413
摘要： A wordline tracking circuit and corresponding method are disclosed, and include a tracking wordline having an impedance characteristic associated therewith that models a row of memory cells in a memory device, wherein the tracking wordline has a near end that receives a wordline pulse signal having a near end rising pulse edge and a near end falling pulse edge. The tracking wordline also has a far end. A tracking cell component is coupled to the far end of the tracking wordline that receives the wordline pulse signal. Lastly, the circuit includes a tracking bitline pre-charge circuit coupled to the tracking cell that is configured to pre-charge a tracking bitline associated with the tracking cell using the near end wordline pulse signal.
摘要翻译：公开了一种字线追踪电路及相应的方法，包括具有与之相关联的阻抗特征的跟踪字线，其对存储器件中的一行存储单元进行建模，其中跟踪字线具有接近具有近似的字线脉冲信号的近端结束上升脉冲沿和近端下降脉冲沿。跟踪字线也有一个远端。跟踪单元组件耦合到接收字线脉冲信号的跟踪字线的远端。最后，电路包括耦合到跟踪单元的跟踪位线预充电电路，其被配置为使用近端字线脉冲信号对与跟踪单元相关联的跟踪位线进行预充电。

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