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    • 2. 发明授权
    • Computer system and method of preparing a layout
    • 计算机系统及其布局方法
    • US08990751B2
    • 2015-03-24
    • US12913949
    • 2010-10-28
    • Chen-Lin YangWei Min Chan
    • Chen-Lin YangWei Min Chan
    • G06F17/50
    • G06F17/5081G06F17/5009G06F17/5068
    • The present application discloses a method of preparing a layout for manufacturing an integrated circuit chip according to a circuit design. In at least one embodiment, a pattern for the layout based on the circuit design is generated. After the generation of the pattern, it is determined if at least one layout rule is violated in the layout, the at least one layout rule being specified according to a predetermined maximum value for at least one of an estimated voltage drop along a signal path in the layout or an estimated current density on the signal path. If the at least one layout rule is violated, a violation is indicated.
    • 本申请公开了根据电路设计制备用于制造集成电路芯片的布局的方法。 在至少一个实施例中,生成用于基于电路设计的布局的图案。 在生成图案之后,确定在布局中是否违反了至少一个布局规则,根据预定的最大值来指定至少一个布局规则,用于沿着信号路径的估计电压降中的至少一个 信号路径上的布局或估计的电流密度。 如果违反了至少一个布局规则,则会显示违规。
    • 6. 发明授权
    • Methods and apparatus for memory word line driver
    • 内存字线驱动程序的方法和装置
    • US08441885B2
    • 2013-05-14
    • US13051681
    • 2011-03-18
    • Wei Min ChanLi-Wen WangJihi-Yu LinChen-Lin YangShao-Yu Chou
    • Wei Min ChanLi-Wen WangJihi-Yu LinChen-Lin YangShao-Yu Chou
    • G11C8/00
    • G11C8/08G11C8/18G11C11/413
    • A word line driver circuit and corresponding methods are disclosed. An apparatus, comprising a decoder circuit coupled to receive address inputs, and having a decoder output; and a word line clock gating circuit coupled to the decoder output and to a word line clock signal, configured to selectively output a word line signal responsive to an edge on the word line clock signal; wherein the address inputs have a set up time requirement relative to the edge of the word line clock signal, and the address inputs have a zero or less hold time requirement relative to the edge of the word line clock signal. Methods for providing a word line signal from a word line driver are disclosed.
    • 公开了一种字线驱动电路及相应的方法。 一种装置,包括被耦合以接收地址输入并具有解码器输出的解码器电路; 以及字线时钟选通电路,其耦合到所述解码器输出和字线时钟信号,被配置为响应于所述字线时钟信号上的边沿选择性地输出字线信号; 其中所述地址输入具有相对于所述字线时钟信号的边缘的建立时间要求,并且所述地址输入相对于所述字线时钟信号的边缘具有零或更小的保持时间要求。 公开了从字线驱动器提供字线信号的方法。
    • 10. 发明授权
    • Far end resistance tracking design with near end pre-charge control for faster recovery time
    • 远端电阻跟踪设计,具有近端预充电控制,可实现更快的恢复时间
    • US08767494B2
    • 2014-07-01
    • US13493118
    • 2012-06-11
    • Chen-Lin YangChung-Yi WuYu-Hao Hsu
    • Chen-Lin YangChung-Yi WuYu-Hao Hsu
    • G11C7/00G11C8/00
    • G11C7/12G11C7/227G11C8/18G11C11/413
    • A wordline tracking circuit and corresponding method are disclosed, and include a tracking wordline having an impedance characteristic associated therewith that models a row of memory cells in a memory device, wherein the tracking wordline has a near end that receives a wordline pulse signal having a near end rising pulse edge and a near end falling pulse edge. The tracking wordline also has a far end. A tracking cell component is coupled to the far end of the tracking wordline that receives the wordline pulse signal. Lastly, the circuit includes a tracking bitline pre-charge circuit coupled to the tracking cell that is configured to pre-charge a tracking bitline associated with the tracking cell using the near end wordline pulse signal.
    • 公开了一种字线追踪电路及相应的方法,包括具有与之相关联的阻抗特征的跟踪字线,其对存储器件中的一行存储单元进行建模,其中跟踪字线具有接近具有近似的字线脉冲信号的近端 结束上升脉冲沿和近端下降脉冲沿。 跟踪字线也有一个远端。 跟踪单元组件耦合到接收字线脉冲信号的跟踪字线的远端。 最后,电路包括耦合到跟踪单元的跟踪位线预充电电路,其被配置为使用近端字线脉冲信号对与跟踪单元相关联的跟踪位线进行预充电。