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1. 发明申请

WO2008100415A3 NONVOLATILE MEMORY SYSTEM 审中-公开
标题翻译：非易失性存储系统
公开(公告)号：WO2008100415A3
公开(公告)日：2008-11-27
申请号：PCT/US2008001669
申请日：2008-02-08
申请人： MARVELL WORLD TRADE LTD , WU ZINING , NGUYEN LAU , SUTARDJA PANTAS , LEE CHI-KONG , YOON TONY
发明人： WU ZINING , NGUYEN LAU , SUTARDJA PANTAS , LEE CHI-KONG , YOON TONY
IPC分类号： G06F11/10
CPC分类号： G06F3/0688 , G06F3/0619 , G06F3/0661 , G06F11/1068 , G06F12/0246
摘要： A nonvolatile (NV) memory system includes a memory control module that encodes data to provide encoded logical data structures. The system also includes NV memory that includes X arrays that include physical data structures that differ in size from the encoded logical data structures. The memory control module writes/reads from the NV memory according to the encoded logical data structures. X is an integer greater than or equal to 1.
摘要翻译：非易失性（NV）存储器系统包括对数据进行编码以提供编码的逻辑数据结构的存储器控制模块。该系统还包括NV存储器，其包括X阵列，其包括与编码的逻辑数据结构不同的物理数据结构。存储器控制模块根据编码的逻辑数据结构从NV存储器读/写。 X是大于或等于1的整数。

2. 发明申请

WO2007084751A2 FLASH MEMORY WITH CODING AND SIGNAL PROCESSING 审中-公开
标题翻译：具有编码和信号处理的闪存
公开(公告)号：WO2007084751A2
公开(公告)日：2007-07-26
申请号：PCT/US2007/001623
申请日：2007-01-19
申请人： MARVELL WORLD TRADE LTD. , WU, Zining , SUTARDJA, Pantas
发明人： WU, Zining , SUTARDJA, Pantas
IPC分类号： G11C11/34 , G11C16/04 , G11C16/06
CPC分类号： G06F11/1072 , G06F11/1068 , G11C7/1006 , G11C7/16 , G11C11/56 , G11C29/00 , G11C2029/0411 , G11C2211/5641
摘要： A solid state non-volatile memory unit includes, in part, an encoder, a multi-level solid state non-volatile memory array adapted to store data encoded by the encoder, and a decoder adapted to decode the data retrieved from the memory array. The memory array may be a flash EEPROM array. The memory unit optionally includes a modulator and a demodulator. The data modulated by the modulator is stored in the memory array. The demodulator demodulates the modulated data retrieved from the memory array.
摘要翻译：固态非易失性存储器单元部分地包括编码器，适用于存储由编码器编码的数据的多级固态非易失性存储器阵列，以及适于对从存储器阵列检索的数据进行解码的解码器。存储器阵列可以是闪存EEPROM阵列。存储器单元可选地包括调制器和解调器。由调制器调制的数据被存储在存储器阵列中。解调器解调从存储器阵列检索的调制数据。

3. 发明申请

WO2008100529A2 PILOT PLACEMENT FOR NON-VOLATILE MEMORY 审中-公开
标题翻译：非易失性存储器的引导放置
公开(公告)号：WO2008100529A2
公开(公告)日：2008-08-21
申请号：PCT/US2008/001882
申请日：2008-02-12
申请人： MARVELL WORLD TRADE LTD. , YANG, Xueshi , WU, Zining , SUTARDJA, Pantas
发明人： YANG, Xueshi , WU, Zining , SUTARDJA, Pantas
CPC分类号： G06F11/1068 , G11C29/18 , G11C29/24 , G11C29/50 , G11C2029/0409 , G11C2029/0411 , G11C2029/5002
摘要： A memory control module includes a format module that communicates with a memory array that includes B memory blocks each including P physical pages and Q logical pages. The format module selects X predetermined locations to write pilot data and read-back pilot signals in each of the B memory blocks. B, P, Q and X are integers greater than or equal to 1. The memory control module also includes a signal processing module that compares the written pilot data to the read-back pilot signals and that determines variations between the written pilot data and the read-back pilot signals based on the comparison.
摘要翻译：存储器控制模块包括与包括B个存储器块的存储器阵列通信的格式模块，每个B存储器块包括P个物理页面和Q个逻辑页面。格式化模块选择X个预定位置以在每个B存储块中写入导频数据和读回导频信号。 B，P，Q和X是大于或等于1的整数。存储器控制模块还包括信号处理模块，其将写入的导频数据与读回导频信号进行比较，并确定写入的导频数据与基于比较的回读导频信号。

4. 发明申请

WO2008036378A3 RELIABILITY METRIC GENERATION FOR TRELLIS-BASED DETECTION AND/OR DECODING 审中-公开
标题翻译：基于TRLLIS的检测和/或解码的可靠性公制生成
公开(公告)号：WO2008036378A3
公开(公告)日：2008-05-15
申请号：PCT/US2007020423
申请日：2007-09-20
申请人： MARVELL WORLD TRADE LTD , YANG SHAOHUA , LOW SEO-HOW , WU ZINING , BURD GREGORY
发明人： YANG SHAOHUA , LOW SEO-HOW , WU ZINING , BURD GREGORY
IPC分类号： H03M13/41
CPC分类号： H03M13/4153 , H03M13/098 , H03M13/2933 , H04L25/03203 , H04L25/067
摘要： The disclosed technology provides methods and systems for determining reliability metrics for decoded or detected bits in the context of trellis based decoding or detection..The reliabilitiy metrics are obtained from path metric differences between winning and alternative paths in a decoding or detection trellis. Decoding or detection may be performed by means of a two-Viterbi system, wherein the first Viterbi determines path metric differences and the maximum-likelihood path and the second Viterbi determines alternative paths and reliability metrics by means of traceback.
摘要翻译：所公开的技术提供用于在基于网格的解码或检测的上下文中确定解码或检测到的比特的可靠性度量的方法和系统。可靠度量是从解码或检测网格中的获胜路径和替代路径之间的路径度量差异获得的。解码或检测可以通过双维特比系统来执行，其中第一维特比确定路径度量差异和最大似然路径，第二维特比通过回溯确定替代路径和可靠性度量。

5. 发明申请

WO2008048690A2 FORWARD DECISION AIDED NONLINEAR VITERBI DETECTOR 审中-公开
标题翻译：前瞻性决定非线性VITERBI检测器
公开(公告)号：WO2008048690A2
公开(公告)日：2008-04-24
申请号：PCT/US2007/022412
申请日：2007-10-18
申请人： MARVELL WORLD TRADE LTD. , YANG, Shaohua , WU, Zining
发明人： YANG, Shaohua , WU, Zining
CPC分类号： H03M13/4169 , G11B20/10009 , G11B20/10296 , H03M13/3961 , H03M13/41 , H03M13/6502
摘要： A system, apparatus, and method are provided for a nonlinear Viterbi detector that may be used in an iterative decoding system or any other system with multiple, interconnected detectors. At least one of the Viterbi detectors may estimate the digital information sequence in a received signal based on the signal itself and an estimate of the signal from another of the Viterbi detectors. The at least one Viterbi detector may calculate branch metrics for a subset of the branches in an associated trellis diagram by selecting branches that correspond to the output of the other Viterbi detector. Thus, the area and complexity of the at least one Viterbi detector may be reduced approximately two-fold or more.
摘要翻译：提供了一种用于非线性维特比检测器的系统，装置和方法，其可用于迭代解码系统或具有多个互连检测器的任何其它系统。维特比检测器中的至少一个可以基于信号本身估计接收信号中的数字信息序列，并且估计来自另一个维特比检测器的信号。所述至少一个维特比检测器可以通过选择与其他维特比检测器的输出相对应的分支来计算相关网格图中的分支子集的分支度量。因此，至少一个维特比检测器的面积和复杂度可以减小大约两倍或更多。

6. 发明申请

WO2008021045A3 SYSTEM AND METHOD FOR CORRECTING ERRORS IN NON-VOLATILE MEMORY USING PRODUCT CODES 审中-公开
标题翻译：用于使用产品代码来纠正非易失性存储器中的错误的系统和方法
公开(公告)号：WO2008021045A3
公开(公告)日：2008-04-17
申请号：PCT/US2007017450
申请日：2007-08-06
申请人： MARVELL WORLD TRADE LTD , WU ZINING , SUTARDJA PANTAS
发明人： WU ZINING , SUTARDJA PANTAS
IPC分类号： G11C29/52 , G06F11/10
CPC分类号： G11C29/52 , G06F11/1068
摘要： A product code encoder for non-volatile (NV) memory includes a first encoder that encodes data in codewords in a first dimension that is stored in the NV memory. The product code encoder also includes a second encoder that encodes data in codewords in a second dimension that is stored in the NV memory. A product code codeword is based on the codewords in the first dimension and the codewords in the second dimension.
摘要翻译：用于非易失性（NV）存储器的产品码编码器包括第一编码器，第一编码器对存储在NV存储器中的第一维中的码字中的数据进行编码。产品码编码器还包括第二编码器，其对存储在NV存储器中的第二维中的码字中的数据进行编码。产品码字是基于第一维中的码字和第二维中的码字。

7. 发明申请

WO2007084749A3 METHOD AND SYSTEM FOR ERROR CORRECTION IN FLASH MEMORY 审中-公开
标题翻译：闪存中错误校正的方法和系统
公开(公告)号：WO2007084749A3
公开(公告)日：2008-04-10
申请号：PCT/US2007001620
申请日：2007-01-19
申请人： MARVELL WORLD TRADE LTD , RAMAMOORTHY ADITYA , WU ZINING , SUTARDJA PANTAS
发明人： RAMAMOORTHY ADITYA , WU ZINING , SUTARDJA PANTAS
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G06F11/1068 , G06F11/1072 , G06F11/1666 , G06F2212/403 , G11C7/02 , G11C7/1006 , G11C7/16 , G11C11/56 , G11C11/5621 , G11C16/10 , G11C27/005 , G11C29/00 , G11C2029/0411 , G11C2207/16 , G11C2211/562 , G11C2211/563 , H03M13/1177 , H03M13/1515
摘要： A solid state non-volatile memory unit. The memory unit includes a multi-level solid state non-volatile memory array adapted to store data characterized by a first number of digital levels. The memory unit also includes an analog-to-digital converter having an input and an output. The input of the analog-to-digital converter is adapted to receive data from the multi-level solid state non-volatile memory array. The output of the analog-to-digital converter is adapted to output a digital signal characterized by a second number of digital levels greater than the first number of digital levels.
摘要翻译：固态非易失性存储器单元。存储单元包括适于存储以第一数量级数字表征的数据的多级固态非易失性存储器阵列。存储器单元还包括具有输入和输出的模拟 - 数字转换器。模拟 - 数字转换器的输入适于从多级固态非易失性存储器阵列接收数据。模拟 - 数字转换器的输出适于输出特征在于数字电平大于第一数字电平数量的第二数字电平的数字信号。

8. 发明申请

WO2007109262A2 METHOD AND APPARATUS FOR GENERATING NON-BINARY BALANCED CODES 审中-公开
标题翻译：用于生成非二进制平衡码的方法和装置
公开(公告)号：WO2007109262A2
公开(公告)日：2007-09-27
申请号：PCT/US2007006900
申请日：2007-03-20
申请人： MARVELL WORLD TRADE LTD , CHAICHANAVONG PANUE , WU ZINING
发明人： CHAICHANAVONG PANUE , WU ZINING
CPC分类号： H04L25/4919
摘要： An encoder and method of decoding includes a grouping module that groups an input signal into a plurality of blocks, wherein the plurality of blocks include a current block and at least one prior block, wherein each of the plurality of blocks includes at least N symbols, and wherein each of the N symbols has one of q symbol values, where N is a positive integer and q is an integer greater than two. The encoder further includes a counting module that counts occurrences of the q symbol values in the at least one prior block to generate a first count and occurrences of the q symbol values in the current block to generate a second count. The encoder also includes a permutation module that selectively permutes the current block based on the first and second counts.
摘要翻译：编码器和解码方法包括分组模块，其将输入信号分组成多个块，其中所述多个块包括当前块和至少一个先前块，其中所述多个块中的每一个包括至少N个符号，并且其中N个符号中的每一个具有q个符号值之一，其中N是正整数，q是大于2的整数。编码器还包括计数模块，其对至少一个先前块中的q个符号值的出现进行计数，以产生当前块中的第一计数和q个符号值的出现以产生第二计数。编码器还包括置换模块，其基于第一和第二计数选择性地排列当前块。

9. 发明申请

WO2016032817A1 STORAGE DEVICE CONTROLLER ARCHITECTURE 审中-公开
标题翻译：存储设备控制器架构
公开(公告)号：WO2016032817A1
公开(公告)日：2016-03-03
申请号：PCT/US2015/045872
申请日：2015-08-19
申请人： MARVELL WORLD TRADE LTD. , WU, Zining
发明人： WU, Zining
IPC分类号： G06F3/06
CPC分类号： G06F3/0647 , G06F3/061 , G06F3/0626 , G06F3/0658 , G06F3/067 , G06F3/0683 , G06F3/0688 , G06F11/073 , G06F11/0793
摘要： Data storage apparatus includes a plurality of drive units, each of the drive units including a plurality of memory channels, and a plurality of storage medium controllers. Each storage medium controller addresses at least one of the memory channels. Each of the storage medium controllers is incapable of performing file system operations. An integrated storage controller connected to each of the drive units performs all file system operations of the data storage apparatus. The integrated storage controller includes a central processing unit, a host interface, and at least one storage medium interface for communicating with the plurality of storage medium controllers. A method for operating such data storage apparatus includes performing, in the integrated storage controller, error correction across all of the memory channels, as well as redundancy and wear-leveling. Each storage medium controller may perform error correction across all of the memory channels addressed by that controller.
摘要翻译：数据存储装置包括多个驱动单元，每个驱动单元包括多个存储器通道，以及多个存储介质控制器。每个存储介质控制器寻址至少一个存储器通道。每个存储介质控制器都不能执行文件系统操作。连接到每个驱动单元的集成存储控制器执行数据存储装置的所有文件系统操作。集成存储控制器包括中央处理单元，主机接口和用于与多个存储介质控制器进行通信的至少一个存储介质接口。用于操作这种数据存储装置的方法包括在集成存储控制器中执行跨所有存储器通道的错误校正，以及冗余和磨损均衡。每个存储介质控制器可以在由该控制器寻址的所有存储器通道上执行纠错。

10. 发明申请

WO2009075831A2 ITERATIVE DECODER SYSTEMS AND METHODS 审中-公开
标题翻译：迭代解码器系统和方法
公开(公告)号：WO2009075831A2
公开(公告)日：2009-06-18
申请号：PCT/US2008013531
申请日：2008-12-08
申请人： MARVELL INT LTD , CHAICHANAVONG PANU , VARNICA NEDELJKO , NANGARE NITIN , BURD GREGORY , WU ZINING
发明人： CHAICHANAVONG PANU , VARNICA NEDELJKO , NANGARE NITIN , BURD GREGORY , WU ZINING
IPC分类号： G11B20/18 , H03M13/11 , H03M13/41
CPC分类号： H03M13/41 , G11B20/1426 , G11B20/1803 , G11B2020/10759 , G11B2020/1457 , H03M13/09 , H03M13/1105 , H03M13/1111 , H03M13/1114 , H03M13/13 , H03M13/29 , H03M13/2948 , H03M13/3746 , H03M13/4146 , H03M13/6343 , H03M13/6502 , H03M13/6561
摘要： Systems and methods are provided for improved designs and performance for iterative decoder systems. In some embodiments, the iterative decoder may be decoupled from FIR samples through an FIR RAM, thus resulting in a less complex design and shorter processing times. In some embodiments, an intermediate memory may be used when passing information between the SOVA and LDPC of the iterative decoder. In some embodiments, the SOVA-required information may be continuously serialized from information received from the LDPC during each LDPC iteration. In some embodiments, the 1/(1+D2) precoder of the HR RLL encoder may be split into two serial, 1/(1+D) precoders. One 1/(1+D) precoder may be pulled outside of the HR RLL encoder and used in conjunction with the iterative decoder. This may allow for a 1/(1+D) precoder that may be used with the iterative decoder while maintaining the RLL constraints imposed upon the encoded information by the HR RLL encoder.
摘要翻译：提供系统和方法用于改进迭代解码器系统的设计和性能。在一些实施例中，迭代解码器可以通过FIR RAM与FIR采样解耦，从而导致较不复杂的设计和较短的处理时间。在一些实施例中，当在迭代解码器的SOVA和LDPC之间传递信息时可以使用中间存储器。在一些实施例中，可以在每个LDPC迭代期间从从LDPC接收的信息连续地序列化SOVA需要的信息。在一些实施例中，HR RLL编码器的1 /（1 + D2）预编码器可以被分成两个串行1 /（1 + D）预编码器。一个1 /（1 + D）预编码器可以拉出HR RLL编码器的外部，并与迭代解码器一起使用。这可以允许可以与迭代解码器一起使用的1 /（1 + D）预编码器，同时保持由HR RLL编码器强加给编码信息的RLL约束。

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