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1. 发明申请

WO2014179001A1 METHOD AND APPARATUS FOR DIMMABLE LED DRIVER 审中-公开
标题翻译：二极管驱动器的方法和装置
公开(公告)号：WO2014179001A1
公开(公告)日：2014-11-06
申请号：PCT/US2014/033308
申请日：2014-04-08
申请人： MARVELL WORLD TRADE LTD , ZHANG, Wanfeng , REED, Daniel , CHOI, Jinho , SUTARDJA, Pantas
发明人： ZHANG, Wanfeng , REED, Daniel , CHOI, Jinho , SUTARDJA, Pantas
IPC分类号： H05B33/08
CPC分类号： H05B33/0845 , H05B33/0815 , H05B37/0263 , Y02B20/346
摘要： Aspects of the disclosure provide a method for driving dimmable load. The method includes detecting a dimming characteristic in an energy source from which a load draws a first energy according to the dimming characteristic. The dimming characteristic requires a second energy in addition to the first energy to be drawn from the energy source to sustain an operation of the energy source. The method further includes biasing a switch to consume the second energy. The second energy and the first energy are drawn from the energy source to sustain the operation of the energy source.
摘要翻译：本公开的方面提供了一种用于驱动可调光负载的方法。该方法包括检测能量源中的调光特性，负载根据调光特性从中抽取第一能量。调光特性除了从能源引出的第一能量之外还需要第二能量来维持能量源的操作。该方法还包括偏置开关以消耗第二能量。第二能量和第一能量来自能量源以维持能源的运行。

2. 发明申请

WO2014066462A4 APPARATUS AND METHOD FOR REFORMING RESISTIVE MEMORY CELLS 审中-公开
公开(公告)号：WO2014066462A4
公开(公告)日：2014-10-02
申请号：PCT/US2013066303
申请日：2013-10-23
申请人： MARVELL WORLD TRADE LTD , SUTARDJA PANTAS , WU ALBERT , LEE WINSTON , LEE PETER , CHANG RUNZI
发明人： SUTARDJA PANTAS , WU ALBERT , LEE WINSTON , LEE PETER , CHANG RUNZI
IPC分类号： G11C29/50 , G11C13/00
CPC分类号： G11C13/0069 , G11C11/16 , G11C13/00 , G11C13/0033 , G11C13/004 , G11C29/50008 , G11C2013/0076 , G11C2013/0083
摘要： A memory includes an array of memory cells, a first module and a second module. The first module is configured to compare a first state of a memory cell with a reference. The memory cell is in the array of memory cells. The second module is configured to, subsequent to a read cycle or a write cycle of the memory cell and based on the comparison, reform the memory cell to adjust a difference between the first state and a second state of the memory cell.

3. 发明申请

WO2013078311A4 FREQUENCY SCALING OF VARIABLE SPEED SYSTEMS FOR FAST RESPONSE AND POWER REDUCTION 审中-公开
标题翻译：用于快速响应和降低功率的变速系统的频率标定
公开(公告)号：WO2013078311A4
公开(公告)日：2013-07-18
申请号：PCT/US2012066257
申请日：2012-11-21
申请人： MARVELL WORLD TRADE LTD , SUTARDJA PANTAS , SUTARDJA SEHAT
发明人： SUTARDJA PANTAS , SUTARDJA SEHAT
IPC分类号： G06F1/08 , G06F1/32 , H03L7/00
CPC分类号： H03K3/02 , G06F1/08 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： A system including a plurality of amplifiers configured to generate a clock signal having a frequency. The clock signal is input to a processor. The amplifiers are connected in series. An output of a last one of the amplifiers is fed back to an input of a first one of the amplifiers. Each of the amplifiers has a transconductance. A frequency adjustment module is configured to adjust, based on an activity level of the processor, the frequency of the clock signal by adjusting the transconductance of the amplifiers.
摘要翻译：一种包括被配置为生成具有频率的时钟信号的多个放大器的系统。时钟信号被输入到处理器。放大器串联连接。最后一个放大器的输出被反馈到第一个放大器的输入端。每个放大器都有一个跨导。频率调整模块被配置为基于处理器的活动水平通过调整放大器的跨导来调整时钟信号的频率。

4. 发明申请

WO2013096456A1 METHOD AND APPARATUS FOR CURRENT CONTROL WITH LED DRIVER 审中-公开
标题翻译： LED驱动器电流控制方法与装置
公开(公告)号：WO2013096456A1
公开(公告)日：2013-06-27
申请号：PCT/US2012/070633
申请日：2012-12-19
申请人： MARVELL WORLD TRADE, LTD. , SUTARDJA, Pantas , OH, InHwan , ZHANG, Wanfeng
发明人： SUTARDJA, Pantas , OH, InHwan , ZHANG, Wanfeng
IPC分类号： H05B33/08
CPC分类号： H05B33/0809
摘要： Aspects of the disclosure provide a circuit that includes a detection circuit and a controller. The detection circuit is configured to detect a starting of a conduction in a power supply provided via an electronic transformer. The controller is configured to control a current regulating circuit to pull a current from the electronic transformer at a pre-determined level enough for triggering the triac dimmer during a time duration following the starting of the conduction, and pull the current at a reduced level according to a predetermined profile after the time duration.
摘要翻译：本公开的方面提供了包括检测电路和控制器的电路。检测电路被配置为检测经由电子变压器提供的电源中的导通开始。该控制器被配置为控制电流调节电路，以便在电流变换器的电流以足够的预定水平拉动电流，以便在导通开始之后的持续时间期间触发三端双向可控硅调光器，并且根据在时间段之后到预定的轮廓。

5. 发明申请

WO2011060248A4 CLOCK TURN-ON STRATEGY FOR POWER MANAGEMENT 审中-公开
标题翻译：电源管理的时钟开启策略
公开(公告)号：WO2011060248A4
公开(公告)日：2011-10-27
申请号：PCT/US2010056509
申请日：2010-11-12
申请人： MARVELL WORLD TRADE LTD , SUTARDJA PANTAS
发明人： SUTARDJA PANTAS
IPC分类号： G06F1/30 , G06F1/08
CPC分类号： G06F21/50 , G06F1/08 , G06F1/305
摘要： A system includes a voltage sensing module and a frequency adjustment module. The voltage sensing module is configured to sense a supply voltage of a circuit block, generate a first control signal when the supply voltage is less than or equal to a first voltage, and generate a second control signal when the supply voltage is within a predetermined range of a second voltage. The frequency adjustment module is configured to set a frequency of a clock signal supplied to the circuit block to less than a normal operating frequency of the circuit block when the supply voltage is initially supplied to the circuit block after a power on reset operation and the first control signal or the second control signal is received.
摘要翻译：一种系统包括电压感测模块和频率调整模块。电压感测模块被配置为感测电路块的电源电压，当电源电压小于或等于第一电压时产生第一控制信号，并且当电源电压在预定范围内时产生第二控制信号的第二电压。频率调节模块被配置为：当在电源接通复位操作之后将电源电压初始提供给电路块时，将提供给电路块的时钟信号的频率设置为小于电路块的正常工作频率，并且第一控制信号或第二控制信号被接收。

6. 发明申请

WO2010114806A1 POWER MANAGEMENT CIRCUIT FOR RECHARGEABLE BATTERY STACK 审中-公开
标题翻译：用于可充电电池堆栈的电源管理电路
公开(公告)号：WO2010114806A1
公开(公告)日：2010-10-07
申请号：PCT/US2010/029113
申请日：2010-03-30
申请人： MARVELL WORLD TRADE LTD. , SUTARDJA, Pantas
发明人： SUTARDJA, Pantas
IPC分类号： H02J7/00
CPC分类号： H02J7/0014 , Y02T10/7055
摘要： A charge-balancing system includes N circuits and a control module, where N is an integer greater than or equal to 1. Each of the N circuits includes first and second switches connected in series and an inductance having a first end connected between the first and second switches. The control module outputs control signals to control the first and second switches. A second end of the inductance of a first one of the N circuits is connected between two cells of a first pair of 2N series-connected cells of a battery stack. The first and second switches of the first one of the N circuits are connected in parallel to the first pair of 2N series-connected cells.
摘要翻译：电荷平衡系统包括N个电路和一个控制模块，其中N是大于或等于1的整数。N个电路中的每一个包括串联连接的第一和第二开关，以及电感，其第一端连接在第一和第二个开关控制模块输出控制信号以控制第一和第二开关。 N个电路中的第一个电路的电感的第二端连接在电池堆叠的第一对2N个串联连接的单元的两个单元之间。 N个电路中的第一个的第一和第二开关与第一对2N个串联的单元并联连接。

7. 发明申请

WO2009108619A1 FATIGUE MANAGEMENT SYSTEM AND METHOD FOR HYBRID NONVOLATILE SOLID STATE MEMORY SYSTEM 审中-公开
标题翻译：混合非线性固态记忆系统的疲劳管理系统和方法
公开(公告)号：WO2009108619A1
公开(公告)日：2009-09-03
申请号：PCT/US2009/034960
申请日：2009-02-24
申请人： MARVELL WORLD TRADE LTD. , SUTARDJA, Pantas
发明人： SUTARDJA, Pantas
IPC分类号： G11C16/34
CPC分类号： G06F12/0246 , G06F2212/1036 , G06F2212/7208 , G06F2212/7211 , G11C16/349 , G11C16/3495
摘要： A solid state memory system comprises a first nonvolatile semiconductor memory having a first write cycle lifetime and a first set of physical addresses, and a second nonvolatile semiconductor memory having a second write cycle lifetime and a second set of physical addresses. The first write cycle lifetime is greater than the second write cycle lifetime. The system further comprises a fatigue management module to generate a write frequency ranking for a plurality of logical addresses. The fatigue management module maps each of the plurality of logical addresses to a physical address of the first set of physical addresses or the second set of physical addresses based on the write frequency rankings.
摘要翻译：固态存储器系统包括具有第一写周期寿命和第一组物理地址的第一非易失性半导体存储器，以及具有第二写周期寿命和第二组物理地址的第二非易失性半导体存储器。第一个写周期寿命大于第二个写周期寿命。所述系统还包括疲劳管理模块，用于产生多个逻辑地址的写频率排序。疲劳管理模块基于写入频率排序将多个逻辑地址中的每一个映射到第一组物理地址的物理地址或第二组物理地址。

8. 发明申请

WO2008073421A3 HYBRID NON-VOLATILE SOLID STATE MEMORY SYSTEM 审中-公开
公开(公告)号：WO2008073421A3
公开(公告)日：2008-07-31
申请号：PCT/US2007025312
申请日：2007-12-11
申请人： MARVELL WORLD TRADE LTD , SUTARDJA PANTAS
发明人： SUTARDJA PANTAS
IPC分类号： G06F12/12 , G11C16/34
CPC分类号： G11C16/349 , G06F3/0616 , G06F3/0644 , G06F3/0679 , G06F12/0246 , G06F2212/1036 , G06F2212/7211 , G11C16/3495 , G11C2211/5641
摘要： A solid state memory system comprises a first nonvolatile semiconductor (NVS) memory that has a first write cycle lifetime, a second nonvolatile semiconductor (NVS) memory that has a second write cycle lifetime that is different than the first write cycle lifetime, and a wear leveling module. The wear leveling module generates first and second wear levels for the first and second NVS memories based on the first and second write cycle lifetimes and maps logical addresses to physical addresses of one of the first and second NVS memories based on the first and second wear levels.

9. 发明申请

WO2008013695A3 FILE SERVER FOR REDUNDANT ARRAY OF INDEPENDENT DISKS (RAID) SYSTEM 审中-公开
公开(公告)号：WO2008013695A3
公开(公告)日：2008-01-31
申请号：PCT/US2007/016159
申请日：2007-07-17
申请人： MARVELL WORLD TRADE LTD. , SUTARDJA, Pantas
发明人： SUTARDJA, Pantas
IPC分类号： G06F11/10
摘要： A redundant array of independent disks (RAID) system comprises N storage arrays. Each of the N storage arrays comprise a target processing module and 1 to M hard disk drives, where M and N are integers greater than 1. A data processing module assigns a first data storage request for a first data block to one of the target processing modules for processing of error checking and correcting (ECC) data for the first data block. The one of the target processing modules sends a first portion of the first data block and ECC data associated with the first data block to another of the target processing modules.

10. 发明申请

WO2007084751A3 FLASH MEMORY WITH CODING AND SIGNAL PROCESSING 审中-公开
标题翻译：具有编码和信号处理的闪存
公开(公告)号：WO2007084751A3
公开(公告)日：2008-01-10
申请号：PCT/US2007001623
申请日：2007-01-19
申请人： MARVELL WORLD TRADE LTD , WU ZINING , SUTARDJA PANTAS
发明人： WU ZINING , SUTARDJA PANTAS
IPC分类号： G11C11/34 , G11C16/04 , G11C16/06
CPC分类号： G06F11/1072 , G06F11/1068 , G11C7/1006 , G11C7/16 , G11C11/56 , G11C29/00 , G11C2029/0411 , G11C2211/5641
摘要： A solid state non-volatile memory unit includes, in part, an encoder, a multi-level solid state non-volatile memory array adapted to store data encoded by the encoder, and a decoder adapted to decode the data retrieved from the memory array. The memory array may be a flash EEPROM array. The memory unit optionally includes a modulator and a demodulator. The data modulated by the modulator is stored in the memory array. The demodulator demodulates the modulated data retrieved from the memory array.
摘要翻译：固态非易失性存储器单元部分地包括编码器，适用于存储由编码器编码的数据的多级固态非易失性存储器阵列，以及适于对从存储器阵列检索的数据进行解码的解码器。存储器阵列可以是闪存EEPROM阵列。存储器单元可选地包括调制器和解调器。由调制器调制的数据被存储在存储器阵列中。解调器解调从存储器阵列检索的调制数据。

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