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1. 发明申请

WO2008100529A2 PILOT PLACEMENT FOR NON-VOLATILE MEMORY 审中-公开
标题翻译：非易失性存储器的引导放置
公开(公告)号：WO2008100529A2
公开(公告)日：2008-08-21
申请号：PCT/US2008/001882
申请日：2008-02-12
申请人： MARVELL WORLD TRADE LTD. , YANG, Xueshi , WU, Zining , SUTARDJA, Pantas
发明人： YANG, Xueshi , WU, Zining , SUTARDJA, Pantas
CPC分类号： G06F11/1068 , G11C29/18 , G11C29/24 , G11C29/50 , G11C2029/0409 , G11C2029/0411 , G11C2029/5002
摘要： A memory control module includes a format module that communicates with a memory array that includes B memory blocks each including P physical pages and Q logical pages. The format module selects X predetermined locations to write pilot data and read-back pilot signals in each of the B memory blocks. B, P, Q and X are integers greater than or equal to 1. The memory control module also includes a signal processing module that compares the written pilot data to the read-back pilot signals and that determines variations between the written pilot data and the read-back pilot signals based on the comparison.
摘要翻译：存储器控制模块包括与包括B个存储器块的存储器阵列通信的格式模块，每个B存储器块包括P个物理页面和Q个逻辑页面。格式化模块选择X个预定位置以在每个B存储块中写入导频数据和读回导频信号。 B，P，Q和X是大于或等于1的整数。存储器控制模块还包括信号处理模块，其将写入的导频数据与读回导频信号进行比较，并确定写入的导频数据与基于比较的回读导频信号。

2. 发明申请

WO2007084751A2 FLASH MEMORY WITH CODING AND SIGNAL PROCESSING 审中-公开
标题翻译：具有编码和信号处理的闪存
公开(公告)号：WO2007084751A2
公开(公告)日：2007-07-26
申请号：PCT/US2007/001623
申请日：2007-01-19
申请人： MARVELL WORLD TRADE LTD. , WU, Zining , SUTARDJA, Pantas
发明人： WU, Zining , SUTARDJA, Pantas
IPC分类号： G11C11/34 , G11C16/04 , G11C16/06
CPC分类号： G06F11/1072 , G06F11/1068 , G11C7/1006 , G11C7/16 , G11C11/56 , G11C29/00 , G11C2029/0411 , G11C2211/5641
摘要： A solid state non-volatile memory unit includes, in part, an encoder, a multi-level solid state non-volatile memory array adapted to store data encoded by the encoder, and a decoder adapted to decode the data retrieved from the memory array. The memory array may be a flash EEPROM array. The memory unit optionally includes a modulator and a demodulator. The data modulated by the modulator is stored in the memory array. The demodulator demodulates the modulated data retrieved from the memory array.
摘要翻译：固态非易失性存储器单元部分地包括编码器，适用于存储由编码器编码的数据的多级固态非易失性存储器阵列，以及适于对从存储器阵列检索的数据进行解码的解码器。存储器阵列可以是闪存EEPROM阵列。存储器单元可选地包括调制器和解调器。由调制器调制的数据被存储在存储器阵列中。解调器解调从存储器阵列检索的调制数据。

3. 发明申请

WO2008021045A2 SYSTEM AND METHOD FOR CORRECTING ERRORS IN NON-VOLATILE MEMORY USING PRODUCT CODES 审中-公开
标题翻译：使用产品代码校正非易失性存储器中的错误的系统和方法
公开(公告)号：WO2008021045A2
公开(公告)日：2008-02-21
申请号：PCT/US2007/017450
申请日：2007-08-06
申请人： MARVELL WORLD TRADE LTD. , WU, Zining , SUTARDJA, Pantas
发明人： WU, Zining , SUTARDJA, Pantas
IPC分类号： G11C29/52 , G06F11/10
CPC分类号： G11C29/52 , G06F11/1068
摘要： A product code encoder for non-volatile (NV) memory includes a first encoder that encodes data in codewords in a first dimension that is stored in the NV memory. The product code encoder also includes a second encoder that encodes data in codewords in a second dimension that is stored in the NV memory. A product code codeword is based on the codewords in the first dimension and the codewords in the second dimension.
摘要翻译：用于非易失性（NV）存储器的产品代码编码器包括编码存储在NV存储器中的第一维中的码字中的数据的第一编码器。产品代码编码器还包括编码存储在NV存储器中的第二维度中的码字中的数据的第二编码器。产品代码码字基于第一维度中的码字和第二维度中的码字。

4. 发明申请

WO2008100415A4 NONVOLATILE MEMORY SYSTEM 审中-公开
公开(公告)号：WO2008100415A4
公开(公告)日：2008-08-21
申请号：PCT/US2008/001669
申请日：2008-02-08
申请人： MARVELL WORLD TRADE LTD. , WU, Zining , NGUYEN, Lau , SUTARDJA, Pantas , LEE, Chi-Kong , YOON, Tony
发明人： WU, Zining , NGUYEN, Lau , SUTARDJA, Pantas , LEE, Chi-Kong , YOON, Tony
IPC分类号： G06F11/10
摘要： A nonvolatile (NV) memory system includes a memory control module that encodes data to provide encoded logical data structures. The system also includes NV memory that includes X arrays that include physical data structures that differ in size from the encoded logical data structures. The memory control module writes/reads from the NV memory according to the encoded logical data structures. X is an integer greater than or equal to 1.

5. 发明申请

WO2007084749A2 METHOD AND SYSTEM FOR ERROR CORRECTION IN FLASH MEMORY 审中-公开
标题翻译：闪存中错误校正的方法和系统
公开(公告)号：WO2007084749A2
公开(公告)日：2007-07-26
申请号：PCT/US2007/001620
申请日：2007-01-19
申请人： MARVELL WORLD TRADE LTD. , RAMAMOORTHY, Aditya , WU, Zining , SUTARDJA, Pantas
发明人： RAMAMOORTHY, Aditya , WU, Zining , SUTARDJA, Pantas
IPC分类号： G11C16/04
CPC分类号： G06F11/1068 , G06F11/1072 , G06F11/1666 , G06F2212/403 , G11C7/02 , G11C7/1006 , G11C7/16 , G11C11/56 , G11C11/5621 , G11C16/10 , G11C27/005 , G11C29/00 , G11C2029/0411 , G11C2207/16 , G11C2211/562 , G11C2211/563 , H03M13/1177 , H03M13/1515
摘要： A solid state non-volatile memory unit. The memory unit includes a multi-level solid state non-volatile memory array adapted to store data characterized by a first number of digital levels. The memory unit also includes an analog-to-digital converter having an input and an output. The input of the analog-to-digital converter is adapted to receive data from the multi-level solid state non-volatile memory array. The output of the analog-to-digital converter is adapted to output a digital signal characterized by a second number of digital levels greater than the first number of digital levels.
摘要翻译：固态非易失性存储器单元。存储单元包括适于存储以第一数量级数字表征的数据的多级固态非易失性存储器阵列。存储器单元还包括具有输入和输出的模拟 - 数字转换器。模拟 - 数字转换器的输入适于从多级固态非易失性存储器阵列接收数据。模拟 - 数字转换器的输出适于输出特征在于数字电平大于第一数字电平数量的第二数字电平的数字信号。

6. 发明申请

WO2009021065A1 ENCODING AND DECODING USING GENERALIZED CONCATENATED CODES (GCC) 审中-公开
标题翻译：使用通用的编码（GCC）编码和解码
公开(公告)号：WO2009021065A1
公开(公告)日：2009-02-12
申请号：PCT/US2008/072373
申请日：2008-08-06
申请人： MARVELL WORLD TRADE LTD. , YANG, Xueshi , BURD, Gregory , TANG, Heng , CHAICHANAVONG, Panu , WU, Zining
发明人： YANG, Xueshi , BURD, Gregory , TANG, Heng , CHAICHANAVONG, Panu , WU, Zining
IPC分类号： H03M13/29
CPC分类号： H03M13/2945 , G06F11/1068 , H03M13/033 , H03M13/1515 , H03M13/2903 , H03M13/2906
摘要： Systems, apparatuses, and methods for encoding and decoding using generalized concatenated codes (GCC) are described. The methods include receiving data; encoding the received data to obtain first encoded data; encoding the first encoded data until a GCC encoding reaches an intermediate level; and terminating the GCC encoding at the intermediate level. Hence, the number of outer codes is reduced by replacing the last layer (s) of outer code (s) by uncoded symbols. The GCC codes may be concatenated with an outer-layer code or an inner-layer code.
摘要翻译：描述使用广义级联码（GCC）的编码和解码的系统，装置和方法。方法包括接收数据; 对所接收的数据进行编码以获得第一编码数据; 对第一编码数据进行编码，直到GCC编码达到中间级; 并终止中级的GCC编码。因此，通过用未编码的符号代替外部码的最后一层来减少外部码的数量。 GCC代码可以与外层代码或内层代码连接。

7. 发明申请

WO2009105153A1 SYSTEMS AND METHODS FOR PERFORMING CONCATENATED ERROR CORRECTION 审中-公开
标题翻译：用于执行定向错误校正的系统和方法
公开(公告)号：WO2009105153A1
公开(公告)日：2009-08-27
申请号：PCT/US2009/000632
申请日：2009-01-30
申请人： MARVELL WORLD TRADE LTD. , YANG, Xueshi , WU, Zining , LOW, Seo-how
发明人： YANG, Xueshi , WU, Zining , LOW, Seo-how
IPC分类号： H03M13/00
CPC分类号： H03M13/2927 , G06F11/1072 , H03M13/152 , H03M13/2903 , H03M13/2906
摘要： A system and method is provided for performing concatenated error correction. In one implementation, an apparatus for encoding data includes an outer encoder to generate a code word corresponding to received input data and a parity circuit to compute parities of logical cells of data, the logical cells of data being obtained from the code word and having a first logical cell. The apparatus also includes an inner encoder to generate an error correction bit for the first logical cell based on a first parity corresponding to the first logical cell, and to insert the error correction bit in the first logical cell.
摘要翻译：提供了一种用于执行串联纠错的系统和方法。在一个实施方式中，用于编码数据的装置包括外编码器，用于产生与所接收的输入数据相对应的代码字，以及奇偶校验电路来计算数据的逻辑单元的奇偶校验，数据的逻辑单元从代码字获得并具有第一个逻辑单元。该装置还包括内编码器，用于基于与第一逻辑单元相对应的第一奇偶校验位产生第一逻辑单元的纠错位，并将误差校正位插入第一逻辑单元。

8. 发明申请

WO2009075918A1 SEQUENCE DETECTION FOR FLASH MEMORY WITH INTER-CELL INTERFERENCE 审中-公开
标题翻译：具有细胞间干扰的闪存的序列检测
公开(公告)号：WO2009075918A1
公开(公告)日：2009-06-18
申请号：PCT/US2008/074414
申请日：2008-08-27
申请人： MARVELL WORLD TRADE LTD. , YANG, Xueshi , WU, Zining
发明人： YANG, Xueshi , WU, Zining
IPC分类号： G11C7/02 , G11C7/10
CPC分类号： G11C16/04 , G11C7/02 , G11C7/14 , G11C16/06 , G11C16/26 , G11C16/3418 , G11C16/3422
摘要： A memory integrated circuit (IC) includes a read module and a sequence detector module. The read module reads S memory cells (cells) located along one of a bit line and a word line and generates S read signals, where S is an integer greater than 1. The sequence detector module detects a data sequence based on the S read signals and reference signals. The data sequence includes data stored in the S cells. Each of the reference signals includes an interference-free signal associated with one of the S cells and an interference signal associated with another of the S cells that is adjacent to the one of the S cells.
摘要翻译：存储器集成电路（IC）包括读取模块和序列检测器模块。读取模块读取沿着位线和字线中的一个位置的S个存储单元（单元），并产生S个读取信号，其中S是大于1的整数。序列检测器模块基于S个读取信号来检测数据序列和参考信号。数据序列包括存储在S单元中的数据。每个参考信号包括与S个小区中的一个相关联的无干扰信号和与S个小区之一相邻的S个小区中的另一个的干扰信号。

9. 发明申请

WO2008045292A2 ERROR CORRECTION DECODING METHODS AND APPARATUS 审中-公开
标题翻译：误差校正解码方法和装置
公开(公告)号：WO2008045292A2
公开(公告)日：2008-04-17
申请号：PCT/US2007/021333
申请日：2007-10-04
申请人： MARVELL WORLD TRADE LTD. , YANG, Xueshi , WU, Zining , TANG, Heng
发明人： YANG, Xueshi , WU, Zining , TANG, Heng
IPC分类号： H04L1/00
CPC分类号： H04L1/0052 , H03M13/1515 , H03M13/152 , H03M13/19 , H03M13/2909 , H03M13/293 , H04L1/0065
摘要： A method and system for error correction decoding uses concatenated error correction decoders. A channel decoder receives encoded user data from a transmission channel, decodes the bits of the user data, and generates erasure information for the decoded bits. The decoded bits and erasure information is received by an outer ECC decoder, which first performs erasure decoding. If the erasure decoding is successful, then the decoded user data is output. If the erasure decoding is not successful, then the outer ECC decoder performs the more complex error decoding. Thus, error decoding need not be performed for user data that can be successfully decoded using erasure decoding. The extra operations required to perform error decoding is avoided. In this manner, the complexity of the overall decoding process is reduced, significantly reducing the computation power required, while maintaining the desired performance level.
摘要翻译：用于纠错解码的方法和系统使用级联纠错解码器。信道解码器从传输信道接收编码的用户数据，对用户数据的比特进行解码，并且生成解码比特的擦除信息。解码的比特和擦除信息由首先执行擦除解码的外部ECC解码器接收。如果擦除解码成功，则输出解码后的用户数据。如果擦除解码不成功，则外部ECC解码器执行更复杂的错误解码。因此，不需要针对可以使用擦除解码成功解码的用户数据执行错误解码。避免执行错误解码所需的额外操作。以这种方式，整个解码过程的复杂度降低，大大降低了所需的计算能力，同时保持了所需的性能水平。

10. 发明申请

WO2008045893A1 ADAPTIVE SYSTEMS AND METHODS FOR STORING AND RETRIEVING DATA TO AND FROM MEMORY CELLS 审中-公开
标题翻译：用于存储和从存储器存储数据的自适应系统和方法
公开(公告)号：WO2008045893A1
公开(公告)日：2008-04-17
申请号：PCT/US2007/080845
申请日：2007-10-09
申请人： MARVELL WORLD TRADE LTD. , YANG, Xueshi , WU, Zining
发明人： YANG, Xueshi , WU, Zining
IPC分类号： G06F11/10
CPC分类号： G06F11/1048
摘要： Adaptive systems and methods that may help assure the reliability of data retrieved from memory cells are described herein. The systems may include a memory device including a plurality of memory cells, a data quality monitoring block, and an adaptive data encoding block, the data quality monitoring block and the adaptive data encoding block both being operatively coupled to the memory device. The data quality monitoring block may be configured to determine a quality value of a group of one or more memory cells included in the memory device, the determined quality value being indicative of a quality of the group of one or more memory cells. The adaptive data encoding block may be configured to select a coding scheme from a plurality of coding schemes to encode data to be written to the group of one or more memory cells in the memory device, the selection of the coding scheme being based at least in part on the determined quality value of the group of one or more memory cells.
摘要翻译：这里描述了可能有助于确保从存储器单元检索的数据的可靠性的自适应系统和方法。系统可以包括包括多个存储器单元，数据质量监控块和自适应数据编码块的存储器件，数据质量监控块和自适应数据编码块都可操作地耦合到存储器件。数据质量监测块可以被配置为确定存储器件中包括的一个或多个存储器单元的组的质量值，所确定的质量值指示一个或多个存储器单元的组的质量。自适应数据编码块可以被配置为从多个编码方案中选择编码方案来编码要写入存储器件中的一个或多个存储器单元的组的数据，编码方案的选择至少基于部分是确定的一个或多个存储单元的组的质量值。

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