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1. 发明申请

WO2007084751A2 FLASH MEMORY WITH CODING AND SIGNAL PROCESSING 审中-公开
标题翻译：具有编码和信号处理的闪存
公开(公告)号：WO2007084751A2
公开(公告)日：2007-07-26
申请号：PCT/US2007/001623
申请日：2007-01-19
申请人： MARVELL WORLD TRADE LTD. , WU, Zining , SUTARDJA, Pantas
发明人： WU, Zining , SUTARDJA, Pantas
IPC分类号： G11C11/34 , G11C16/04 , G11C16/06
CPC分类号： G06F11/1072 , G06F11/1068 , G11C7/1006 , G11C7/16 , G11C11/56 , G11C29/00 , G11C2029/0411 , G11C2211/5641
摘要： A solid state non-volatile memory unit includes, in part, an encoder, a multi-level solid state non-volatile memory array adapted to store data encoded by the encoder, and a decoder adapted to decode the data retrieved from the memory array. The memory array may be a flash EEPROM array. The memory unit optionally includes a modulator and a demodulator. The data modulated by the modulator is stored in the memory array. The demodulator demodulates the modulated data retrieved from the memory array.
摘要翻译：固态非易失性存储器单元部分地包括编码器，适用于存储由编码器编码的数据的多级固态非易失性存储器阵列，以及适于对从存储器阵列检索的数据进行解码的解码器。存储器阵列可以是闪存EEPROM阵列。存储器单元可选地包括调制器和解调器。由调制器调制的数据被存储在存储器阵列中。解调器解调从存储器阵列检索的调制数据。

2. 发明申请

WO2008021045A2 SYSTEM AND METHOD FOR CORRECTING ERRORS IN NON-VOLATILE MEMORY USING PRODUCT CODES 审中-公开
标题翻译：使用产品代码校正非易失性存储器中的错误的系统和方法
公开(公告)号：WO2008021045A2
公开(公告)日：2008-02-21
申请号：PCT/US2007/017450
申请日：2007-08-06
申请人： MARVELL WORLD TRADE LTD. , WU, Zining , SUTARDJA, Pantas
发明人： WU, Zining , SUTARDJA, Pantas
IPC分类号： G11C29/52 , G06F11/10
CPC分类号： G11C29/52 , G06F11/1068
摘要： A product code encoder for non-volatile (NV) memory includes a first encoder that encodes data in codewords in a first dimension that is stored in the NV memory. The product code encoder also includes a second encoder that encodes data in codewords in a second dimension that is stored in the NV memory. A product code codeword is based on the codewords in the first dimension and the codewords in the second dimension.
摘要翻译：用于非易失性（NV）存储器的产品代码编码器包括编码存储在NV存储器中的第一维中的码字中的数据的第一编码器。产品代码编码器还包括编码存储在NV存储器中的第二维度中的码字中的数据的第二编码器。产品代码码字基于第一维度中的码字和第二维度中的码字。

3. 发明申请

WO2008100529A2 PILOT PLACEMENT FOR NON-VOLATILE MEMORY 审中-公开
标题翻译：非易失性存储器的引导放置
公开(公告)号：WO2008100529A2
公开(公告)日：2008-08-21
申请号：PCT/US2008/001882
申请日：2008-02-12
申请人： MARVELL WORLD TRADE LTD. , YANG, Xueshi , WU, Zining , SUTARDJA, Pantas
发明人： YANG, Xueshi , WU, Zining , SUTARDJA, Pantas
CPC分类号： G06F11/1068 , G11C29/18 , G11C29/24 , G11C29/50 , G11C2029/0409 , G11C2029/0411 , G11C2029/5002
摘要： A memory control module includes a format module that communicates with a memory array that includes B memory blocks each including P physical pages and Q logical pages. The format module selects X predetermined locations to write pilot data and read-back pilot signals in each of the B memory blocks. B, P, Q and X are integers greater than or equal to 1. The memory control module also includes a signal processing module that compares the written pilot data to the read-back pilot signals and that determines variations between the written pilot data and the read-back pilot signals based on the comparison.
摘要翻译：存储器控制模块包括与包括B个存储器块的存储器阵列通信的格式模块，每个B存储器块包括P个物理页面和Q个逻辑页面。格式化模块选择X个预定位置以在每个B存储块中写入导频数据和读回导频信号。 B，P，Q和X是大于或等于1的整数。存储器控制模块还包括信号处理模块，其将写入的导频数据与读回导频信号进行比较，并确定写入的导频数据与基于比较的回读导频信号。

4. 发明申请

WO2008100415A4 NONVOLATILE MEMORY SYSTEM 审中-公开
公开(公告)号：WO2008100415A4
公开(公告)日：2008-08-21
申请号：PCT/US2008/001669
申请日：2008-02-08
申请人： MARVELL WORLD TRADE LTD. , WU, Zining , NGUYEN, Lau , SUTARDJA, Pantas , LEE, Chi-Kong , YOON, Tony
发明人： WU, Zining , NGUYEN, Lau , SUTARDJA, Pantas , LEE, Chi-Kong , YOON, Tony
IPC分类号： G06F11/10
摘要： A nonvolatile (NV) memory system includes a memory control module that encodes data to provide encoded logical data structures. The system also includes NV memory that includes X arrays that include physical data structures that differ in size from the encoded logical data structures. The memory control module writes/reads from the NV memory according to the encoded logical data structures. X is an integer greater than or equal to 1.

5. 发明申请

WO2007084749A2 METHOD AND SYSTEM FOR ERROR CORRECTION IN FLASH MEMORY 审中-公开
标题翻译：闪存中错误校正的方法和系统
公开(公告)号：WO2007084749A2
公开(公告)日：2007-07-26
申请号：PCT/US2007/001620
申请日：2007-01-19
申请人： MARVELL WORLD TRADE LTD. , RAMAMOORTHY, Aditya , WU, Zining , SUTARDJA, Pantas
发明人： RAMAMOORTHY, Aditya , WU, Zining , SUTARDJA, Pantas
IPC分类号： G11C16/04
CPC分类号： G06F11/1068 , G06F11/1072 , G06F11/1666 , G06F2212/403 , G11C7/02 , G11C7/1006 , G11C7/16 , G11C11/56 , G11C11/5621 , G11C16/10 , G11C27/005 , G11C29/00 , G11C2029/0411 , G11C2207/16 , G11C2211/562 , G11C2211/563 , H03M13/1177 , H03M13/1515
摘要： A solid state non-volatile memory unit. The memory unit includes a multi-level solid state non-volatile memory array adapted to store data characterized by a first number of digital levels. The memory unit also includes an analog-to-digital converter having an input and an output. The input of the analog-to-digital converter is adapted to receive data from the multi-level solid state non-volatile memory array. The output of the analog-to-digital converter is adapted to output a digital signal characterized by a second number of digital levels greater than the first number of digital levels.
摘要翻译：固态非易失性存储器单元。存储单元包括适于存储以第一数量级数字表征的数据的多级固态非易失性存储器阵列。存储器单元还包括具有输入和输出的模拟 - 数字转换器。模拟 - 数字转换器的输入适于从多级固态非易失性存储器阵列接收数据。模拟 - 数字转换器的输出适于输出特征在于数字电平大于第一数字电平数量的第二数字电平的数字信号。

6. 发明申请

WO2014179001A1 METHOD AND APPARATUS FOR DIMMABLE LED DRIVER 审中-公开
标题翻译：二极管驱动器的方法和装置
公开(公告)号：WO2014179001A1
公开(公告)日：2014-11-06
申请号：PCT/US2014/033308
申请日：2014-04-08
申请人： MARVELL WORLD TRADE LTD , ZHANG, Wanfeng , REED, Daniel , CHOI, Jinho , SUTARDJA, Pantas
发明人： ZHANG, Wanfeng , REED, Daniel , CHOI, Jinho , SUTARDJA, Pantas
IPC分类号： H05B33/08
CPC分类号： H05B33/0845 , H05B33/0815 , H05B37/0263 , Y02B20/346
摘要： Aspects of the disclosure provide a method for driving dimmable load. The method includes detecting a dimming characteristic in an energy source from which a load draws a first energy according to the dimming characteristic. The dimming characteristic requires a second energy in addition to the first energy to be drawn from the energy source to sustain an operation of the energy source. The method further includes biasing a switch to consume the second energy. The second energy and the first energy are drawn from the energy source to sustain the operation of the energy source.
摘要翻译：本公开的方面提供了一种用于驱动可调光负载的方法。该方法包括检测能量源中的调光特性，负载根据调光特性从中抽取第一能量。调光特性除了从能源引出的第一能量之外还需要第二能量来维持能量源的操作。该方法还包括偏置开关以消耗第二能量。第二能量和第一能量来自能量源以维持能源的运行。

7. 发明申请

WO2013096456A1 METHOD AND APPARATUS FOR CURRENT CONTROL WITH LED DRIVER 审中-公开
标题翻译： LED驱动器电流控制方法与装置
公开(公告)号：WO2013096456A1
公开(公告)日：2013-06-27
申请号：PCT/US2012/070633
申请日：2012-12-19
申请人： MARVELL WORLD TRADE, LTD. , SUTARDJA, Pantas , OH, InHwan , ZHANG, Wanfeng
发明人： SUTARDJA, Pantas , OH, InHwan , ZHANG, Wanfeng
IPC分类号： H05B33/08
CPC分类号： H05B33/0809
摘要： Aspects of the disclosure provide a circuit that includes a detection circuit and a controller. The detection circuit is configured to detect a starting of a conduction in a power supply provided via an electronic transformer. The controller is configured to control a current regulating circuit to pull a current from the electronic transformer at a pre-determined level enough for triggering the triac dimmer during a time duration following the starting of the conduction, and pull the current at a reduced level according to a predetermined profile after the time duration.
摘要翻译：本公开的方面提供了包括检测电路和控制器的电路。检测电路被配置为检测经由电子变压器提供的电源中的导通开始。该控制器被配置为控制电流调节电路，以便在电流变换器的电流以足够的预定水平拉动电流，以便在导通开始之后的持续时间期间触发三端双向可控硅调光器，并且根据在时间段之后到预定的轮廓。

8. 发明申请

WO2010114806A1 POWER MANAGEMENT CIRCUIT FOR RECHARGEABLE BATTERY STACK 审中-公开
标题翻译：用于可充电电池堆栈的电源管理电路
公开(公告)号：WO2010114806A1
公开(公告)日：2010-10-07
申请号：PCT/US2010/029113
申请日：2010-03-30
申请人： MARVELL WORLD TRADE LTD. , SUTARDJA, Pantas
发明人： SUTARDJA, Pantas
IPC分类号： H02J7/00
CPC分类号： H02J7/0014 , Y02T10/7055
摘要： A charge-balancing system includes N circuits and a control module, where N is an integer greater than or equal to 1. Each of the N circuits includes first and second switches connected in series and an inductance having a first end connected between the first and second switches. The control module outputs control signals to control the first and second switches. A second end of the inductance of a first one of the N circuits is connected between two cells of a first pair of 2N series-connected cells of a battery stack. The first and second switches of the first one of the N circuits are connected in parallel to the first pair of 2N series-connected cells.
摘要翻译：电荷平衡系统包括N个电路和一个控制模块，其中N是大于或等于1的整数。N个电路中的每一个包括串联连接的第一和第二开关，以及电感，其第一端连接在第一和第二个开关控制模块输出控制信号以控制第一和第二开关。 N个电路中的第一个电路的电感的第二端连接在电池堆叠的第一对2N个串联连接的单元的两个单元之间。 N个电路中的第一个的第一和第二开关与第一对2N个串联的单元并联连接。

9. 发明申请

WO2009108619A1 FATIGUE MANAGEMENT SYSTEM AND METHOD FOR HYBRID NONVOLATILE SOLID STATE MEMORY SYSTEM 审中-公开
标题翻译：混合非线性固态记忆系统的疲劳管理系统和方法
公开(公告)号：WO2009108619A1
公开(公告)日：2009-09-03
申请号：PCT/US2009/034960
申请日：2009-02-24
申请人： MARVELL WORLD TRADE LTD. , SUTARDJA, Pantas
发明人： SUTARDJA, Pantas
IPC分类号： G11C16/34
CPC分类号： G06F12/0246 , G06F2212/1036 , G06F2212/7208 , G06F2212/7211 , G11C16/349 , G11C16/3495
摘要： A solid state memory system comprises a first nonvolatile semiconductor memory having a first write cycle lifetime and a first set of physical addresses, and a second nonvolatile semiconductor memory having a second write cycle lifetime and a second set of physical addresses. The first write cycle lifetime is greater than the second write cycle lifetime. The system further comprises a fatigue management module to generate a write frequency ranking for a plurality of logical addresses. The fatigue management module maps each of the plurality of logical addresses to a physical address of the first set of physical addresses or the second set of physical addresses based on the write frequency rankings.
摘要翻译：固态存储器系统包括具有第一写周期寿命和第一组物理地址的第一非易失性半导体存储器，以及具有第二写周期寿命和第二组物理地址的第二非易失性半导体存储器。第一个写周期寿命大于第二个写周期寿命。所述系统还包括疲劳管理模块，用于产生多个逻辑地址的写频率排序。疲劳管理模块基于写入频率排序将多个逻辑地址中的每一个映射到第一组物理地址的物理地址或第二组物理地址。

10. 发明申请

WO2008013695A3 FILE SERVER FOR REDUNDANT ARRAY OF INDEPENDENT DISKS (RAID) SYSTEM 审中-公开
公开(公告)号：WO2008013695A3
公开(公告)日：2008-01-31
申请号：PCT/US2007/016159
申请日：2007-07-17
申请人： MARVELL WORLD TRADE LTD. , SUTARDJA, Pantas
发明人： SUTARDJA, Pantas
IPC分类号： G06F11/10
摘要： A redundant array of independent disks (RAID) system comprises N storage arrays. Each of the N storage arrays comprise a target processing module and 1 to M hard disk drives, where M and N are integers greater than 1. A data processing module assigns a first data storage request for a first data block to one of the target processing modules for processing of error checking and correcting (ECC) data for the first data block. The one of the target processing modules sends a first portion of the first data block and ECC data associated with the first data block to another of the target processing modules.

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