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1. 发明申请

WO2007084749A3 METHOD AND SYSTEM FOR ERROR CORRECTION IN FLASH MEMORY 审中-公开
标题翻译：闪存中错误校正的方法和系统
公开(公告)号：WO2007084749A3
公开(公告)日：2008-04-10
申请号：PCT/US2007001620
申请日：2007-01-19
申请人： MARVELL WORLD TRADE LTD , RAMAMOORTHY ADITYA , WU ZINING , SUTARDJA PANTAS
发明人： RAMAMOORTHY ADITYA , WU ZINING , SUTARDJA PANTAS
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G06F11/1068 , G06F11/1072 , G06F11/1666 , G06F2212/403 , G11C7/02 , G11C7/1006 , G11C7/16 , G11C11/56 , G11C11/5621 , G11C16/10 , G11C27/005 , G11C29/00 , G11C2029/0411 , G11C2207/16 , G11C2211/562 , G11C2211/563 , H03M13/1177 , H03M13/1515
摘要： A solid state non-volatile memory unit. The memory unit includes a multi-level solid state non-volatile memory array adapted to store data characterized by a first number of digital levels. The memory unit also includes an analog-to-digital converter having an input and an output. The input of the analog-to-digital converter is adapted to receive data from the multi-level solid state non-volatile memory array. The output of the analog-to-digital converter is adapted to output a digital signal characterized by a second number of digital levels greater than the first number of digital levels.
摘要翻译：固态非易失性存储器单元。存储单元包括适于存储以第一数量级数字表征的数据的多级固态非易失性存储器阵列。存储器单元还包括具有输入和输出的模拟 - 数字转换器。模拟 - 数字转换器的输入适于从多级固态非易失性存储器阵列接收数据。模拟 - 数字转换器的输出适于输出特征在于数字电平大于第一数字电平数量的第二数字电平的数字信号。

2. 发明申请

WO2008100415A3 NONVOLATILE MEMORY SYSTEM 审中-公开
标题翻译：非易失性存储系统
公开(公告)号：WO2008100415A3
公开(公告)日：2008-11-27
申请号：PCT/US2008001669
申请日：2008-02-08
申请人： MARVELL WORLD TRADE LTD , WU ZINING , NGUYEN LAU , SUTARDJA PANTAS , LEE CHI-KONG , YOON TONY
发明人： WU ZINING , NGUYEN LAU , SUTARDJA PANTAS , LEE CHI-KONG , YOON TONY
IPC分类号： G06F11/10
CPC分类号： G06F3/0688 , G06F3/0619 , G06F3/0661 , G06F11/1068 , G06F12/0246
摘要： A nonvolatile (NV) memory system includes a memory control module that encodes data to provide encoded logical data structures. The system also includes NV memory that includes X arrays that include physical data structures that differ in size from the encoded logical data structures. The memory control module writes/reads from the NV memory according to the encoded logical data structures. X is an integer greater than or equal to 1.
摘要翻译：非易失性（NV）存储器系统包括对数据进行编码以提供编码的逻辑数据结构的存储器控制模块。该系统还包括NV存储器，其包括X阵列，其包括与编码的逻辑数据结构不同的物理数据结构。存储器控制模块根据编码的逻辑数据结构从NV存储器读/写。 X是大于或等于1的整数。

3. 发明申请

WO2007084751A3 FLASH MEMORY WITH CODING AND SIGNAL PROCESSING 审中-公开
标题翻译：具有编码和信号处理的闪存
公开(公告)号：WO2007084751A3
公开(公告)日：2008-01-10
申请号：PCT/US2007001623
申请日：2007-01-19
申请人： MARVELL WORLD TRADE LTD , WU ZINING , SUTARDJA PANTAS
发明人： WU ZINING , SUTARDJA PANTAS
IPC分类号： G11C11/34 , G11C16/04 , G11C16/06
CPC分类号： G06F11/1072 , G06F11/1068 , G11C7/1006 , G11C7/16 , G11C11/56 , G11C29/00 , G11C2029/0411 , G11C2211/5641
摘要： A solid state non-volatile memory unit includes, in part, an encoder, a multi-level solid state non-volatile memory array adapted to store data encoded by the encoder, and a decoder adapted to decode the data retrieved from the memory array. The memory array may be a flash EEPROM array. The memory unit optionally includes a modulator and a demodulator. The data modulated by the modulator is stored in the memory array. The demodulator demodulates the modulated data retrieved from the memory array.
摘要翻译：固态非易失性存储器单元部分地包括编码器，适用于存储由编码器编码的数据的多级固态非易失性存储器阵列，以及适于对从存储器阵列检索的数据进行解码的解码器。存储器阵列可以是闪存EEPROM阵列。存储器单元可选地包括调制器和解调器。由调制器调制的数据被存储在存储器阵列中。解调器解调从存储器阵列检索的调制数据。

4. 发明申请

WO2008100529A3 PILOT PLACEMENT FOR NON-VOLATILE MEMORY 审中-公开
标题翻译：非易失性存储器的导引放置
公开(公告)号：WO2008100529A3
公开(公告)日：2008-11-27
申请号：PCT/US2008001882
申请日：2008-02-12
申请人： MARVELL WORLD TRADE LTD , YANG XUESHI , WU ZINING , SUTARDJA PANTAS
发明人： YANG XUESHI , WU ZINING , SUTARDJA PANTAS
IPC分类号： G06F11/10 , G11C29/00
CPC分类号： G06F11/1068 , G11C29/18 , G11C29/24 , G11C29/50 , G11C2029/0409 , G11C2029/0411 , G11C2029/5002
摘要： A memory control module includes a format module that communicates with a memory array that includes B memory blocks each including P physical pages and Q logical pages. The format module selects X predetermined locations to write pilot data and read-back pilot signals in each of the B memory blocks. B, P, Q and X are integers greater than or equal to 1. The memory control module also includes a signal processing module that compares the written pilot data to the read-back pilot signals and that determines variations between the written pilot data and the read-back pilot signals based on the comparison.
摘要翻译：存储器控制模块包括格式化模块，该格式化模块与包括B个存储器块的存储器阵列通信，每个B存储器块包括P个物理页面和Q个逻辑页面。格式模块选择X个预定位置以在每个B存储块中写入导频数据和回读导频信号。 B，P，Q和X是大于或等于1的整数。存储器控制模块还包括信号处理模块，其将写入的导频数据与回读的导频信号进行比较，并确定写入的导频数据与基于比较的回读导频信号。

5. 发明申请

WO2008100415A2 NONVOLATILE MEMORY SYSTEM 审中-公开
标题翻译：非易失性存储器系统
公开(公告)号：WO2008100415A2
公开(公告)日：2008-08-21
申请号：PCT/US2008001669
申请日：2008-02-08
申请人： MARVELL WORLD TRADE LTD , WU ZINING , NGUYEN LAU , SUTARDJA PANTAS , LEE CHI-KONG , YOON TONY
发明人： WU ZINING , NGUYEN LAU , SUTARDJA PANTAS , LEE CHI-KONG , YOON TONY
CPC分类号： G06F3/0688 , G06F3/0619 , G06F3/0661 , G06F11/1068 , G06F12/0246
摘要： A nonvolatile (NV) memory system includes a memory control module that encodes data to provide encoded logical data structures. The system also includes NV memory that includes X arrays that include physical data structures that differ in size from the encoded logical data structures. The memory control module writes/reads from the NV memory according to the encoded logical data structures. X is an integer greater than or equal to 1.
摘要翻译：非易失性（NV）存储器系统包括对数据进行编码以提供编码的逻辑数据结构的存储器控制模块。该系统还包括NV存储器，其包括X阵列，其包括尺寸与编码的逻辑数据结构不同的物理数据结构。存储器控制模块根据编码的逻辑数据结构从NV存储器写入/读取。 X是大于或等于1的整数。

6. 发明申请

WO2008021045A3 SYSTEM AND METHOD FOR CORRECTING ERRORS IN NON-VOLATILE MEMORY USING PRODUCT CODES 审中-公开
标题翻译：用于使用产品代码来纠正非易失性存储器中的错误的系统和方法
公开(公告)号：WO2008021045A3
公开(公告)日：2008-04-17
申请号：PCT/US2007017450
申请日：2007-08-06
申请人： MARVELL WORLD TRADE LTD , WU ZINING , SUTARDJA PANTAS
发明人： WU ZINING , SUTARDJA PANTAS
IPC分类号： G11C29/52 , G06F11/10
CPC分类号： G11C29/52 , G06F11/1068
摘要： A product code encoder for non-volatile (NV) memory includes a first encoder that encodes data in codewords in a first dimension that is stored in the NV memory. The product code encoder also includes a second encoder that encodes data in codewords in a second dimension that is stored in the NV memory. A product code codeword is based on the codewords in the first dimension and the codewords in the second dimension.
摘要翻译：用于非易失性（NV）存储器的产品码编码器包括第一编码器，第一编码器对存储在NV存储器中的第一维中的码字中的数据进行编码。产品码编码器还包括第二编码器，其对存储在NV存储器中的第二维中的码字中的数据进行编码。产品码字是基于第一维中的码字和第二维中的码字。

7. 发明申请

WO2014066462A4 APPARATUS AND METHOD FOR REFORMING RESISTIVE MEMORY CELLS 审中-公开
公开(公告)号：WO2014066462A4
公开(公告)日：2014-10-02
申请号：PCT/US2013066303
申请日：2013-10-23
申请人： MARVELL WORLD TRADE LTD , SUTARDJA PANTAS , WU ALBERT , LEE WINSTON , LEE PETER , CHANG RUNZI
发明人： SUTARDJA PANTAS , WU ALBERT , LEE WINSTON , LEE PETER , CHANG RUNZI
IPC分类号： G11C29/50 , G11C13/00
CPC分类号： G11C13/0069 , G11C11/16 , G11C13/00 , G11C13/0033 , G11C13/004 , G11C29/50008 , G11C2013/0076 , G11C2013/0083
摘要： A memory includes an array of memory cells, a first module and a second module. The first module is configured to compare a first state of a memory cell with a reference. The memory cell is in the array of memory cells. The second module is configured to, subsequent to a read cycle or a write cycle of the memory cell and based on the comparison, reform the memory cell to adjust a difference between the first state and a second state of the memory cell.

8. 发明申请

WO2013078311A4 FREQUENCY SCALING OF VARIABLE SPEED SYSTEMS FOR FAST RESPONSE AND POWER REDUCTION 审中-公开
标题翻译：用于快速响应和降低功率的变速系统的频率标定
公开(公告)号：WO2013078311A4
公开(公告)日：2013-07-18
申请号：PCT/US2012066257
申请日：2012-11-21
申请人： MARVELL WORLD TRADE LTD , SUTARDJA PANTAS , SUTARDJA SEHAT
发明人： SUTARDJA PANTAS , SUTARDJA SEHAT
IPC分类号： G06F1/08 , G06F1/32 , H03L7/00
CPC分类号： H03K3/02 , G06F1/08 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： A system including a plurality of amplifiers configured to generate a clock signal having a frequency. The clock signal is input to a processor. The amplifiers are connected in series. An output of a last one of the amplifiers is fed back to an input of a first one of the amplifiers. Each of the amplifiers has a transconductance. A frequency adjustment module is configured to adjust, based on an activity level of the processor, the frequency of the clock signal by adjusting the transconductance of the amplifiers.
摘要翻译：一种包括被配置为生成具有频率的时钟信号的多个放大器的系统。时钟信号被输入到处理器。放大器串联连接。最后一个放大器的输出被反馈到第一个放大器的输入端。每个放大器都有一个跨导。频率调整模块被配置为基于处理器的活动水平通过调整放大器的跨导来调整时钟信号的频率。

9. 发明申请

WO2011060248A4 CLOCK TURN-ON STRATEGY FOR POWER MANAGEMENT 审中-公开
标题翻译：电源管理的时钟开启策略
公开(公告)号：WO2011060248A4
公开(公告)日：2011-10-27
申请号：PCT/US2010056509
申请日：2010-11-12
申请人： MARVELL WORLD TRADE LTD , SUTARDJA PANTAS
发明人： SUTARDJA PANTAS
IPC分类号： G06F1/30 , G06F1/08
CPC分类号： G06F21/50 , G06F1/08 , G06F1/305
摘要： A system includes a voltage sensing module and a frequency adjustment module. The voltage sensing module is configured to sense a supply voltage of a circuit block, generate a first control signal when the supply voltage is less than or equal to a first voltage, and generate a second control signal when the supply voltage is within a predetermined range of a second voltage. The frequency adjustment module is configured to set a frequency of a clock signal supplied to the circuit block to less than a normal operating frequency of the circuit block when the supply voltage is initially supplied to the circuit block after a power on reset operation and the first control signal or the second control signal is received.
摘要翻译：一种系统包括电压感测模块和频率调整模块。电压感测模块被配置为感测电路块的电源电压，当电源电压小于或等于第一电压时产生第一控制信号，并且当电源电压在预定范围内时产生第二控制信号的第二电压。频率调节模块被配置为：当在电源接通复位操作之后将电源电压初始提供给电路块时，将提供给电路块的时钟信号的频率设置为小于电路块的正常工作频率，并且第一控制信号或第二控制信号被接收。

10. 发明申请

WO2008073421A3 HYBRID NON-VOLATILE SOLID STATE MEMORY SYSTEM 审中-公开
公开(公告)号：WO2008073421A3
公开(公告)日：2008-07-31
申请号：PCT/US2007025312
申请日：2007-12-11
申请人： MARVELL WORLD TRADE LTD , SUTARDJA PANTAS
发明人： SUTARDJA PANTAS
IPC分类号： G06F12/12 , G11C16/34
CPC分类号： G11C16/349 , G06F3/0616 , G06F3/0644 , G06F3/0679 , G06F12/0246 , G06F2212/1036 , G06F2212/7211 , G11C16/3495 , G11C2211/5641
摘要： A solid state memory system comprises a first nonvolatile semiconductor (NVS) memory that has a first write cycle lifetime, a second nonvolatile semiconductor (NVS) memory that has a second write cycle lifetime that is different than the first write cycle lifetime, and a wear leveling module. The wear leveling module generates first and second wear levels for the first and second NVS memories based on the first and second write cycle lifetimes and maps logical addresses to physical addresses of one of the first and second NVS memories based on the first and second wear levels.

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