会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 2. 发明申请
    • DETERMINING PLASMA PROCESSING SYSTEM READINESS WITHOUT GENERATING PLASMA
    • 在不产生等离子体的情况下确定等离子体处理系统的准备情况
    • WO2011008376A3
    • 2011-03-10
    • PCT/US2010037936
    • 2010-06-09
    • LAM RES CORPCHOI BRIANYUN GUNSUVENUGOPAL VIJAYAKUMAR CWILLIAMS NORMAN
    • CHOI BRIANYUN GUNSUVENUGOPAL VIJAYAKUMAR CWILLIAMS NORMAN
    • H01L21/66H01L21/00H01L21/02
    • H01J37/32935
    • A test system for facilitating determining whether a plasma processing system (which includes a plasma processing chamber) is ready for processing wafers. The test system may include a computer-readable medium storing at least a test program. The test program may include code for receiving electric parameter values derived from signals detected by at least one sensor when no plasma is present in the plasma processing chamber. The test program may also include code for generating electric model parameter values using the electric parameter values and a mathematical model. The test program may also include code for comparing the electric model parameter values with baseline model parameter value information. The test program may also include code for determining readiness of the plasma processing system based on the comparison. The test system may also include circuit hardware for performing one or more tasks associated with the test program.
    • 一种便于确定等离子体处理系统(包括等离子体处理室)是否准备好处理晶片的测试系统。 测试系统可以包括存储至少一个测试程序的计算机可读介质。 测试程序可以包括用于当在等离子体处理室中不存在等离子体时接收由至少一个传感器检测到的信号导出的电参数值的代码。 测试程序还可以包括用于使用电参数值和数学模型来生成电模型参数值的代码。 测试程序还可以包括用于将电模型参数值与基线模型参数值信息进行比较的代码。 测试程序还可以包括用于基于比较确定等离子体处理系统的准备状态的代码。 测试系统还可以包括用于执行与测试程序相关联的一个或多个任务的电路硬件。
    • 5. 发明申请
    • METHODS AND ARRANGEMENTS FOR IN-SITU PROCESS MONITORING AND CONTROL FOR PLASMA PROCESSING TOOLS
    • 用于等离子体处理工具的原位过程监测和控制的方法和装置
    • WO2011002800A2
    • 2011-01-06
    • PCT/US2010/040456
    • 2010-06-29
    • LAM RESEARCH CORPORATIONVENUGOPAL, Vijayakumar C.BENJAMIN, Neil Martin Paul
    • VENUGOPAL, Vijayakumar C.BENJAMIN, Neil Martin Paul
    • H01L21/3065H01L21/00
    • H01J37/3299H01J37/32935
    • An arrangement for implementing an automatic in-situ process control scheme during execution of a recipe is provided. The arrangement includes control-loop sensors configured at least for collecting a first set of sensor data to facilitate monitoring set points during the recipe execution, wherein the control-loop sensors being part of a process control loop. The arrangement also includes independent sensors configured at least for collecting a second set of sensor data, which is not part of the process control loop. The arrangement yet also includes a hub configured for at least receiving at least one of the first set of sensor data and the second set of sensor data. The arrangement yet further includes an analysis computer communicably coupled with the hub and configured for performing analysis of at least one of the first set of sensor data and the second set of sensor data.
    • 提供了在执行配方期间实现自动现场过程控制方案的配置。 该装置包括控制回路传感器,该传感器被配置为至少用于收集第一组传感器数据以便于在配方执行期间监测设定点,其中,控制回路传感器是过程控制回路的一部分。 该装置还包括独立的传感器,其被配置为至少用于收集第二组传感器数据,其不是过程控制回路的一部分。 该装置还包括配置用于至少接收第一组传感器数据和第二组传感器数据中的至少一个的集线器。 该装置还包括分析计算机,该分析计算机与集线器可通信地耦合并被配置为执行对第一组传感器数据和第二组传感器数据中的至少一个的分析。
    • 7. 发明申请
    • METHOD FOR CONTROLLING A RECESS ETCH PROCESS
    • 控制记忆蚀刻过程的方法
    • WO2004015727A2
    • 2004-02-19
    • PCT/US2003/025156
    • 2003-08-12
    • LAM RESEARCH CORPORATIONVENUGOPAL, Vijayakumar, C.PERRY, Andrew, J.
    • VENUGOPAL, Vijayakumar, C.PERRY, Andrew, J.
    • H01G
    • G01B11/0683G01B11/0616G01B11/0625H01L27/1087H01L29/66181
    • A method of controlling a recess etch process for a multilayered substrate having a trench therein and a column of material deposited in the trench includes determining a first dimension from a surface of the substrate to a reference point in the substrate by obtaining a measured net reflectance of at least a portion of the substrate including the trench, computing a modeled net reflectance of the portion of the substrate as a weighted incoherent sum of reflectances from n1 different regions constituting the portion of the substrate, determining a set of parameters that provides a close match between the measured net reflectance and the modeled net reflectance, and extracting the first dimension from the set of parameters; computing an endpoint of the process as a function of the first dimension and a desired recess depth measured from the reference point; and etching down from a surface of the column of material until the endpoint is reached.
    • 控制其中具有沟槽的多层衬底的凹陷蚀刻工艺和沉积在沟槽中的材料柱的方法包括通过获得测量的净反射率来确定从衬底的表面到衬底中的参考点的第一维度 衬底的至少一部分包括沟槽,计算衬底部分的建模净反射率作为来自构成衬底部分的n1个不同区域的反射率的加权非相干总和,确定提供紧密匹配的一组参数 在测量的净反射率和建模的净反射率之间,并从该组参数中提取第一维度; 计算作为第一尺寸的函数的过程的端点和从参考点测量的期望的凹陷深度; 并且从材料柱的表面向下蚀刻直到达到端点。
    • 8. 发明申请
    • DETERMINING PLASMA PROCESSING SYSTEM READINESS WITHOUT GENERATING PLASMA
    • 确定等离子体处理系统无需生成等离子体
    • WO2011008376A2
    • 2011-01-20
    • PCT/US2010/037936
    • 2010-06-09
    • LAM RESEARCH CORPORATIONCHOI, BrianYUN, GunsuVENUGOPAL, Vijayakumar C.WILLIAMS, Norman
    • CHOI, BrianYUN, GunsuVENUGOPAL, Vijayakumar C.WILLIAMS, Norman
    • H01L21/66H01L21/02H01L21/00
    • H01J37/32935
    • A test system for facilitating determining whether a plasma processing system (which includes a plasma processing chamber) is ready for processing wafers. The test system may include a computer-readable medium storing at least a test program. The test program may include code for receiving electric parameter values derived from signals detected by at least one sensor when no plasma is present in the plasma processing chamber. The test program may also include code for generating electric model parameter values using the electric parameter values and a mathematical model. The test program may also include code for comparing the electric model parameter values with baseline model parameter value information. The test program may also include code for determining readiness of the plasma processing system based on the comparison. The test system may also include circuit hardware for performing one or more tasks associated with the test program.
    • 用于有助于确定等离子体处理系统(其包括等离子体处理室)是否准备好用于处理晶片的测试系统。 测试系统可以包括至少存储测试程序的计算机可读介质。 测试程序可以包括用于接收由等离子体处理室中没有等离子体时由至少一个传感器检测的信号导出的电参数值的代码。 测试程序还可以包括使用电参数值和数学模型产生电模型参数值的代码。 测试程序还可以包括用于将电模型参数值与基准模型参数值信息进行比较的代码。 测试程序还可以包括用于基于比较来确定等离子体处理系统的准备状态的代码。 测试系统还可以包括用于执行与测试程序相关联的一个或多个任务的电路硬件。
    • 9. 发明申请
    • METHODS AND APPARATUS TO PREDICT ETCH RATE UNIFORMITY FOR QUALIFICATION OF A PLASMA CHAMBER
    • 预测等离子体室质量的方法和装置预测
    • WO2011002804A2
    • 2011-01-06
    • PCT/US2010/040468
    • 2010-06-29
    • LAM RESEARCH CORPORATIONCHOI, Brian D.YUN, GunsuVENUGOPAL, Vijayakumar C.
    • CHOI, Brian D.YUN, GunsuVENUGOPAL, Vijayakumar C.
    • H05H1/24G06F17/40
    • H01J37/3299H01J37/32935
    • A method for predicting etch rate uniformity for qualifying health status of a processing chamber during substrate processing of substrates is provided. The method includes executing a recipe and receiving processing data from a first set of sensors. The method further includes analyzing the processing data utilizing a subsystem health check predictive model to determine calculated data, which includes at least one of etch rate data and uniformity data. The subsystem health check predictive model is constructed by correlating measurement data from a set of film substrates with processing data collected during analogous processing of a set of non-film substrates. The method yet also includes performing a comparison of the calculated data against a set of control limits as defined by the subsystem health check predictive model. The method yet further includes generating a warning if the calculated data is outside of the set of control limits.
    • 提供了一种用于在衬底的衬底处理期间预测用于限定处理室的健康状况的蚀刻速率均匀性的方法。 该方法包括执行食谱并从第一组传感器接收处理数据。 该方法还包括利用子系统健康检查预测模型来分析处理数据,以确定计算出的数据,其包括蚀刻速率数据和均匀性数据中的至少一个。 通过将来自一组膜基底的测量数据与在一组非膜基底的类似处理期间收集的处理数据相关联来构建子系统健康检查预测模型。 该方法还包括执行计算数据与由子系统健康检查预测模型定义的一组控制限制的比较。 所述方法还包括如果所计算的数据在所述一组控制限度之外,则产生警告。