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1. 发明授权

US5193196A Process request arbitration system which preferentially maintains previously selected process request upon receipt of a subsequent request of identical priority 失效
标题翻译：处理请求仲裁系统，其在接收到相同优先级的后续请求时优先维护先前选择的进程请求
公开(公告)号：US5193196A
公开(公告)日：1993-03-09
申请号：US331297
申请日：1989-03-31
申请人： Tetsuya Mochida , Shigeo Tsujioka , Masami Jikihara , Hitoshi Sadamitsu , Kazushi Kobayashi
发明人： Tetsuya Mochida , Shigeo Tsujioka , Masami Jikihara , Hitoshi Sadamitsu , Kazushi Kobayashi
IPC分类号： G06F13/30 , G06F13/364
CPC分类号： G06F13/30 , G06F13/364
摘要： A plurality of process requests generated from processing units, for example, direct memory access (DMA) channels are controlled by a preference circuit in accordance with a priority level assigned to each of the processing unit. An information of the highest priority obtained processing unit and its priority level is stored in latches. Another process requests having the same priority level as the stored processing unit are inhibited from being supplied to the preference circuit, so that the first generated process request is accepted and executed prior to acceptance of the another process requests having the same priority level.
摘要翻译：从处理单元产生的多个处理请求，例如直接存储器访问（DMA）信道由优先级电路根据分配给每个处理单元的优先级控制。最高优先级获得的处理单元及其优先级的信息被存储在锁存器中。禁止具有与存储的处理单元相同的优先级的另一处理请求被提供给偏好电路，使得在接受具有相同优先级的另一进程请求之前接受并执行第一生成的处理请求。

2. 发明授权

US4709231A Shading apparatus for displaying three dimensional objects 失效
标题翻译：用于显示三维物体的遮光装置
公开(公告)号：US4709231A
公开(公告)日：1987-11-24
申请号：US766941
申请日：1985-08-19
申请人： Toru Sakaibara , Shigeo Tsujioka , Toshinori Kajiura , Toshihisa Aoshima , Motonobu Tonomura
发明人： Toru Sakaibara , Shigeo Tsujioka , Toshinori Kajiura , Toshihisa Aoshima , Motonobu Tonomura
IPC分类号： G06F3/153 , G06T1/00 , G06T15/80 , G09G5/02 , G09G5/36 , G09G1/06
CPC分类号： G06T15/506
摘要： An apparatus for shading a polyhedron at high speed is disclosed which includes the combination of a polygon-scan line conversion processor and an inner product interpolation processor for obtaining a pair of inner products of vectors indicative of a relation among the direction of a normal, the direction of a light source and the direction of a view point each viewed at a point within a polygon having a plurality of vertices, on the basis of the position of said point in the polygon and the direction of a normal at each of the vertices, a table searched on the basis of the inner products of vectors and holding a series of brightness data which have previously been calculated for a series of values of each of the inner products of vectors, a buffer for storing the result of table search for the above table, and a D/A conversion circuit for converting the result of table search into a signal which is used as a brightness control signal in a display device.
摘要翻译：公开了一种用于高速遮光多面体的装置，其包括多边形扫描线转换处理器和内积插值处理器的组合，用于获得指示正常方向之间的关系的向量的一对内积，基于多边形中的点的位置和每个顶点的法线方向，在具有多个顶点的多边形内的点处观察光源的方向和观察点的方向，基于向量的内积产生的表的搜索，并且保存了先前针对向量的每个内积的一系列值计算的一系列亮度数据，用于存储上述搜索结果的缓冲器表和D / A转换电路，用于将表搜索的结果转换为在显示装置中用作亮度控制信号的信号。

3. 发明授权

US4626838A Filled shaped generating apparatus 失效
标题翻译：填充形状发生装置
公开(公告)号：US4626838A
公开(公告)日：1986-12-02
申请号：US541444
申请日：1983-10-13
申请人： Shigeo Tsujioka , Seiichi Kanema , Eiji Okamura , Kiyoshi Umezawa , Mitsuo Ooyama , Toshihisa Aoshima , Mitsugu Yoneyama
发明人： Shigeo Tsujioka , Seiichi Kanema , Eiji Okamura , Kiyoshi Umezawa , Mitsuo Ooyama , Toshihisa Aoshima , Mitsugu Yoneyama
IPC分类号： G06F3/153 , G06T11/40 , G09G5/36 , G09G5/393 , G09G1/00
CPC分类号： G09G5/393 , G06T11/40
摘要： An apparatus for filling an interior of a shape to be displayed on a raster scan CRT which reads out a refresh memory. The apparatus includes a memory for storing information of starting points and ending points for filling. The write of a filling color code into the refresh memory is initiated and terminates in response to the filling starting point and the filling ending point, respectively, but inhibited at its memory locations on the contour of the shape. The direction of the filling is perpendicular to the raster scanning of the CRT.
摘要翻译：一种用于填充要在显示刷新存储器的光栅扫描CRT上显示的形状内部的装置。该装置包括用于存储用于填充的起点和终点的信息的存储器。启动填充颜色代码到刷新存储器中的写入，并且分别响应于填充起始点和填充结束点而终止，但是在其形状轮廓上的存储器位置被禁止。填充方向垂直于CRT的光栅扫描。

4. 发明授权

US5734810A Client server system performing automatic reconnection and control method thereof 失效
标题翻译：客户服务器系统执行自动重新连接及其控制方法
公开(公告)号：US5734810A
公开(公告)日：1998-03-31
申请号：US498484
申请日：1995-07-05
申请人： Toshio Tanaka , Shigeo Tsujioka
发明人： Toshio Tanaka , Shigeo Tsujioka
IPC分类号： G06F13/00 , H04L29/06 , H04L12/00
CPC分类号： H04L67/42
摘要： In a client server system including a server machine including a network device and a plurality of client machines each including a network machine, the server machine includes a unit to send shutdown information indicating the shutdown state thereof and restoration information to the client machines and each client machine includes a control logic operative at reception of shutdown information from the server machine to conduct an attempt for line connection to the server machine at a desired interval of time. As a result, at restoration of the server machine from the shutdown state, the state of connection to each client machine is automatically achieved from the client side. Accordingly, at shut-down of the server machine, the logical line connection can be reconstructed without any intervention of the user of each client machine.
摘要翻译：在包括包括网络设备的服务器机器和包括网络机器的多台客户机的客户端服务器系统中，服务器机器包括向客户端机器和每个客户机发送指示其关闭状态的关机信息和恢复信息的单元机器包括控制逻辑，该控制逻辑在接收来自服务器机器的关机信息时进行操作，以在期望的时间间隔进行线路连接到服务器机器的尝试。因此，在从关机状态恢复服务器的情况下，从客户端自动实现与各客户机的连接状态。因此，在服务器机器关闭时，逻辑线路连接可以被重建，而不需要每个客户端机器的用户的干预。

5. 发明授权

US5504922A Virtual machine with hardware display controllers for base and target machines 失效
标题翻译：虚拟机与基础和目标机器的硬件显示控制器
公开(公告)号：US5504922A
公开(公告)日：1996-04-02
申请号：US300863
申请日：1994-09-06
申请人： Yukihiro Seki , Hiromichi Itoh , Shigeo Tsujioka
发明人： Yukihiro Seki , Hiromichi Itoh , Shigeo Tsujioka
IPC分类号： G06F3/048 , G06F3/023 , G06F3/14 , G06F9/455 , G06F9/46 , G06F3/037 , G06F13/12
CPC分类号： G06F3/023 , G06F9/45533
摘要： A virtual machine for operating, on a base machine, applications software for a target machine. The virtual machine includes first display control hardware for the base machine, second display control hardware for the target machine, a virtual machine monitor for emulating the operation of the target machine by utilizing the second display control hardware for displaying operation, and a selector for selecting one of the first display control hardware and the second display control hardware depending on whether the virtual machine monitor is operable in a target machine mode or a base machine mode. The OS of the base machine is utilized for the virtual machine without modification.
摘要翻译：用于在基本机器上操作用于目标机器的应用软件的虚拟机。虚拟机包括用于基本机器的第一显示控制硬件，用于目标机器的第二显示控制硬件，用于通过利用用于显示操作的第二显示控制硬件模拟目标机器的操作的虚拟机监视器，以及用于选择第一显示控制硬件和第二显示控制硬件之一，取决于虚拟机监视器是否在目标机器模式或基本机器模式下可操作。基本机器的操作系统无需修改即可用于虚拟机。

6. 发明授权

US4990907A Method and apparatus for data transfer 失效
标题翻译：用于数据传输的方法和装置
公开(公告)号：US4990907A
公开(公告)日：1991-02-05
申请号：US231000
申请日：1988-08-11
申请人： Masami Jikihara , Shigeo Tsujioka , Hiromichi Enomoto , Tetsuya Mochida , Masataka Kobayashi
发明人： Masami Jikihara , Shigeo Tsujioka , Hiromichi Enomoto , Tetsuya Mochida , Masataka Kobayashi
IPC分类号： G06F13/42
CPC分类号： G06F13/4213
摘要： A bus master and a plurality of bus slaves are connected through a data bus and a control bus, and data transfer of hand shake system is performed. In the control bus, at least data strobe signal from the bus master to the bus slave and data confirmation signal from the bus slave to the bus master are transmitted. The data strobe signal from the bus master is one inputted to a bus strobe control circuit. The data confirmation signal from the bus slave is also inputted to the bus strobe control circuit, and the control circuit supervises level of the data confirmation signal being asserted and confirms negation, and then asserts the data strobe signal to the bus slave. Thereafter, a next data transfer is started.
摘要翻译：通过数据总线和控制总线连接总线主机和多个总线从机，执行手抖动系统的数据传送。在控制总线中，至少从总线主机到总线从站的数据选通信号和从总线从站到总线主站的数据确认信号。来自总线主机的数据选通信号是输入到总线选通控制电路的信号。来自总线从站的数据确认信号也被输入到总线选通控制电路，控制电路对数据确认信号的电平进行监控，并确认为否定，然后将数据选通信号置为总线从站。此后，开始下一次数据传送。

7. 发明授权

US4080648A Micro program control system 失效
标题翻译：微程序控制系统
公开(公告)号：US4080648A
公开(公告)日：1978-03-21
申请号：US691136
申请日：1976-05-28
申请人： Michio Asano , Masato Yamagishi , Shoji Iwamoto , Shigeo Tsujioka
发明人： Michio Asano , Masato Yamagishi , Shoji Iwamoto , Shigeo Tsujioka
IPC分类号： G06F9/22 , G06F9/26 , G06F9/06
CPC分类号： G06F9/268
摘要： A micro program control system for use in a data processing system includes a subsidiary control memory for storing the first micro instructions of respective micro programs, and a control memory for storing the second and the remaining micro instructions of the respective micro programs. The subsidinary control memory is coupled to a main memory in which macro instructions of a program for the data processing system are stored. The operation code of the macro instruction includes a code to address the first micro instruction in the subsidiary control memory, so that one of the first micro instructions can be accessed to supply into a control register when the macro instruction is read out from the main memory to an instruction register of the data processing system, whereby control signals for controlling the operation of the data processing system are delivered from the control register according to the contents of the first micro instruction. The second and necessary number of the remaining micro instructions in the control memory are fetched, in turn, into the control register according to the operation code of the macro instruction held in the instruction register and the contents of the preceding micro instruction in the control register, whereby a micro program corresponding to the macro instruction is performed.
摘要翻译：用于数据处理系统的微程序控制系统包括用于存储各个微程序的第一微指令的辅助控制存储器和用于存储相应微程序的第二和剩余微指令的控制存储器。辅助控制存储器耦合到其中存储用于数据处理系统的程序的宏指令的主存储器。宏指令的操作代码包括用于寻址辅助控制存储器中的第一微指令的代码，使得当从主存储器读出宏指令时，可以访问第一微指令中的一个以供给控制寄存器到数据处理系统的指令寄存器，由此根据第一微指令的内容从控制寄存器传送用于控制数据处理系统的操作的控制信号。根据控制寄存器中保持的宏指令的操作代码和控制寄存器中的前一个微指令的内容，将控制存储器中的剩余微指令的第二和必要数量依次取入控制寄存器由此执行与宏指令相对应的微程序。

8. 发明授权

US5933613A Computer system and inter-bus control circuit 失效
标题翻译：计算机系统和总线间控制电路
公开(公告)号：US5933613A
公开(公告)日：1999-08-03
申请号：US675118
申请日：1996-07-03
申请人： Toshio Tanaka , Kazuhisa Ishida , Tetsuro Kiyomatsu , Shigeo Tsujioka
发明人： Toshio Tanaka , Kazuhisa Ishida , Tetsuro Kiyomatsu , Shigeo Tsujioka
IPC分类号： G06F13/40 , G06F13/24
CPC分类号： G06F13/4022
摘要： In a computer system having a double PCI bus configuration, an inter-bus control circuit for relaying a first PCI bus and a second PCI bus is provided with a memory control mechanism common to devices connected to the second PCI bus and an interrupt control mechanism for controlling interrupts between local processors, in addition to a control function for controlling the buses. The inter-bus control circuit having the above mechanisms can be implemented by a single-chip integrated circuit. The integrated inter-bus control circuit prevents the use of a plurality of identical decoder circuits, an increase in the number of parts, and an increase in mounting area, thus providing a compact and low price computer system.
摘要翻译：在具有双PCI总线配置的计算机系统中，用于中继第一PCI总线和第二PCI总线的总线间控制电路设置有与连接到第二PCI总线的设备通用的存储器控制机制，以及用于控制本地处理器之间的中断，以及用于控制总线的控制功能。具有上述机构的总线间控制电路可以由单芯片集成电路来实现。集成的总线间控制电路防止使用多个相同的解码器电路，部件数量的增加和安装面积的增加，从而提供了一种紧凑且价格低廉的计算机系统。

9. 发明授权

US5109333A Data transfer control method and apparatus for co-processor system 失效
标题翻译：协处理器系统的数据传输控制方法和装置
公开(公告)号：US5109333A
公开(公告)日：1992-04-28
申请号：US338286
申请日：1989-04-14
申请人： Kazumi Kubota , Shigeo Tsujioka , Kensuke Ooyu , Hitoshi Kawaguchi , Mitsutoshi Uchida , Yasuo Kurosu
发明人： Kazumi Kubota , Shigeo Tsujioka , Kensuke Ooyu , Hitoshi Kawaguchi , Mitsutoshi Uchida , Yasuo Kurosu
IPC分类号： G06F9/38 , G06F13/42 , G06F15/16 , G06F15/177
CPC分类号： G06F9/3877 , G06F13/4217
摘要： A data transfer control apparatus for a co-processor system. The co-processor system includes a memory; a memory bus connected to the memory; a main processor connected to the memory bus and having a control circuit for controlling data read/write relative to the memory, the main processor performing data transfer from/to the memory bus via a first data input/output terminal; and a co-processor connected to the memory bus via a second data input/output terminal. The control apparatus includes a high impedance setting circuit for selectively setting the first data input/output terminal at a high impedance state to electrically isolate the first data input/output terminal from the memory bus; and a control signal generator for selectively outputting a control signal to the high impedance setting circuit to cause the high impedance setting circuit to set the first data input/output terminal at the high impedance state. When the co-processor is to perform data read/write relative to the memory, the control signal generator generates the control signal to cause the high impedance setting circuit to set the first data input/output terminal at the high impedance state, and while the first data input/output terminal is set at the high impedance state, the main processor performs read/write control of the memory bus, and the co-processor performs data transfer from/to the memory bus via the second data input/output terminal.
摘要翻译：一种用于协处理器系统的数据传输控制装置。协处理器系统包括存储器; 连接到存储器的存储器总线; 主处理器连接到存储器总线并具有用于控制相对于存储器的数据读/写的控制电路，主处理器经由第一数据输入/输出端执行从存储器总线的数据传送; 以及经由第二数据输入/输出端连接到存储器总线的协处理器。控制装置包括：高阻抗设定电路，用于选择性地将第一数据输入/输出端子设置在高阻抗状态，以使第一数据输入/输出端与存储器总线电隔离; 以及控制信号发生器，用于选择性地向高阻抗设置电路输出控制信号，以使高阻抗设置电路将第一数据输入/输出端子设置在高阻抗状态。当协处理器执行相对于存储器的数据读/写时，控制信号发生器产生控制信号以使高阻抗设置电路将第一数据输入/输出端设置在高阻抗状态，而第一数据输入/输出端被设置在高阻抗状态，主处理器执行存储器总线的读/写控制，并且协处理器经由第二数据输入/输出端执行从存储器总线的数据传送。

10. 发明授权

US4733227A Color display with automatic color control device 失效
标题翻译：彩色显示带自动色彩控制装置
公开(公告)号：US4733227A
公开(公告)日：1988-03-22
申请号：US820640
申请日：1986-01-21
申请人： Seiichi Kanema , Shigeo Tsujioka
发明人： Seiichi Kanema , Shigeo Tsujioka
IPC分类号： G06F3/153 , G09G5/02 , H04N9/68
CPC分类号： H04N9/68
摘要： A detector for detecting the radiation state of a display surface is disposed in a cathode ray tube in order to improve the color reproducibility of a color display. Revise order signals as standard signals are applied to obtain a difference signal between the radiation quantity of a color signal that must be displayed originally and the output signal of the detector, and a circuit for compensating for the radiation order signal is disposed in a path through which the radiation order signal is applied to the cathode ray tube.
摘要翻译：用于检测显示表面的辐射状态的检测器设置在阴极射线管中，以便改善彩色显示的颜色再现性。施加作为标准信号修正订单信号以获得必须在原始显示的彩色信号的辐射量与检测器的输出信号之间的差分信号，并且用于补偿辐射指令信号的电路设置在通过的路径辐射指令信号被施加到阴极射线管。

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