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1. 发明授权

US5523973A Memory device 失效
公开(公告)号：US5523973A
公开(公告)日：1996-06-04
申请号：US458480
申请日：1995-06-02
申请人： Koichi Kimura , Toshihiko Ogura , Hiroaki Aotsu , Mitsuru Ikegami , Tadashi Kuwabara , Hiromichi Enomoto , Tadashi Kyoda
发明人： Koichi Kimura , Toshihiko Ogura , Hiroaki Aotsu , Mitsuru Ikegami , Tadashi Kuwabara , Hiromichi Enomoto , Tadashi Kyoda
IPC分类号： G06F7/575 , G06T1/20 , G06T1/60 , G09G5/393 , G11C13/00
CPC分类号： G06T1/20 , G06F7/575 , G06T1/60 , G09G5/393 , G09G2340/10
摘要： A memory device formed on an IC chip includes dynamic random access memories for effecting data read and write operations, first and second data terminals for receiving data from an external side of the IC chip, and a controller having a first data input connected to the first data terminal to receive first data, a second input connected to receive second data read, a third data input connected to the second data terminal to receive a function mode signal, and operation unit for executing operations between the first data provided from the first data input and the second data provided from the second input. The operation unit includes a function setting unit responsive to the function mode signal for setting a function indicated by the function mode signal prior to receipt of the first data. The second data is read out of a selected part of the storage locations. The operation corresponding to the function set by the function setting unit is executed for the first and second data. The result of the execution is written into the selected part of the storage locations via the input of the dynamic random access memories during one memory cycle.

2. 发明授权

US5499222A Memory device 失效
公开(公告)号：US5499222A
公开(公告)日：1996-03-12
申请号：US435962
申请日：1995-05-05
申请人： Koichi Kimura , Toshihiko Ogura , Hiroaki Aotsu , Mitsuru Ikegami , Tadashi Kuwabara , Hiromichi Enomoto , Tadashi Kyoda
发明人： Koichi Kimura , Toshihiko Ogura , Hiroaki Aotsu , Mitsuru Ikegami , Tadashi Kuwabara , Hiromichi Enomoto , Tadashi Kyoda
IPC分类号： G06F7/575 , G06T1/20 , G06T1/60 , G09G5/393 , G11C13/00
CPC分类号： G06F7/575 , G06T1/20 , G06T1/60 , G09G5/393 , G09G2340/10
摘要： A memory device formed on an IC chip includes dynamic random access memories for effecting data read and write operations, first and second data terminals for receiving data from an external side of the IC chip, and a controller having a first data input connected to the first data terminal to receive first data, a second input connected to receive second data read, a third data input connected to the second data terminal to receive a function mode signal, and operation unit for executing operations between the first data provided from the first data input and the second data provided from the second input. The operation unit includes a function setting unit responsive to the function mode signal for setting a function indicated by the function mode signal prior to receipt of the first data. The second data is read out of a selected part of the storage locations. The operation corresponding to the function set by the function setting unit is executed for the first and second data. The result of the execution is written into the selected part of the storage locations via the input of the dynamic random access memories during one memory cycle.

3. 发明授权

US5450342A Memory device 失效
公开(公告)号：US5450342A
公开(公告)日：1995-09-12
申请号：US855843
申请日：1992-03-20
申请人： Koichi Kimura , Toshihiko Ogura , Hiroaki Aotsu , Mitsuru Ikegami , Tadashi Kuwabara , Hiromichi Enomoto , Tadashi Kyoda
发明人： Koichi Kimura , Toshihiko Ogura , Hiroaki Aotsu , Mitsuru Ikegami , Tadashi Kuwabara , Hiromichi Enomoto , Tadashi Kyoda
IPC分类号： G06F7/575 , G06T1/20 , G06T1/60 , G09G5/393 , G11C13/00
CPC分类号： G06F7/575 , G06T1/20 , G06T1/60 , G09G5/393 , G09G2340/10
摘要： A memory device formed on an IC chip includes dynamic random access memories for effecting data read and write operations, first and second data terminals for receiving data from an external side of the IC chip, and a controller having a first data input connected to the first data terminal to receive first data, a second input connected to receive second data read, a third data input connected to the second data terminal to receive a function mode signal, and operation unit for executing operations between the first data provided from the first data input and the second data provided from the second input. The operation unit includes a function setting unit responsive to the function mode signal for setting a function indicated by the function mode signal prior to receipt of the first data. The second data is read out of a selected part of the storage locations. The operation corresponding to the function set by the function setting unit is executed for the first and second data. The result of the execution is written into the selected part of the storage locations via the input of the dynamic random access memories during one memory cycle.

4. 发明授权

US5265234A Integrated memory circuit and function unit with selective storage of logic functions 失效
标题翻译：集成存储器电路和功能单元，具有选择性存储逻辑功能
公开(公告)号：US5265234A
公开(公告)日：1993-11-23
申请号：US13174
申请日：1993-01-29
申请人： Toshihiko Ogura , Hiroaki Aotsu , Koichi Kimura , Hiromichi Enomoto , Tadashi Kyoda
发明人： Toshihiko Ogura , Hiroaki Aotsu , Koichi Kimura , Hiromichi Enomoto , Tadashi Kyoda
IPC分类号： G09G5/393 , G06F15/62
CPC分类号： G09G5/393 , G09G2340/10
摘要： In a memory circuit having a memory device operative to read, write and hold data and an operation unit implementing computation between a first datum supplied externally and a second datum read out of the memory device, a selector for selecting one of operational function specification data preset externally and a selector for selecting one of bit write control data present externally are given with select control signals, so that a frame buffer memory operative in read-modify-write mode can be used commonly.
摘要翻译：在具有可操作以读取，写入和保持数据的存储器件的存储器电路以及在从外部提供的第一数据和从存储器件读出的第二数据之间实现计算的操作单元中选择一个操作功能指定数据预设外部选择器和用于选择外部存在的位写控制数据中的一个的选择器给出选择控制信号，使得可以通常使用以读 - 修改 - 写模式操作的帧缓冲存储器。

5. 发明授权

US4751124A Information recording medium 失效
标题翻译：信息记录介质
公开(公告)号：US4751124A
公开(公告)日：1988-06-14
申请号：US14454
申请日：1987-02-13
申请人： Takahiro Matsuzawa , Katsuyuki Takeda , Hiromichi Enomoto , Yoshitaka Takahashi , Shozo Ishibashi
发明人： Takahiro Matsuzawa , Katsuyuki Takeda , Hiromichi Enomoto , Yoshitaka Takahashi , Shozo Ishibashi
IPC分类号： G11B7/24 , G11B7/253 , G11B11/10 , G11B11/105 , G11B23/00
CPC分类号： G11B23/0014 , G11B11/10582 , G11B7/253 , Y10S428/90 , Y10S430/146 , Y10T428/24851 , Y10T428/24917
摘要： An information recording medium such as a magneto-optical recording medium is disclosed. The medium comprises two pieces of recording elements. Each element comprises a support and a recording layer provided on a part of one surface of the support. The two pieces of the elements adhere to each other by a non-corrosion-causing adhesive provided on a part of said surface where a recording layer is provided and a fast-hardening adhesive provided on a part of the surface where no recording layer is provided. The time required to adhere the two pieces of the elements can be considerably decreased and the corrosion of the recording layer by the adhesive can be avoided.
摘要翻译：公开了诸如磁光记录介质的信息记录介质。该介质包括两片记录元件。每个元件包括支撑件和设置在支撑件的一个表面的一部分上的记录层。这两个元件通过设置在设置有记录层的所述表面的一部分上的非腐蚀性粘合剂彼此粘合，并且在不设置记录层的表面的一部分上设置快速硬化粘合剂。粘附两片元件所需的时间可以大大降低，并且可以避免粘合剂对记录层的腐蚀。

6. 发明授权

US06359812B2 Memory device 失效
标题翻译：内存设备
公开(公告)号：US06359812B2
公开(公告)日：2002-03-19
申请号：US09750040
申请日：2000-12-29
申请人： Koichi Kimura , Toshihiko Ogura , Hiroaki Aotsu , Mitsuru Ikegami , Tadashi Kuwabara , Hiromichi Enomoto , Tadashi Kyoda
发明人： Koichi Kimura , Toshihiko Ogura , Hiroaki Aotsu , Mitsuru Ikegami , Tadashi Kuwabara , Hiromichi Enomoto , Tadashi Kyoda
IPC分类号： G11C1300
CPC分类号： G11C11/4076 , G06T1/60 , G11C7/1006
摘要： A memory device formed on an IC chip includes dynamic random access memories for effecting data read and write operations, first and second data terminals for receiving data from an external side of the IC chip, and a controller having a first data input connected to the first data terminal to receive first data, a second input connected to receive second data read, a third data input connected to the second data terminal to receive a function mode signal, and operation unit for executing operations between the first data provided from the first data input and the second data provided from the second input. The operation unit includes a function setting unit responsive to the function mode signal for setting a function indicated by the function mode signal prior to receipt of the first data. The second data is read out of a selected part of the storage locations. The operation corresponding to the function set by the function setting unit is executed for the first and second data. The result of the execution is written into the selected part of the storage locations via the input of the dynamic random access memories during one memory cycle.
摘要翻译：形成在IC芯片上的存储器件包括用于进行数据读取和写入操作的动态随机存取存储器，用于从IC芯片的外部侧接收数据的第一和第二数据端子以及具有连接到IC芯片的第一数据输入端的控制器用于接收第一数据的数据终端，连接以接收第二数据读取的第二输入，连接到第二数据终端以接收功能模式信号的第三数据输入，以及用于执行从第一数据输入提供的第一数据之间的操作的操作单元以及从第二输入提供的第二数据。操作单元包括功能设置单元，其响应于在接收到第一数据之前设置由功能模式信号指示的功能的功能模式信号。从存储位置的选定部分读出第二数据。对于第一和第二数据执行与由功能设置单元设置的功能相对应的操作。在一个存储器周期期间，通过动态随机存取存储器的输入将执行的结果写入存储位置的所选部分。

7. 发明授权

US06198665B1 One chip semiconductor integrated circuit device having two modes of data write operation and bits setting operation 失效
标题翻译：具有两种模式的数据写入操作和位设置操作的单芯片半导体集成电路器件
公开(公告)号：US06198665B1
公开(公告)日：2001-03-06
申请号：US09428925
申请日：1999-10-28
申请人： Koichi Kimura , Toshihiko Ogura , Hiroaki Aotsu , Mitsuru Ikegami , Tadashi Kuwabara , Hiromichi Enomoto , Tadashi Kyoda
发明人： Koichi Kimura , Toshihiko Ogura , Hiroaki Aotsu , Mitsuru Ikegami , Tadashi Kuwabara , Hiromichi Enomoto , Tadashi Kyoda
IPC分类号： G11C1300
CPC分类号： G11C11/4076 , G06T1/60 , G11C7/1006
摘要： A memory device formed on an IC chip includes dynamic random access memories for effecting data read and write operations, first and second data terminals for receiving data from an external side of the IC chip, and a controller having a first data input connected to the first data terminal to receive first data, a second input connected to receive second data read, a third data input connected to the second data terminal to receive a function mode signal, and operation unit for executing operations between the first data provided from the first data input and the second data provided from the second input. The operation unit includes a function setting unit responsive to the function mode signal for setting a function indicated by the function mode signal prior to receipt of the first data. The second data is read out of a selected part of the storage locations. The operation corresponding to the function set by the function setting unit is executed for the first and second data. The result of the execution is written into the selected part of the storage locations via the input of the dynamic random access memories during one memory cycle.
摘要翻译：形成在IC芯片上的存储器件包括用于进行数据读取和写入操作的动态随机存取存储器，用于从IC芯片的外部侧接收数据的第一和第二数据端子以及具有连接到IC芯片的第一数据输入端的控制器用于接收第一数据的数据终端，连接以接收第二数据读取的第二输入，连接到第二数据终端以接收功能模式信号的第三数据输入，以及用于执行从第一数据输入提供的第一数据之间的操作的操作单元以及从第二输入提供的第二数据。操作单元包括功能设置单元，其响应于在接收到第一数据之前设置由功能模式信号指示的功能的功能模式信号。从存储位置的选定部分读出第二数据。对于第一和第二数据执行与由功能设置单元设置的功能相对应的操作。在一个存储器周期期间，通过动态随机存取存储器的输入将执行的结果写入存储位置的所选部分。

8. 发明授权

US5781479A Memory device 失效
公开(公告)号：US5781479A
公开(公告)日：1998-07-14
申请号：US853713
申请日：1997-05-09
申请人： Koichi Kimura , Toshihiko Ogura , Hiroaki Aotsu , Mitsuru Ikegami , Tadashi Kuwabara , Hiromichi Enomoto , Tadashi Kyoda
发明人： Koichi Kimura , Toshihiko Ogura , Hiroaki Aotsu , Mitsuru Ikegami , Tadashi Kuwabara , Hiromichi Enomoto , Tadashi Kyoda
IPC分类号： G06F7/575 , G06T1/20 , G06T1/60 , G09G5/393 , G11C13/00
CPC分类号： G06T1/20 , G06F7/575 , G06T1/60 , G09G5/393 , G09G2340/10
摘要： A memory device formed on an IC chip includes dynamic random access memories for effecting data read and write operations, first and second data terminals for receiving data from an external side of the IC chip, and a controller having a first data input connected to the first data terminal to receive first data, a second input connected to receive second data read, a third data input connected to the second data terminal to receive a function mode signal, and operation unit for executing operations between the first data provided from the first data input and the second data provided from the second input. The operation unit includes a function setting unit responsive to the function mode signal for setting a function indicated by the function mode signal prior to receipt of the first data. The second data is read out of a selected part of the storage locations. The operation corresponding to the function set by the function setting unit is executed for the first and second data. The result of the execution is written into the selected part of the storage locations via the input of the dynamic random access memories during one memory cycle.

9. 发明授权

US5719809A Memory device 失效
公开(公告)号：US5719809A
公开(公告)日：1998-02-17
申请号：US694599
申请日：1996-08-09
申请人： Koichi Kimura , Toshihiko Ogura , Hiroaki Aotsu , Mitsuru Ikegami , Tadashi Kuwabara , Hiromichi Enomoto , Tadashi Kyoda
发明人： Koichi Kimura , Toshihiko Ogura , Hiroaki Aotsu , Mitsuru Ikegami , Tadashi Kuwabara , Hiromichi Enomoto , Tadashi Kyoda
IPC分类号： G06F7/575 , G06T1/20 , G06T1/60 , G09G5/393 , G11C13/00
CPC分类号： G06T1/20 , G06F7/575 , G06T1/60 , G09G5/393 , G09G2340/10
摘要： A memory device formed on an IC chip includes dynamic random access memories for effecting data read and write operations, first and second data terminals for receiving data from an external side of the IC chip, and a controller having a first data input connected to the first data terminal to receive first data, a second input connected to receive second data read, a third data input connected to the second data terminal to receive a function mode signal, and operation unit for executing operations between the first data provided from the first data input and the second data provided from the second input. The operation unit includes a function setting unit responsive to the function mode signal for setting a function indicated by the function mode signal prior to receipt of the first data. The second data is read out of a selected part of the storage locations. The operation corresponding to the function set by the function setting unit is executed for the first and second data. The result of the execution is written into the selected part of the storage locations via the input of the dynamic random access memories during one memory cycle.

10. 发明授权

US5615155A Memory device 失效
公开(公告)号：US5615155A
公开(公告)日：1997-03-25
申请号：US582906
申请日：1996-01-04
申请人： Koichi Kimura , Toshihiko Ogura , Hiroaki Aotsu , Mitsuru Ikegami , Tadashi Kuwabara , Hiromichi Enomoto , Tadashi Kyoda
发明人： Koichi Kimura , Toshihiko Ogura , Hiroaki Aotsu , Mitsuru Ikegami , Tadashi Kuwabara , Hiromichi Enomoto , Tadashi Kyoda
IPC分类号： G06F7/575 , G06T1/20 , G06T1/60 , G09G5/393 , G11C13/00
CPC分类号： G06T1/20 , G06F7/575 , G06T1/60 , G09G5/393 , G09G2340/10
摘要： A memory device formed on an IC chip includes dynamic random access memories for effecting data read and write operations, first and second data terminals for receiving data from an external side of the IC chip, and a controller having a first data input connected to the first data terminal to receive first data, a second input connected to receive second data read, a third data input connected to the second data terminal to receive a function mode signal, and operation unit for executing operations between the first data provided from the first data input and the second data provided from the second input. The operation unit includes a function setting unit responsive to the function mode signal for setting a function indicated by the function mode signal prior to receipt of the first data. The second data is read out of a selected part of the storage locations. The operation corresponding to the function set by the function setting unit is executed for the first and second data. The result of the execution is written into the selected part of the storage locations via the input of the dynamic random access memories during one memory cycle.

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