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1. 发明授权

US08592886B2 Erasable programmable single-ploy nonvolatile memory 有权
标题翻译：可擦除可编程单态非易失性存储器
公开(公告)号：US08592886B2
公开(公告)日：2013-11-26
申请号：US13572731
申请日：2012-08-13
申请人： Te-Hsun Hsu , Hsin-Ming Chen , Ching-Sung Yang , Wen-Hao Ching , Wei-Ren Chen
发明人： Te-Hsun Hsu , Hsin-Ming Chen , Ching-Sung Yang , Wen-Hao Ching , Wei-Ren Chen
IPC分类号： H01L29/788 , H01L29/06
CPC分类号： H01L27/11558 , G11C16/0433 , G11C2216/10 , H01L29/42328 , H01L29/7883 , H01L29/7885
摘要： An erasable programmable single-poly nonvolatile memory includes a floating gate transistor having a floating gate, a gate oxide layer under the floating gate, and a channel region; and an erase gate region, wherein the floating gate is extended to and is adjacent to the erase gate region. The gate oxide layer comprises a first portion above the channel region of the floating gate transistor and a second portion above the erase gate region, and a thickness of the first portion of the gate oxide layer is different from a thickness of the second portion of the gate oxide layer.
摘要翻译：可擦除可编程单一多晶硅非易失性存储器包括具有浮置栅极的浮动栅极晶体管，浮置栅极下方的栅极氧化物层和沟道区域; 和擦除栅极区，其中浮置栅极延伸到擦除栅极区并且与擦除栅极区相邻。栅极氧化物层包括位于浮动栅极晶体管的沟道区上方的第一部分和擦除栅极区上方的第二部分，并且栅极氧化物层的第一部分的厚度与第二部分的厚度不同栅氧化层。

2. 发明授权

US08384149B2 Memory cell having a shared programming gate 有权
标题翻译：具有共享编程门的存储单元
公开(公告)号：US08384149B2
公开(公告)日：2013-02-26
申请号：US11785608
申请日：2007-04-19
申请人： Shih Wei Wang , Te-Hsun Hsu , Hung-Cheng Sung
发明人： Shih Wei Wang , Te-Hsun Hsu , Hung-Cheng Sung
IPC分类号： H01L29/788
CPC分类号： H01L29/7883 , H01L27/115 , H01L29/42336
摘要： A semiconductor memory device includes a substrate, and a trench formed in the substrate. First and second floating gates, each associated with corresponding first and second memory cells, extend into the trench. Since the trench can be made relatively deep, the floating gates may be made relatively large while the lateral dimensions of the floating gates remains small. Moreover, the insulator thickness between the floating gate and a sidewall of the trench where a channel region is formed can be made relatively thick, even though the lateral extent of the memory cell is reduced. A programming gate extends into the trench between the first and second floating gates, and is shared, along with a source region, by the two memory cells.
摘要翻译：半导体存储器件包括衬底和形成在衬底中的沟槽。每个与对应的第一和第二存储器单元相关联的第一和第二浮动栅极延伸到沟槽中。由于可以使沟槽相对较深，所以可以使浮动栅极相对较大，同时浮动栅极的横向尺寸保持较小。此外，尽管存储单元的横向范围减小，浮栅和形成沟道区的沟槽的侧壁之间的绝缘体厚度可以做得相对较厚。编程门延伸到第一和第二浮栅之间的沟槽中，并且与源区域一起被两个存储单元共享。

3. 发明授权

US07880217B2 Programmable non-volatile memory (PNVM) device 有权
标题翻译：可编程非易失性存储器（PNVM）器件
公开(公告)号：US07880217B2
公开(公告)日：2011-02-01
申请号：US11192669
申请日：2005-07-30
申请人： Hung-Cheng Sung , Te-Hsun Hsu , Shih-Wei Wang
发明人： Hung-Cheng Sung , Te-Hsun Hsu , Shih-Wei Wang
IPC分类号： H01L29/788
CPC分类号： H01L29/7881 , H01L29/42324 , H01L29/66825
摘要： A programmable non-volatile memory (PNVM) device and method of forming the same compatible with CMOS logic device processes to improve a process flow, the PNVM device including a semiconductor substrate active area; a gate dielectric on the active area; a floating gate electrode on the gate dielectric; an inter-gate dielectric disposed over the floating gate electrode; and, a control gate damascene electrode extending through a dielectric insulating layer in electrical communication with the inter-gate dielectric, the control gate damascene electrode disposed over an upper portion of the floating gate electrode.
摘要翻译：一种可编程非易失性存储器（PNVM）器件和形成与CMOS逻辑器件工艺兼容的方法，以改善工艺流程，PNVM器件包括半导体衬底有源区; 有源区上的栅极电介质; 栅极电介质上的浮栅电极; 设置在所述浮栅上的栅极间电介质; 以及延伸穿过与所述栅极间电介质电连通的介电绝缘层的控制栅极镶嵌电极，所述控制栅极镶嵌电极设置在所述浮栅电极的上部。

4. 发明授权

US07663916B2 Logic compatible arrays and operations 有权
标题翻译：逻辑兼容阵列和操作
公开(公告)号：US07663916B2
公开(公告)日：2010-02-16
申请号：US11787291
申请日：2007-04-16
申请人： Yue-Der Chih , Te-Hsun Hsu
发明人： Yue-Der Chih , Te-Hsun Hsu
IPC分类号： G11C11/34
CPC分类号： G11C16/3427 , G11C16/0433 , G11C16/10 , H01L27/115 , H01L27/11521 , H01L27/11558
摘要： An array of memory cells arranged in a plurality of rows and a plurality of columns are provided. The array includes a first program line in a first direction, wherein the first program line is connected to program gates of memory cells in a first row of the array; a first erase line in the first direction, wherein the first erase line is connected to erase gates of the memory cells in the first row of the array; and a first word-line in the first direction, wherein the first word-line is connected to word-line nodes of the memory cells in the first row of the array.
摘要翻译：提供了布置成多行和多列的存储单元的阵列。阵列包括第一方向上的第一编程线，其中第一编程线连接到阵列的第一行中的存储器单元的编程门; 在第一方向上的第一擦除线，其中第一擦除线连接到阵列的第一行中的存储器单元的擦除栅极; 以及第一方向上的第一字线，其中第一字线连接到阵列的第一行中的存储器单元的字线节点。

5. 发明授权

US07608884B2 Scalable split-gate flash memory cell with high source-coupling ratio 有权
标题翻译：具有高源耦合比的可扩展分离式闪存单元
公开(公告)号：US07608884B2
公开(公告)日：2009-10-27
申请号：US11088492
申请日：2005-03-24
申请人： Te-Hsun Hsu , Hung-Cheng Sung
发明人： Te-Hsun Hsu , Hung-Cheng Sung
IPC分类号： H01L29/788
CPC分类号： H01L27/11521 , H01L21/28273 , H01L27/115 , H01L29/42324 , H01L29/66825 , H01L29/7883
摘要： A system and method provides an improved source-coupling ratio in flash memories. In one embodiment, a flash memory cell system with high source-coupling ratio includes at least a conventional floating gate device having a floating gate, a drain and a source. The floating gate is formed over a first junction for charging the floating gate by electron injection from the source to the floating gate and at least a first dielectric is layered on top of the floating gate to form a second junction. At least a first polycrystalline silicon is layered on top of the first dielectric, the first polycrystalline silicon electrically connected to the source. Electron tunneling provided through the second junction to the floating gate charges the floating gate, thereby increasing the source-coupling ratio of the floating gate and increasing the efficiency of storing electrical charge.
摘要翻译：系统和方法提供了闪存中改进的源耦合比。在一个实施例中，具有高源耦合比率的快闪存储器单元系统至少包括具有浮置栅极，漏极和源极的常规浮动栅极器件。浮置栅极形成在第一结上，用于通过从源极到浮置栅极的电子注入来对浮置栅极充电，并且至少第一电介质层叠在浮置栅极的顶部上以形成第二结。至少第一多晶硅层叠在第一电介质的顶部上，第一多晶硅电连接到源极。通过第二结提供到浮栅的电子隧穿对浮置栅极充电，从而增加浮栅的源极耦合比并提高存储电荷的效率。

6. 发明申请

US20060214214A1 Scalable spilt-gate flash memory cell with high source-coupling ratio 有权
标题翻译：具有高源耦合比的可扩展溢出栅闪存单元
公开(公告)号：US20060214214A1
公开(公告)日：2006-09-28
申请号：US11088492
申请日：2005-03-24
申请人： Te-Hsun Hsu , Hung-Cheng Sung
发明人： Te-Hsun Hsu , Hung-Cheng Sung
IPC分类号： H01L29/76
CPC分类号： H01L27/11521 , H01L21/28273 , H01L27/115 , H01L29/42324 , H01L29/66825 , H01L29/7883
摘要： A system and method provides an improved source-coupling ratio in flash memories. In one embodiment, a flash memory cell system with high source-coupling ratio includes at least a conventional floating gate device having a floating gate, a drain and a source. The floating gate is formed over a first junction for charging the floating gate by electron injection from the source to the floating gate and at least a first dielectric is layered on top of the floating gate to form a second junction. At least a first polycrystalline silicon is layered on top of the first dielectric, the first polycrystalline silicon electrically connected to the source. Electron tunneling provided through the second junction to the floating gate charges the floating gate, thereby increasing the source-coupling ratio of the floating gate and increasing the efficiency of storing electrical charge.
摘要翻译：系统和方法提供了闪存中改进的源耦合比。在一个实施例中，具有高源耦合比率的快闪存储器单元系统至少包括具有浮置栅极，漏极和源极的常规浮动栅极器件。浮置栅极形成在第一结上，用于通过从源极到浮置栅极的电子注入来对浮置栅极充电，并且至少第一电介质层叠在浮置栅极的顶部上以形成第二结。至少第一多晶硅层叠在第一电介质的顶部上，第一多晶硅电连接到源极。通过第二结提供到浮栅的电子隧穿对浮置栅极充电，从而增加浮栅的源极耦合比并提高存储电荷的效率。

7. 发明申请

US20050239247A1 Novel architecture to monitor isolation integrity between floating gate and source line 有权
标题翻译：监控浮动栅极和源极线之间隔离完整性的新型体系结构
公开(公告)号：US20050239247A1
公开(公告)日：2005-10-27
申请号：US10833179
申请日：2004-04-27
申请人： Chang-Jen Hsieh , Hung-Cheng Sung , Te-Hsun Hsu
发明人： Chang-Jen Hsieh , Hung-Cheng Sung , Te-Hsun Hsu
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8247 , H01L23/544 , H01L27/115
CPC分类号： H01L27/115 , H01L21/28273 , H01L22/34 , H01L27/11521 , H01L2924/0002 , H01L2924/00
摘要： A new method to form a floating gate isolation test structure in the manufacture of a memory device is achieved. The method comprises providing a substrate. A gate oxide layer is formed overlying the substrate. A floating gate conductor layer is deposited overlying the gate oxide layer. The floating gate conductor layer is patterned to expose the substrate for planned source regions. Ions are implanted into the exposed substrate to form the source regions. Contacting structures are formed to the source regions. Contacting structures are formed to the floating gate conductor layer.
摘要翻译：实现了在制造存储器件中形成浮栅隔离测试结构的新方法。该方法包括提供基底。栅极氧化层形成在衬底上。沉积栅极氧化物层的浮栅导体层。图案化浮栅导体层以暴露用于计划源区的衬底。将离子注入到暴露的基底中以形成源区。接触结构形成于源区。接触结构形成于浮栅导体层。

8. 发明授权

US08958245B2 Logic-based multiple time programming memory cell compatible with generic CMOS processes 有权
标题翻译：与通用CMOS工艺兼容的基于逻辑的多时间编程存储单元
公开(公告)号：US08958245B2
公开(公告)日：2015-02-17
申请号：US13483033
申请日：2012-05-29
申请人： Te-Hsun Hsu , Wei-Ren Chen , Wen-Hao Ching , Wen-Chuan Chang
发明人： Te-Hsun Hsu , Wei-Ren Chen , Wen-Hao Ching , Wen-Chuan Chang
IPC分类号： G11C16/04 , G11C16/06 , H01L27/115 , H01L29/66 , H01L29/788
CPC分类号： G11C16/0441 , G11C16/3418 , G11C2216/10 , H01L27/11519 , H01L27/11524 , H01L29/66825 , H01L29/7881
摘要： The non-volatile memory cell includes a coupling device and a first select transistor. The coupling device is formed in a first conductivity region. The first select transistor is serially connected to a first floating gate transistor and a second select transistor, all formed in a second conductivity region. An electrode of the coupling device and a gate of the first floating gate transistor are a monolithically formed floating gate; wherein the first conductivity region and the second conductivity region are formed in a third conductivity region; wherein the first conductivity region, the second conductivity region, and the third conductivity region are wells.
摘要翻译：非易失性存储单元包括耦合器件和第一选择晶体管。耦合装置形成在第一导电区域中。第一选择晶体管串联连接到第一浮栅晶体管和第二选择晶体管，全部形成在第二导电区域中。耦合器件的电极和第一浮栅晶体管的栅极是单片形成的浮栅; 其中所述第一导电区域和所述第二导电区域形成在第三导电区域中; 其中所述第一导电区域，所述第二导电区域和所述第三导电区域是孔。

9. 发明授权

US08941167B2 Erasable programmable single-ploy nonvolatile memory 有权
标题翻译：可擦除可编程单态非易失性存储器
公开(公告)号：US08941167B2
公开(公告)日：2015-01-27
申请号：US13415185
申请日：2012-03-08
申请人： Wei-Ren Chen , Te-Hsun Hsu , Shih-Chen Wang , Hsin-Ming Chen , Ching-Sung Yang
发明人： Wei-Ren Chen , Te-Hsun Hsu , Shih-Chen Wang , Hsin-Ming Chen , Ching-Sung Yang
IPC分类号： H01L29/788
CPC分类号： H01L29/42328 , G11C16/0408 , H01L27/11558 , H01L29/7885
摘要： An erasable programmable single-poly nonvolatile memory includes a first PMOS transistor comprising a select gate, a first p-type doped region, and a second p-type doped region, wherein the select gate is connected to a select gate voltage, and the first p-type doped region is connected to a source line voltage; a second PMOS transistor comprising the second p-type doped region, a third p-type doped region, and a floating gate, wherein the third p-type doped region is connected to a bit line voltage; and an erase gate region adjacent to the floating gate, wherein the erase gate region is connected to an erase line voltage.
摘要翻译：可擦除可编程单一多晶硅非易失性存储器包括包括选择栅极，第一p型掺杂区域和第二p型掺杂区域的第一PMOS晶体管，其中选择栅极连接到选择栅极电压，并且第一 p型掺杂区域连接到源极线电压; 包括第二p型掺杂区的第二PMOS晶体管，第三p型掺杂区和浮置栅，其中第三p型掺杂区连接到位线电压; 以及与浮置栅极相邻的擦除栅极区域，其中擦除栅极区域连接到擦除线电压。

10. 发明授权

US07968926B2 Logic non-volatile memory cell with improved data retention ability 有权
标题翻译：具有提高数据保留能力的逻辑非易失性存储单元
公开(公告)号：US07968926B2
公开(公告)日：2011-06-28
申请号：US12022943
申请日：2008-01-30
申请人： Chin-Yi Huang , Te-Hsun Hsu , Cheng Hsiang Huang
发明人： Chin-Yi Huang , Te-Hsun Hsu , Cheng Hsiang Huang
IPC分类号： H01L27/112
CPC分类号： H01L27/115 , G11C16/0441 , G11C2216/10 , H01L27/11521 , H01L27/11558
摘要： A memory cell includes a semiconductor substrate; and a first, a second, and a third transistor. The first transistor includes a first dielectric over the semiconductor substrate; and a first floating gate over the first dielectric. The second transistor is electrically coupled to the first transistor and includes a second dielectric over the semiconductor substrate; and a second floating gate over the second dielectric. The first and the second floating gates are electrically disconnected. The memory cell further includes a first capacitor; a second capacitor electrically coupled to the first capacitor; a third capacitor; a fourth capacitor electrically coupled to the third capacitor, wherein each of the first, the second, the third and the fourth capacitors includes the semiconductor substrate as one of the capacitor plates. The third transistor is a selector of the memory cell and is electrically coupled to the first and the second transistors.
摘要翻译：存储单元包括半导体衬底; 以及第一，第二和第三晶体管。第一晶体管包括半导体衬底上的第一电介质; 以及在第一电介质上的第一浮动栅极。第二晶体管电耦合到第一晶体管，并且在半导体衬底上包括第二电介质; 以及在第二电介质上的第二浮栅。第一和第二浮栅电气断开。存储单元还包括第一电容器; 电耦合到所述第一电容器的第二电容器; 第三电容器; 电耦合到第三电容器的第四电容器，其中第一，第二，第三和第四电容器中的每一个包括作为电容器板之一的半导体衬底。第三晶体管是存储单元的选择器，并且电耦合到第一和第二晶体管。

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