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1. 发明授权

US07326994B2 Logic compatible non-volatile memory cell 有权
标题翻译：逻辑兼容的非易失性存储单元
公开(公告)号：US07326994B2
公开(公告)日：2008-02-05
申请号：US11248357
申请日：2005-10-12
申请人： Te-Hsun Hsu , Hung-Cheng Sung , Wen-Ting Chu , Shih-Wei Wang
发明人： Te-Hsun Hsu , Hung-Cheng Sung , Wen-Ting Chu , Shih-Wei Wang
IPC分类号： H01L29/788
CPC分类号： H01L27/11521 , H01L27/115 , H01L27/11558
摘要： A non-volatile memory cell and a method of manufacturing the same are provided. The non-volatile memory cell includes a semiconductor substrate, a floating gate over the semiconductor substrate, a first, a second, and a third capacitor each having a first plate and sharing a common floating gate as a second plate. The non-volatile memory cell further includes a transistor connected in series with the first capacitor. The gate electrode of the transistor is connected to a wordline of a memory array, and a source/drain region is connected to a bitline.
摘要翻译：提供了一种非易失性存储单元及其制造方法。非易失性存储单元包括半导体衬底，半导体衬底上的浮置栅极，第一，第二和第三电容器，每个电容器具有第一板并且共用公共浮置栅极作为第二板。非易失性存储单元还包括与第一电容器串联连接的晶体管。晶体管的栅电极连接到存储器阵列的字线，源极/漏极区连接到位线。

2. 发明授权

US08384149B2 Memory cell having a shared programming gate 有权
标题翻译：具有共享编程门的存储单元
公开(公告)号：US08384149B2
公开(公告)日：2013-02-26
申请号：US11785608
申请日：2007-04-19
申请人： Shih Wei Wang , Te-Hsun Hsu , Hung-Cheng Sung
发明人： Shih Wei Wang , Te-Hsun Hsu , Hung-Cheng Sung
IPC分类号： H01L29/788
CPC分类号： H01L29/7883 , H01L27/115 , H01L29/42336
摘要： A semiconductor memory device includes a substrate, and a trench formed in the substrate. First and second floating gates, each associated with corresponding first and second memory cells, extend into the trench. Since the trench can be made relatively deep, the floating gates may be made relatively large while the lateral dimensions of the floating gates remains small. Moreover, the insulator thickness between the floating gate and a sidewall of the trench where a channel region is formed can be made relatively thick, even though the lateral extent of the memory cell is reduced. A programming gate extends into the trench between the first and second floating gates, and is shared, along with a source region, by the two memory cells.
摘要翻译：半导体存储器件包括衬底和形成在衬底中的沟槽。每个与对应的第一和第二存储器单元相关联的第一和第二浮动栅极延伸到沟槽中。由于可以使沟槽相对较深，所以可以使浮动栅极相对较大，同时浮动栅极的横向尺寸保持较小。此外，尽管存储单元的横向范围减小，浮栅和形成沟道区的沟槽的侧壁之间的绝缘体厚度可以做得相对较厚。编程门延伸到第一和第二浮栅之间的沟槽中，并且与源区域一起被两个存储单元共享。

3. 发明授权

US07880217B2 Programmable non-volatile memory (PNVM) device 有权
标题翻译：可编程非易失性存储器（PNVM）器件
公开(公告)号：US07880217B2
公开(公告)日：2011-02-01
申请号：US11192669
申请日：2005-07-30
申请人： Hung-Cheng Sung , Te-Hsun Hsu , Shih-Wei Wang
发明人： Hung-Cheng Sung , Te-Hsun Hsu , Shih-Wei Wang
IPC分类号： H01L29/788
CPC分类号： H01L29/7881 , H01L29/42324 , H01L29/66825
摘要： A programmable non-volatile memory (PNVM) device and method of forming the same compatible with CMOS logic device processes to improve a process flow, the PNVM device including a semiconductor substrate active area; a gate dielectric on the active area; a floating gate electrode on the gate dielectric; an inter-gate dielectric disposed over the floating gate electrode; and, a control gate damascene electrode extending through a dielectric insulating layer in electrical communication with the inter-gate dielectric, the control gate damascene electrode disposed over an upper portion of the floating gate electrode.
摘要翻译：一种可编程非易失性存储器（PNVM）器件和形成与CMOS逻辑器件工艺兼容的方法，以改善工艺流程，PNVM器件包括半导体衬底有源区; 有源区上的栅极电介质; 栅极电介质上的浮栅电极; 设置在所述浮栅上的栅极间电介质; 以及延伸穿过与所述栅极间电介质电连通的介电绝缘层的控制栅极镶嵌电极，所述控制栅极镶嵌电极设置在所述浮栅电极的上部。

4. 发明申请

US20070120172A1 Logic compatible non-volatile memory cell 有权
标题翻译：逻辑兼容的非易失性存储单元
公开(公告)号：US20070120172A1
公开(公告)日：2007-05-31
申请号：US11248357
申请日：2005-10-12
申请人： Te-Hsun Hsu , Hung-Cheng Sung , Wen-Ting Chu , Shih-Wei Wang
发明人： Te-Hsun Hsu , Hung-Cheng Sung , Wen-Ting Chu , Shih-Wei Wang
IPC分类号： H01L29/788
CPC分类号： H01L27/11521 , H01L27/115 , H01L27/11558
摘要： A non-volatile memory cell and a method of manufacturing the same are provided. The non-volatile memory cell includes a semiconductor substrate, a floating gate over the semiconductor substrate, a first, a second, and a third capacitor each having a first plate and sharing a common floating gate as a second plate. The non-volatile memory cell further includes a transistor connected in series with the first capacitor. The gate electrode of the transistor is connected to a wordline of a memory array, and a source/drain region is connected to a bitline.
摘要翻译：提供了一种非易失性存储单元及其制造方法。非易失性存储单元包括半导体衬底，半导体衬底上的浮置栅极，第一，第二和第三电容器，每个电容器具有第一板并且共用公共浮置栅极作为第二板。非易失性存储单元还包括与第一电容器串联连接的晶体管。晶体管的栅电极连接到存储器阵列的字线，源极/漏极区连接到位线。

5. 发明申请

US20080258200A1 Memory cell having a shared programming gate 有权
标题翻译：具有共享编程门的存储单元
公开(公告)号：US20080258200A1
公开(公告)日：2008-10-23
申请号：US11785608
申请日：2007-04-19
申请人： Shih Wei Wang , Te-Hsun Hsu , Hung-Cheng Sung
发明人： Shih Wei Wang , Te-Hsun Hsu , Hung-Cheng Sung
IPC分类号： H01L29/788
CPC分类号： H01L29/7883 , H01L27/115 , H01L29/42336
摘要： A semiconductor memory device includes a substrate, and a trench formed in the substrate. First and second floating gates, each associated with corresponding first and second memory cells, extend into the trench. Since the trench can be made relatively deep, the floating gates may be made relatively large while the lateral dimensions of the floating gates remains small. Moreover, the insulator thickness between the floating gate and a sidewall of the trench where a channel region is formed can be made relatively thick, even though the lateral extent of the memory cell is reduced. A programming gate extends into the trench between the first and second floating gates, and is shared, along with a source region, by the two memory cells.
摘要翻译：半导体存储器件包括衬底和形成在衬底中的沟槽。每个与对应的第一和第二存储器单元相关联的第一和第二浮动栅极延伸到沟槽中。由于可以使沟槽相对较深，所以可以使浮动栅极相对较大，同时浮动栅极的横向尺寸保持较小。此外，尽管存储单元的横向范围减小，浮栅和形成沟道区的沟槽的侧壁之间的绝缘体厚度可以做得相对较厚。编程门延伸到第一和第二浮栅之间的沟槽中，并且与源区域一起被两个存储单元共享。

6. 发明申请

US20070023822A1 Programmable non-volatile memory (PNVM) device 有权
标题翻译：可编程非易失性存储器（PNVM）器件
公开(公告)号：US20070023822A1
公开(公告)日：2007-02-01
申请号：US11192669
申请日：2005-07-30
申请人： Hung-Cheng Sung , Te-Hsun Hsu , Shih-Wei Wang
发明人： Hung-Cheng Sung , Te-Hsun Hsu , Shih-Wei Wang
IPC分类号： H01L29/788
CPC分类号： H01L29/7881 , H01L29/42324 , H01L29/66825
摘要： A programmable non-volatile memory (PNVM) device and method of forming the same compatible with CMOS logic device processes to improve a process flow, the PNVM device including a semiconductor substrate active area; a gate dielectric on the active area; a floating gate electrode on the gate dielectric; an inter-gate dielectric disposed over the floating gate electrode; and, a control gate damascene electrode extending through a dielectric insulating layer in electrical communication with the inter-gate dielectric, the control gate damascene electrode disposed over an upper portion of the floating gate electrode.
摘要翻译：一种可编程非易失性存储器（PNVM）器件和形成与CMOS逻辑器件工艺兼容的方法，以改善工艺流程，PNVM器件包括半导体衬底有源区; 有源区上的栅极电介质; 栅极电介质上的浮栅电极; 设置在所述浮栅上的栅极间电介质; 以及延伸穿过与所述栅极间电介质电连通的介电绝缘层的控制栅极镶嵌电极，所述控制栅极镶嵌电极设置在所述浮栅电极的上部。

7. 发明授权

US07335941B2 Uniform channel programmable erasable flash EEPROM 有权
标题翻译：统一通道可编程可擦除闪存EEPROM
公开(公告)号：US07335941B2
公开(公告)日：2008-02-26
申请号：US10890673
申请日：2004-07-14
申请人： Te-Hsun Hsu , Hung-Cheng Sung
发明人： Te-Hsun Hsu , Hung-Cheng Sung
IPC分类号： H01L29/792
CPC分类号： H01L29/66833 , H01L21/28282 , H01L29/792
摘要： A new method to form a split gate for a flash device in the manufacture of an integrated circuit device is achieved. The method comprises providing a substrate. A film is deposited overlying the substrate. The film comprises a second dielectric layer overlying a first dielectric layer with an electronic-trapping layer therebetween. A masking layer is deposited overlying the film. The masking layer and the film are patterned to expose a part of the substrate and to form a floating gate electrode comprising the electronic-trapping layer. An oxide layer is grown overlying the exposed part of the substrate. The masking layer is removed. A conductive layer is deposited overlying the oxide layer and the second dielectric layer. The conductive layer and the oxide layer are patterned to complete a control gate electrode comprising the conductive layer. The control gate electrode has a first part overlying the floating gate electrode and a second part not overlying the floating gate electrode.
摘要翻译：实现了在制造集成电路器件中形成用于闪存器件的分离栅极的新方法。该方法包括提供基底。覆盖在衬底上的膜被沉积。膜包括覆盖在第一电介质层之间的电子捕获层的第二电介质层。掩模层沉积在膜上。图案化掩模层和膜以暴露基板的一部分并形成包括电子捕获层的浮栅电极。生长在衬底的暴露部分上的氧化物层。去除掩模层。沉积覆盖氧化物层和第二介电层的导电层。图案化导电层和氧化物层以完成包括导电层的控制栅电极。控制栅电极具有覆盖浮置栅电极的第一部分和不覆盖浮置栅电极的第二部分。

8. 发明授权

US07608884B2 Scalable split-gate flash memory cell with high source-coupling ratio 有权
标题翻译：具有高源耦合比的可扩展分离式闪存单元
公开(公告)号：US07608884B2
公开(公告)日：2009-10-27
申请号：US11088492
申请日：2005-03-24
申请人： Te-Hsun Hsu , Hung-Cheng Sung
发明人： Te-Hsun Hsu , Hung-Cheng Sung
IPC分类号： H01L29/788
CPC分类号： H01L27/11521 , H01L21/28273 , H01L27/115 , H01L29/42324 , H01L29/66825 , H01L29/7883
摘要： A system and method provides an improved source-coupling ratio in flash memories. In one embodiment, a flash memory cell system with high source-coupling ratio includes at least a conventional floating gate device having a floating gate, a drain and a source. The floating gate is formed over a first junction for charging the floating gate by electron injection from the source to the floating gate and at least a first dielectric is layered on top of the floating gate to form a second junction. At least a first polycrystalline silicon is layered on top of the first dielectric, the first polycrystalline silicon electrically connected to the source. Electron tunneling provided through the second junction to the floating gate charges the floating gate, thereby increasing the source-coupling ratio of the floating gate and increasing the efficiency of storing electrical charge.
摘要翻译：系统和方法提供了闪存中改进的源耦合比。在一个实施例中，具有高源耦合比率的快闪存储器单元系统至少包括具有浮置栅极，漏极和源极的常规浮动栅极器件。浮置栅极形成在第一结上，用于通过从源极到浮置栅极的电子注入来对浮置栅极充电，并且至少第一电介质层叠在浮置栅极的顶部上以形成第二结。至少第一多晶硅层叠在第一电介质的顶部上，第一多晶硅电连接到源极。通过第二结提供到浮栅的电子隧穿对浮置栅极充电，从而增加浮栅的源极耦合比并提高存储电荷的效率。

9. 发明申请

US20060214214A1 Scalable spilt-gate flash memory cell with high source-coupling ratio 有权
标题翻译：具有高源耦合比的可扩展溢出栅闪存单元
公开(公告)号：US20060214214A1
公开(公告)日：2006-09-28
申请号：US11088492
申请日：2005-03-24
申请人： Te-Hsun Hsu , Hung-Cheng Sung
发明人： Te-Hsun Hsu , Hung-Cheng Sung
IPC分类号： H01L29/76
CPC分类号： H01L27/11521 , H01L21/28273 , H01L27/115 , H01L29/42324 , H01L29/66825 , H01L29/7883
摘要： A system and method provides an improved source-coupling ratio in flash memories. In one embodiment, a flash memory cell system with high source-coupling ratio includes at least a conventional floating gate device having a floating gate, a drain and a source. The floating gate is formed over a first junction for charging the floating gate by electron injection from the source to the floating gate and at least a first dielectric is layered on top of the floating gate to form a second junction. At least a first polycrystalline silicon is layered on top of the first dielectric, the first polycrystalline silicon electrically connected to the source. Electron tunneling provided through the second junction to the floating gate charges the floating gate, thereby increasing the source-coupling ratio of the floating gate and increasing the efficiency of storing electrical charge.
摘要翻译：系统和方法提供了闪存中改进的源耦合比。在一个实施例中，具有高源耦合比率的快闪存储器单元系统至少包括具有浮置栅极，漏极和源极的常规浮动栅极器件。浮置栅极形成在第一结上，用于通过从源极到浮置栅极的电子注入来对浮置栅极充电，并且至少第一电介质层叠在浮置栅极的顶部上以形成第二结。至少第一多晶硅层叠在第一电介质的顶部上，第一多晶硅电连接到源极。通过第二结提供到浮栅的电子隧穿对浮置栅极充电，从而增加浮栅的源极耦合比并提高存储电荷的效率。

10. 发明申请

US20050239247A1 Novel architecture to monitor isolation integrity between floating gate and source line 有权
标题翻译：监控浮动栅极和源极线之间隔离完整性的新型体系结构
公开(公告)号：US20050239247A1
公开(公告)日：2005-10-27
申请号：US10833179
申请日：2004-04-27
申请人： Chang-Jen Hsieh , Hung-Cheng Sung , Te-Hsun Hsu
发明人： Chang-Jen Hsieh , Hung-Cheng Sung , Te-Hsun Hsu
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8247 , H01L23/544 , H01L27/115
CPC分类号： H01L27/115 , H01L21/28273 , H01L22/34 , H01L27/11521 , H01L2924/0002 , H01L2924/00
摘要： A new method to form a floating gate isolation test structure in the manufacture of a memory device is achieved. The method comprises providing a substrate. A gate oxide layer is formed overlying the substrate. A floating gate conductor layer is deposited overlying the gate oxide layer. The floating gate conductor layer is patterned to expose the substrate for planned source regions. Ions are implanted into the exposed substrate to form the source regions. Contacting structures are formed to the source regions. Contacting structures are formed to the floating gate conductor layer.
摘要翻译：实现了在制造存储器件中形成浮栅隔离测试结构的新方法。该方法包括提供基底。栅极氧化层形成在衬底上。沉积栅极氧化物层的浮栅导体层。图案化浮栅导体层以暴露用于计划源区的衬底。将离子注入到暴露的基底中以形成源区。接触结构形成于源区。接触结构形成于浮栅导体层。

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