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1. 发明申请

US20130234227A1 ERASABLE PROGRAMMABLE SINGLE-PLOY NONVOLATILE MEMORY 有权
标题翻译：可擦除可编程的单槽非易失性存储器
公开(公告)号：US20130234227A1
公开(公告)日：2013-09-12
申请号：US13415185
申请日：2012-03-08
申请人： Wei-Ren Chen , Te-Hsun Hsu , Shih-Chen Wang , Hsin-Ming Chen , Ching-Sung Yang
发明人： Wei-Ren Chen , Te-Hsun Hsu , Shih-Chen Wang , Hsin-Ming Chen , Ching-Sung Yang
IPC分类号： H01L27/115
CPC分类号： H01L29/42328 , G11C16/0408 , H01L27/11558 , H01L29/7885
摘要： An erasable programmable single-poly nonvolatile memory includes a first PMOS transistor comprising a select gate, a first p-type doped region, and a second p-type doped region, wherein the select gate is connected to a select gate voltage, and the first p-type doped region is connected to a source line voltage; a second PMOS transistor comprising the second p-type doped region, a third p-type doped region, and a floating gate, wherein the third p-type doped region is connected to a bit line voltage; and an erase gate region adjacent to the floating gate, wherein the erase gate region is connected to an erase line voltage.
摘要翻译：可擦除可编程单一多晶硅非易失性存储器包括包括选择栅极，第一p型掺杂区域和第二p型掺杂区域的第一PMOS晶体管，其中选择栅极连接到选择栅极电压，并且第一 p型掺杂区域连接到源极线电压; 包括第二p型掺杂区的第二PMOS晶体管，第三p型掺杂区和浮置栅，其中第三p型掺杂区连接到位线电压; 以及与浮置栅极相邻的擦除栅极区域，其中擦除栅极区域连接到擦除线电压。

2. 发明授权

US08941167B2 Erasable programmable single-ploy nonvolatile memory 有权
标题翻译：可擦除可编程单态非易失性存储器
公开(公告)号：US08941167B2
公开(公告)日：2015-01-27
申请号：US13415185
申请日：2012-03-08
申请人： Wei-Ren Chen , Te-Hsun Hsu , Shih-Chen Wang , Hsin-Ming Chen , Ching-Sung Yang
发明人： Wei-Ren Chen , Te-Hsun Hsu , Shih-Chen Wang , Hsin-Ming Chen , Ching-Sung Yang
IPC分类号： H01L29/788
CPC分类号： H01L29/42328 , G11C16/0408 , H01L27/11558 , H01L29/7885
摘要： An erasable programmable single-poly nonvolatile memory includes a first PMOS transistor comprising a select gate, a first p-type doped region, and a second p-type doped region, wherein the select gate is connected to a select gate voltage, and the first p-type doped region is connected to a source line voltage; a second PMOS transistor comprising the second p-type doped region, a third p-type doped region, and a floating gate, wherein the third p-type doped region is connected to a bit line voltage; and an erase gate region adjacent to the floating gate, wherein the erase gate region is connected to an erase line voltage.
摘要翻译：可擦除可编程单一多晶硅非易失性存储器包括包括选择栅极，第一p型掺杂区域和第二p型掺杂区域的第一PMOS晶体管，其中选择栅极连接到选择栅极电压，并且第一 p型掺杂区域连接到源极线电压; 包括第二p型掺杂区的第二PMOS晶体管，第三p型掺杂区和浮置栅，其中第三p型掺杂区连接到位线电压; 以及与浮置栅极相邻的擦除栅极区域，其中擦除栅极区域连接到擦除线电压。

3. 发明申请

US20130234228A1 ERASABLE PROGRAMMABLE SINGLE-PLOY NONVOLATILE MEMORY 有权
标题翻译：可擦除可编程的单槽非易失性存储器
公开(公告)号：US20130234228A1
公开(公告)日：2013-09-12
申请号：US13572731
申请日：2012-08-13
申请人： Te-Hsun Hsu , Hsin-Ming Chen , Ching-Sung Yang , Wen-Hao Ching , Wei-Ren Chen
发明人： Te-Hsun Hsu , Hsin-Ming Chen , Ching-Sung Yang , Wen-Hao Ching , Wei-Ren Chen
IPC分类号： H01L27/115
CPC分类号： H01L27/11558 , G11C16/0433 , G11C2216/10 , H01L29/42328 , H01L29/7883 , H01L29/7885
摘要： An erasable programmable single-poly nonvolatile memory includes a floating gate transistor having a floating gate, a gate oxide layer under the floating gate, and a channel region; and an erase gate region, wherein the floating gate is extended to and is adjacent to the erase gate region. The gate oxide layer comprises a first portion above the channel region of the floating gate transistor and a second portion above the erase gate region, and a thickness of the first portion of the gate oxide layer is different from a thickness of the second portion of the gate oxide layer.
摘要翻译：可擦除可编程单一多晶硅非易失性存储器包括具有浮置栅极的浮栅晶体管，浮置栅极下方的栅极氧化物层和沟道区域; 和擦除栅极区，其中浮置栅极延伸到擦除栅极区并且与擦除栅极区相邻。栅极氧化物层包括位于浮动栅极晶体管的沟道区上方的第一部分和擦除栅极区上方的第二部分，并且栅极氧化物层的第一部分的厚度与第二部分的厚度不同栅氧化层。

4. 发明授权

US08592886B2 Erasable programmable single-ploy nonvolatile memory 有权
标题翻译：可擦除可编程单态非易失性存储器
公开(公告)号：US08592886B2
公开(公告)日：2013-11-26
申请号：US13572731
申请日：2012-08-13
申请人： Te-Hsun Hsu , Hsin-Ming Chen , Ching-Sung Yang , Wen-Hao Ching , Wei-Ren Chen
发明人： Te-Hsun Hsu , Hsin-Ming Chen , Ching-Sung Yang , Wen-Hao Ching , Wei-Ren Chen
IPC分类号： H01L29/788 , H01L29/06
CPC分类号： H01L27/11558 , G11C16/0433 , G11C2216/10 , H01L29/42328 , H01L29/7883 , H01L29/7885
摘要： An erasable programmable single-poly nonvolatile memory includes a floating gate transistor having a floating gate, a gate oxide layer under the floating gate, and a channel region; and an erase gate region, wherein the floating gate is extended to and is adjacent to the erase gate region. The gate oxide layer comprises a first portion above the channel region of the floating gate transistor and a second portion above the erase gate region, and a thickness of the first portion of the gate oxide layer is different from a thickness of the second portion of the gate oxide layer.
摘要翻译：可擦除可编程单一多晶硅非易失性存储器包括具有浮置栅极的浮动栅极晶体管，浮置栅极下方的栅极氧化物层和沟道区域; 和擦除栅极区，其中浮置栅极延伸到擦除栅极区并且与擦除栅极区相邻。栅极氧化物层包括位于浮动栅极晶体管的沟道区上方的第一部分和擦除栅极区上方的第二部分，并且栅极氧化物层的第一部分的厚度与第二部分的厚度不同栅氧化层。

5. 发明授权

US08705289B2 Flash memory apparatus with programming voltage control generators 有权
标题翻译：带编程电压控制发生器的闪存设备
公开(公告)号：US08705289B2
公开(公告)日：2014-04-22
申请号：US13344621
申请日：2012-01-06
申请人： Ching-Sung Yang , Wen-Hao Ching , Wei-Ming Ku , Yung-Hsiang Chen , Shih-Chen Wang , Hsin-Ming Chen
发明人： Ching-Sung Yang , Wen-Hao Ching , Wei-Ming Ku , Yung-Hsiang Chen , Shih-Chen Wang , Hsin-Ming Chen
IPC分类号： G11C16/06
CPC分类号： G11C16/10 , G11C16/12
摘要： A flash memory apparatus is provided. The flash memory apparatus includes a plurality of memory cells and a plurality of programming voltage control generators. Each of the memory cells receives a programming control voltage through a control end thereof, and executes data programming operation according to the programming control voltages. Each of the programming voltage control generators includes a pre-charge voltage transmitter and a pumping capacitor. The pre-charge voltage transmitter provides pre-charge voltage to the end of each of the corresponding memory cells according to pre-charge enable signal during a first period. A pumping voltage is provided to the pumping capacitor during a second period, and the programming control voltage is generated at the control end of each of the memory cells.
摘要翻译：提供一种闪存装置。闪存装置包括多个存储单元和多个编程电压控制发生器。每个存储单元通过其控制端接收编程控制电压，并根据编程控制电压执行数据编程操作。每个编程电压控制发生器包括预充电电压发射器和泵浦电容器。预充电电压发射器在第一时段期间根据预充电使能信号向每个相应存储器单元的末端提供预充电电压。在第二时段期间向泵浦电容器提供泵浦电压，并且在每个存储器单元的控制端产生编程控制电压。

6. 发明申请

US20120273860A1 NON-VOLATILE MEMORY UNIT CELL WITH IMPROVED SENSING MARGIN AND RELIABILITY 有权
标题翻译：非易失性存储器单元具有改进的传感和可靠性
公开(公告)号：US20120273860A1
公开(公告)日：2012-11-01
申请号：US13541755
申请日：2012-07-04
申请人： Hsin-Ming Chen , Shih-Chen Wang , Wen-Hao Ching , Yen-Hsin Lai , Hau-Yan Lu , Ching-Sung Yang
发明人： Hsin-Ming Chen , Shih-Chen Wang , Wen-Hao Ching , Yen-Hsin Lai , Hau-Yan Lu , Ching-Sung Yang
IPC分类号： H01L27/06
CPC分类号： H01L27/088 , G11C16/0458 , G11C16/28 , G11C16/3418
摘要： An only-one-polysilicon layer non-volatile memory unit cell includes a first P-type transistor, a second P-type transistor, a N-type transistor pair, a first and second coupling capacitors is provided. The N-type transistor pair has a third transistor and a fourth transistor that are connected. The third transistor and the fourth transistor have a first floating polysilicon gate and a second floating polysilicon gate to serve as charge storage mediums, respectively. One end of the second coupling capacitor is connected to the gate of the second transistor and is coupled to the second floating polysilicon gate, the other end of the second coupling capacitor receives a second control voltage. One end of the second coupling capacitor is connected to the gate of the second transistor and is coupled to the second floating polysilicon gate, the other end of the second coupling capacitor receives a second control voltage.
摘要翻译：唯一一多晶硅层非易失性存储单元包括第一P型晶体管，第二P型晶体管，N型晶体管对，第一和第二耦合电容器。 N型晶体管对具有连接的第三晶体管和第四晶体管。第三晶体管和第四晶体管分别具有第一浮置多晶硅栅极和第二浮置多晶硅栅极，用作电荷存储介质。第二耦合电容器的一端连接到第二晶体管的栅极并耦合到第二浮置多晶硅栅极，第二耦合电容器的另一端接收第二控制电压。第二耦合电容器的一端连接到第二晶体管的栅极并且耦合到第二浮置多晶硅栅极，第二耦合电容器的另一端接收第二控制电压。

7. 发明授权

US08199578B2 Single polysilicon layer non-volatile memory and operating method thereof 有权
标题翻译：单晶硅层非易失性存储器及其操作方法
公开(公告)号：US08199578B2
公开(公告)日：2012-06-12
申请号：US12792746
申请日：2010-06-03
申请人： Hsin-Ming Chen , Shih-Chen Wang , Wen-Hao Ching , Yen-Hsin Lai , Ching-Sung Yang
发明人： Hsin-Ming Chen , Shih-Chen Wang , Wen-Hao Ching , Yen-Hsin Lai , Ching-Sung Yang
IPC分类号： G11C16/04 , H01L29/788
CPC分类号： H01L27/11558 , G11C16/0433 , H01L27/11521 , H01L29/66825 , H01L29/7881
摘要： A single-polysilicon layer non-volatile memory having a floating gate transistor, a program gate and a control gate is provided. The floating gate transistor has a floating gate and a tunneling dielectric layer. The floating gate is disposed on a substrate. The tunneling dielectric layer is disposed between the floating gate and the substrate. The program gate, the control gate and the erase gate are respectively disposed in the substrate under the floating gate separated by the tunneling dielectric layer. Therefore, during a program operation and an erase operation, charges are injected in and expelled out through different regions of the tunneling dielectric layer, so as to increase reliability of the non-volatile memory.
摘要翻译：提供具有浮置栅晶体管，编程门和控制栅极的单多晶硅层非易失性存储器。浮栅晶体管具有浮置栅极和隧穿介电层。浮栅设置在基板上。隧道介电层设置在浮置栅极和衬底之间。编程栅极，控制栅极和擦除栅极分别设置在由隧道电介质层分离的浮置栅极下的衬底中。因此，在编程操作和擦除操作期间，通过隧道介电层的不同区域注入和排出电荷，以增加非易失性存储器的可靠性。

8. 发明申请

US20120087170A1 Single Polysilicon Non-Volatile Memory 有权
标题翻译：单多晶硅非易失性存储器
公开(公告)号：US20120087170A1
公开(公告)日：2012-04-12
申请号：US12899562
申请日：2010-10-07
申请人： Hau-Yan Lu , Ching-Sung Yang , Shih-Chen Wang , Hsin-Ming Chen
发明人： Hau-Yan Lu , Ching-Sung Yang , Shih-Chen Wang , Hsin-Ming Chen
IPC分类号： G11C17/04 , G11C17/00
CPC分类号： G11C17/16 , G11C17/18
摘要： A one-time-programmable memory device comprises a one-time-programmable memory cell array, a voltage pumping circuit, and a programming verification circuit. The one-time-programmable memory cell array comprises a plurality of memory cells. Each memory cell is arranged at an intersection of a bit line and a word line. The voltage pumping circuit comprises a plurality of local voltage boost circuits. Each local voltage boost circuit is shared by a corresponding memory cell of the plurality of memory cells. The programming verification circuit is coupled to the one-time-programmable memory cell array for verifying that conduction current of programmed memory cells of the plurality of memory cells is greater than a predetermined current level after programming. Each local boost circuit isolates leakage current of a corresponding programmed memory cell, and prevents programming voltage failure due to current overloading at a corresponding voltage pumping circuit.
摘要翻译：一次可编程存储器件包括一次可编程存储器单元阵列，电压泵浦电路和编程验证电路。一次可编程存储单元阵列包括多个存储单元。每个存储单元被布置在位线和字线的交点处。电压泵浦电路包括多个局部升压电路。每个本地升压电路由多个存储单元的相应存储单元共享。编程验证电路耦合到一次可编程存储单元阵列，用于在编程之后验证多个存储单元的编程存储单元的传导电流大于预定电流电平。每个本地升压电路隔离相应的编程存储单元的漏电流，并且防止由于在相应的电压泵浦电路处的电流过载导致的编程电压故障。

9. 发明申请

US20130176793A1 FLASH MEMORY APPARATUS 有权
标题翻译：闪存设备
公开(公告)号：US20130176793A1
公开(公告)日：2013-07-11
申请号：US13344621
申请日：2012-01-06
申请人： Ching-Sung Yang , Wen-Hao Ching , Wei-Ming Ku , Yung-Hsiang Chen , Shih-Chen Wang , Hsin-Ming Chen
发明人： Ching-Sung Yang , Wen-Hao Ching , Wei-Ming Ku , Yung-Hsiang Chen , Shih-Chen Wang , Hsin-Ming Chen
IPC分类号： G11C16/10
CPC分类号： G11C16/10 , G11C16/12
摘要： A flash memory apparatus is provided. The flash memory apparatus includes a plurality of memory cells and a plurality of programming voltage control generators. Each of the memory cells receives a programming control voltage through a control end thereof, and executes data programming operation according to the programming control voltages. Each of the programming voltage control generators includes a pre-charge voltage transmitter and a pumping capacitor. The pre-charge voltage transmitter provides pre-charge voltage to the end of each of the corresponding memory cells according to pre-charge enable signal during a first period. A pumping voltage is provided to the pumping capacitor during a second period, and the programming control voltage is generated at the control end of each of the memory cells.
摘要翻译：提供一种闪存装置。闪存装置包括多个存储单元和多个编程电压控制发生器。每个存储单元通过其控制端接收编程控制电压，并根据编程控制电压执行数据编程操作。每个编程电压控制发生器包括预充电电压发射器和泵浦电容器。预充电电压发射器在第一时段期间根据预充电使能信号向每个相应存储器单元的末端提供预充电电压。在第二时段期间向泵浦电容器提供泵浦电压，并且在每个存储器单元的控制端产生编程控制电压。

10. 发明授权

US08363475B2 Non-volatile memory unit cell with improved sensing margin and reliability 有权
标题翻译：非易失性存储单元，具有改进的感测裕度和可靠性
公开(公告)号：US08363475B2
公开(公告)日：2013-01-29
申请号：US12750650
申请日：2010-03-30
申请人： Hsin-Ming Chen , Shih-Chen Wang , Wen-Hao Ching , Yen-Hsin Lai , Hau-Yan Lu , Ching-Sung Yang
发明人： Hsin-Ming Chen , Shih-Chen Wang , Wen-Hao Ching , Yen-Hsin Lai , Hau-Yan Lu , Ching-Sung Yang
IPC分类号： G11C11/34
CPC分类号： H01L27/088 , G11C16/0458 , G11C16/28 , G11C16/3418
摘要： A non-volatile memory unit cell includes a first transistor pair and first and second control gates. The first transistor pair includes first and second transistors that are connected in series and of the same type. The first and second transistors have a first floating polysilicon gate and a second floating polysilicon gate, respectively. The first control gate is coupled to the first floating polysilicon gate through a tunneling junction and the second control gate is coupled to the second floating polysilicon gate through another tunneling junction.
摘要翻译：非易失性存储单元包括第一晶体管对以及第一和第二控制栅极。第一晶体管对包括串联和相同类型的第一和第二晶体管。第一和第二晶体管分别具有第一浮置多晶硅栅极和第二浮置多晶硅栅极。第一控制栅极通过隧道结耦合到第一浮动多晶硅栅极，并且第二控制栅极通过另一隧道结耦合到第二浮动多晶硅栅极。

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