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1. 发明授权

US09000511B2 Non-volatile memory device 有权
标题翻译：非易失性存储器件
公开(公告)号：US09000511B2
公开(公告)日：2015-04-07
申请号：US13529621
申请日：2012-06-21
申请人： Sung-Il Chang , Young-Woo Park
发明人： Sung-Il Chang , Young-Woo Park
IPC分类号： H01L29/792 , H01L27/115
CPC分类号： H01L21/764 , H01L21/76224 , H01L27/11563 , H01L27/11568 , H01L29/792
摘要： A non-volatile memory device includes a substrate having an active region defined by a device isolation region that has a trench and an air gap, a device isolation pattern positioned at a lower portion of the trench, a memory cell layer including a tunnel insulation layer, a trap insulation layer and a blocking insulation layer that are sequentially stacked on the active region and one of which extends from the active region toward the device isolation region encloses top of the air gap whose bottom is defined by a layer other than that of the top, and a control gate electrode positioned on the cell structure. The one of the insulation layer extending includes a recess at a region corresponding to the center of the air gap.
摘要翻译：非易失性存储器件包括具有由具有沟槽和气隙的器件隔离区限定的有源区的衬底，位于沟槽下部的器件隔离图案，包括隧道绝缘层的存储单元层，顺序堆叠在有源区上并且其中一个从有源区向器件隔离区延伸的陷阱绝缘层和阻挡绝缘层包围气隙的顶部，其底部由不同于顶部和位于电池结构上的控制栅电极。绝缘层延伸的一个包括在对应于气隙的中心的区域处的凹部。

2. 发明授权

US08877591B2 Methods of manufacturing vertical structure nonvolatile memory devices 有权
标题翻译：制造垂直结构非易失性存储器件的方法
公开(公告)号：US08877591B2
公开(公告)日：2014-11-04
申请号：US14092191
申请日：2013-11-27
申请人： Byeong-in Choe , Sung-il Chang , Chang-seok Kang , Jin-soo Lim
发明人： Byeong-in Choe , Sung-il Chang , Chang-seok Kang , Jin-soo Lim
IPC分类号： H01L21/336 , H01L29/78 , G11C16/04 , H01L29/66 , H01L29/792 , H01L27/115 , H01L29/788
CPC分类号： H01L29/66666 , G11C16/0466 , G11C16/0483 , H01L27/11551 , H01L27/11556 , H01L27/11578 , H01L29/66825 , H01L29/66833 , H01L29/7827 , H01L29/7889 , H01L29/7926
摘要： A vertical structure nonvolatile memory device can include a channel layer that extends in a vertical direction on a substrate. A memory cell string includes a plurality of transistors that are disposed on the substrate in the vertical direction along a vertical sidewall of the channel layer. At least one of the plurality of transistors includes at least one recess in a gate of the transistor into which at least one protrusion, which includes the channel layer, extends.
摘要翻译：垂直结构的非易失性存储器件可以包括在衬底上沿垂直方向延伸的沟道层。存储单元串包括沿着沟道层的垂直侧壁在垂直方向上设置在基板上的多个晶体管。多个晶体管中的至少一个晶体管包括在晶体管的栅极中的至少一个凹部，至少一个包括沟道层的突起延伸到该凹槽中。

3. 发明授权

US08872183B2 Three-dimensional semiconductor devices 有权
标题翻译：三维半导体器件
公开(公告)号：US08872183B2
公开(公告)日：2014-10-28
申请号：US13366057
申请日：2012-02-03
申请人： Sung-Il Chang , Changhyun Lee , Byoungkeun Son , Jin-Soo Lim
发明人： Sung-Il Chang , Changhyun Lee , Byoungkeun Son , Jin-Soo Lim
IPC分类号： H01L29/04 , H01L21/822 , H01L27/115 , H01L27/06
CPC分类号： H01L27/11582 , H01L21/02532 , H01L21/02595 , H01L21/31111 , H01L21/8221 , H01L27/0688 , H01L27/11556 , H01L29/4232 , H01L29/42372
摘要： Three-dimensional semiconductor devices are provided. The three-dimensional semiconductor device includes a substrate, a buffer layer on the substrate. The buffer layer includes a material having an etching selectivity relative to that of the substrate. A multi-layer stack including alternating insulation patterns and conductive patterns is provided on the buffer layer opposite the substrate. One or more active patterns respectively extend through the alternating insulation patterns and conductive patterns of the multi-layer stack and into the buffer layer. Related fabrication methods are also discussed.
摘要翻译：提供三维半导体器件。三维半导体器件包括衬底，衬底上的缓冲层。缓冲层包括具有相对于衬底的蚀刻选择性的材料。在与衬底相对的缓冲层上提供包括交替绝缘图案和导电图案的多层堆叠。一个或多个有源图案分别延伸穿过多层堆叠的交替绝缘图案和导电图案并进入缓冲层。还讨论了相关的制造方法。

4. 发明申请

US20120068245A1 NON-VOLATILE MEMORY DEVICES INCLUDING BLOCKING INSULATION PATTERNS WITH SUB-LAYERS HAVING DIFFERENT ENERGY BAND GAPS 有权
标题翻译：非易失性存储器件，包括具有不同能量带GAAS的子层的阻塞绝缘图案
公开(公告)号：US20120068245A1
公开(公告)日：2012-03-22
申请号：US13305930
申请日：2011-11-29
申请人： Ju-Hyung Kim , Sung-Il Chang , Chang-Seok Kang , Jung-Dal Choi
发明人： Ju-Hyung Kim , Sung-Il Chang , Chang-Seok Kang , Jung-Dal Choi
IPC分类号： H01L29/788 , H01L29/792
CPC分类号： H01L29/792 , H01L21/28273 , H01L21/28282 , H01L27/115 , H01L27/11517 , H01L27/11529 , H01L27/11563 , H01L27/11568 , H01L29/42324 , H01L29/4234 , H01L29/42348 , H01L29/51 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66825 , H01L29/66833 , H01L29/788 , H01L29/7883
摘要： A non-volatile memory device may include a semiconductor substrate and an isolation layer on the semiconductor substrate wherein the isolation layer defines an active region of the semiconductor substrate. A tunnel insulation layer may be provided on the active region of the semiconductor substrate, and a charge storage pattern may be provided on the tunnel insulation layer. An interface layer pattern may be provided on the charge storage pattern, and a blocking insulation pattern may be provided on the interface layer pattern. Moreover, the block insulation pattern may include a high-k dielectric material, and the interface layer pattern and the blocking insulation pattern may include different materials. A control gate electrode may be provided on the blocking insulating layer so that the blocking insulation pattern is between the interface layer pattern and the control gate electrode. Related methods are also discussed.
摘要翻译：非易失性存储器件可以包括半导体衬底和半导体衬底上的隔离层，其中隔离层限定半导体衬底的有源区。可以在半导体衬底的有源区上设置隧道绝缘层，并且可以在隧道绝缘层上设置电荷存储图案。可以在电荷存储图案上提供界面层图案，并且可以在界面层图案上提供阻挡绝缘图案。此外，块绝缘图案可以包括高k介电材料，并且界面层图案和阻挡绝缘图案可以包括不同的材料。可以在阻挡绝缘层上设置控制栅电极，使得阻挡绝缘图案位于界面层图案和控制栅电极之间。还讨论了相关方法。

5. 发明申请

US20120049268A1 THREE DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES AND METHODS OF FABRICATING THE SAME 有权
标题翻译：三维半导体存储器件及其制造方法
公开(公告)号：US20120049268A1
公开(公告)日：2012-03-01
申请号：US13222173
申请日：2011-08-31
申请人： Sung Il Chang , Young Woo Park , Jae Goo Lee
发明人： Sung Il Chang , Young Woo Park , Jae Goo Lee
IPC分类号： H01L29/792
CPC分类号： H01L27/11582 , H01L21/28273 , H01L21/28282 , H01L21/31111 , H01L27/11551 , H01L27/11556 , H01L27/11578 , H01L29/42324 , H01L29/4234
摘要： A 3D semiconductor device includes an electrode structure has electrodes stacked on a substrate, semiconductor patterns penetrating the electrode structure, charge storing patterns interposed between the semiconductor patterns and the electrode structure, and blocking insulating patterns interposed between the charge storing patterns and the electrode structure. Each of the blocking insulating patterns surrounds the semiconductor patterns, and the charge storing patterns are horizontally spaced from each other and configured in such a way as to each be disposed around a respective one of the semiconductor patterns. Also, each of the charge storing patterns includes a plurality of horizontal segments, each interposed between vertically adjacent ones of the electrodes.
摘要翻译：一种3D半导体器件包括：电极结构，其具有堆叠在基板上的电极，穿透电极结构的半导体图案，插入在半导体图案和电极结构之间的电荷存储图案，以及插入在电荷存储图案和电极结构之间的绝缘图案。每个隔离绝缘图案包围半导体图案，并且电荷存储图案彼此水平间隔并且以这样的方式配置，以使得每个隔离绝缘图案围绕相应的一个半导体图案设置。而且，每个电荷存储图案包括多个水平段，每个水平段插入垂直相邻的电极之间。

6. 发明申请

US20120043673A1 THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：三维半导体存储器件
公开(公告)号：US20120043673A1
公开(公告)日：2012-02-23
申请号：US13198234
申请日：2011-08-04
申请人： SUNG-IL CHANG , Youngwoo Park , Kwang Soo Seol
发明人： SUNG-IL CHANG , Youngwoo Park , Kwang Soo Seol
IPC分类号： H01L23/52
CPC分类号： H01L27/11551 , H01L27/11556 , H01L27/11578 , H01L29/66825 , H01L29/66833 , H01L29/7889 , H01L29/7926
摘要： Provided are three-dimensional semiconductor devices. A device includes an electrode structure including conductive patterns sequentially stacked on a substrate, a semiconductor pattern penetrating the electrode structure and including channel regions adjacent to the conductive patterns and vertical adjacent regions between the channel regions, and a semiconductor connecting layer extending from an outer sidewall of the semiconductor pattern to connect the semiconductor pattern to the substrate.
摘要翻译：提供三维半导体器件。一种器件包括：电极结构，包括依次层叠在衬底上的导电图案，穿透电极结构的半导体图案，以及包括与导电图案相邻的沟道区域和沟道区域之间的垂直相邻区域;以及从外侧壁延伸的半导体连接层的半导体图案以将半导体图案连接到基板。

7. 发明申请

US20110205802A1 NONVOLATILE MEMORY DEVICE AND METHOD OF READING THE SAME 审中-公开
标题翻译：非易失存储器件及其读取方法
公开(公告)号：US20110205802A1
公开(公告)日：2011-08-25
申请号：US13029947
申请日：2011-02-17
申请人： Byeong-In CHOE , Sung-Il Chang , Changseok Kang
发明人： Byeong-In CHOE , Sung-Il Chang , Changseok Kang
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C11/5642 , G11C16/26
摘要： Provided are a nonvolatile memory device and a method of reading the same. The nonvolatile memory device includes: a memory cell; a transistor disposed between a common source line and the memory cell; and a control logic for controlling a bias voltage of the transistor to reduce the amount of current flowing into the common source line during a read operation. The method includes: applying a read voltage to the memory cell; and controlling a bias voltage of the transistor to reduce the amount of current flowing into the common source line.
摘要翻译：提供一种非易失性存储器件及其读取方法。非易失性存储器件包括：存储单元; 设置在公共源极线和存储器单元之间的晶体管; 以及用于控制晶体管的偏置电压以减少在读取操作期间流入公共源极线的电流量的控制逻辑。该方法包括：向存储单元施加读取电压; 以及控制晶体管的偏置电压以减少流入公共源极线的电流量。

8. 发明申请

US20170103998A1 Vertical Semiconductor Devices and Methods of Manufacturing the Same 审中-公开
公开(公告)号：US20170103998A1
公开(公告)日：2017-04-13
申请号：US15288517
申请日：2016-10-07
申请人： Sung-il Chang , Jun-Hee LIM , Yong-Seok KIM , Tae-Young KIM , Jae-Sung SIM , Su-Jin AHN , Ji-Yeong HWANG
发明人： Sung-il Chang , Jun-Hee LIM , Yong-Seok KIM , Tae-Young KIM , Jae-Sung SIM , Su-Jin AHN , Ji-Yeong HWANG
IPC分类号： H01L27/115 , H01L29/66 , H01L21/265
CPC分类号： H01L27/11582 , H01L21/26513 , H01L27/11556 , H01L27/1157 , H01L27/11578 , H01L29/66666 , H01L29/66833 , H01L29/7827
摘要： In a method of manufacturing a vertical semiconductor device, an insulation layer and a sacrificial layer are alternatively and repeatedly formed on a substrate to define a structure. The structure is etched to form a hole therethrough that exposes the substrate. A first semiconductor pattern is formed in a lower portion of the hole, and a blocking pattern, a charge storage pattern, a tunnel insulation pattern and a first channel pattern are formed on a sidewall of the hole. A second channel pattern is formed on the first channel pattern and the semiconductor pattern, and a second semiconductor pattern is formed on a portion of the second channel pattern on the semiconductor pattern to define an upper channel pattern including the second channel pattern and the second semiconductor pattern. The sacrificial layers are replaced with a plurality of gates, respectively, including a conductive material.

9. 发明授权

US09536895B2 Methods of fabricating three-dimensional semiconductor devices 有权
标题翻译：制造三维半导体器件的方法
公开(公告)号：US09536895B2
公开(公告)日：2017-01-03
申请号：US14657849
申请日：2015-03-13
申请人： Changhyun Lee , Chanjin Park , Byoungkeun Son , Sung-Il Chang
发明人： Changhyun Lee , Chanjin Park , Byoungkeun Son , Sung-Il Chang
IPC分类号： H01L27/115
CPC分类号： H01L27/11582 , H01L27/11551 , H01L27/11556 , H01L27/11578 , H01L29/0649 , H01L29/7926
摘要： A three-dimensional semiconductor device includes an upper structure on a lower structure, the upper structure including conductive patterns, a semiconductor pattern connected to the lower structure through the upper structure, and an insulating spacer between the semiconductor pattern and the upper structure, a bottom surface of the insulating spacer being positioned at a vertical level equivalent to or higher than an uppermost surface of the lower structure.
摘要翻译：三维半导体器件包括下结构的上结构，上结构包括导电图案，通过上结构连接到下结构的半导体图案，以及半导体图案和上结构之间的绝缘间隔物，底部绝缘间隔物的表面位于等于或高于下部结构的最上表面的垂直水平。

10. 发明授权

US08952443B2 Three dimensional semiconductor memory devices and methods of fabricating the same 有权
标题翻译：三维半导体存储器件及其制造方法
公开(公告)号：US08952443B2
公开(公告)日：2015-02-10
申请号：US13222173
申请日：2011-08-31
申请人： Sung-Il Chang , Young Woo Park , Jae Goo Lee
发明人： Sung-Il Chang , Young Woo Park , Jae Goo Lee
IPC分类号： H01L29/792 , H01L27/115 , H01L21/28
CPC分类号： H01L27/11582 , H01L21/28273 , H01L21/28282 , H01L21/31111 , H01L27/11551 , H01L27/11556 , H01L27/11578 , H01L29/42324 , H01L29/4234
摘要： A 3D semiconductor device includes an electrode structure has electrodes stacked on a substrate, semiconductor patterns penetrating the electrode structure, charge storing patterns interposed between the semiconductor patterns and the electrode structure, and blocking insulating patterns interposed between the charge storing patterns and the electrode structure. Each of the blocking insulating patterns surrounds the semiconductor patterns, and the charge storing patterns are horizontally spaced from each other and configured in such a way as to each be disposed around a respective one of the semiconductor patterns. Also, each of the charge storing patterns includes a plurality of horizontal segments, each interposed between vertically adjacent ones of the electrodes.
摘要翻译：一种3D半导体器件包括：电极结构，其具有堆叠在基板上的电极，穿透电极结构的半导体图案，插入在半导体图案和电极结构之间的电荷存储图案，以及插入在电荷存储图案和电极结构之间的绝缘图案。每个隔离绝缘图案包围半导体图案，并且电荷存储图案彼此水平间隔并且以这样的方式配置，以使得每个隔离绝缘图案围绕相应的一个半导体图案设置。而且，每个电荷存储图案包括多个水平段，每个水平段插入垂直相邻的电极之间。

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