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1. 发明授权

US07461117B2 Floating point unit with fused multiply add and method for calculating a result with a floating point unit 失效
标题翻译：具有融合乘法的浮点单元和用浮点单元计算结果的方法
公开(公告)号：US07461117B2
公开(公告)日：2008-12-02
申请号：US11055812
申请日：2005-02-11
申请人： Son Dao Trong , Juergen Haess , Christian Jacobi , Klaus Michael Kroener , Silvia Melitta Mueller , Jochen Preiss
发明人： Son Dao Trong , Juergen Haess , Christian Jacobi , Klaus Michael Kroener , Silvia Melitta Mueller , Jochen Preiss
IPC分类号： G06F7/483
CPC分类号： G06F7/483 , G06F7/5443
摘要： The invention proposes a Floating Point Unit (1) with fused multiply add, with one addend operand (eb, fb) and two multiplicand operands (ea, fa; ec, fc), with a shift amount logic (2) which based on the exponents of the operands (ea, eb and ec) computes an alignment shift amount, with an alignment logic (3) which uses the alignment shift amount to align the fraction (fb) of the addend operand, with a multiply logic (4) which multiplies the fractions of the multiplicand operands (fa, fc), with a adder logic (5) which adds the outputs of the alignment logic (3) and the multiply logic (4), with a normalization logic (6) which normalizes the output of the adder logic (5), which is characterized in that a leading zero logic (7) is provided which computes the number of leading zeros of the fraction of the addend operand (fb), and that a compare logic (8) is provided which based on the number of leading zeros and the alignment shift amount computes select signals that indicate whether the most significant bits of the alignment logic (3) output have all the same value in order to: a) control the carry logic of the adder logic (5) and/or b) control a stage of the normalization logic (6).
摘要翻译：本发明提出了一种具有融合乘法运算的浮点单元（1），具有一个加数运算数（eb，fb）和两个被乘数运算符（ea，fa; ec，fc），其中移位量逻辑（2）基于操作数（ea，eb和ec）的指数利用对准逻辑（3）计算对准偏移量，该对准逻辑（3）使用对准移位量来对齐加数操作数的分数（fb）与乘法逻辑（4）将乘法器操作数（fa，fc）的分数与加法器逻辑（5）相乘，该逻辑（5）将对准逻辑（3）和乘法逻辑（4）的输出与归一化逻辑（6）进行归一化，归一化逻辑（6）加法器逻辑（5）的特征在于提供一个前导零逻辑（7），其计算加法运算数（fb）的分数的前导零的数量，并且提供比较逻辑（8）其基于前导零的数量和对准偏移量计算指示mo的选择信号对准逻辑（3）输出的高有效位具有全部相同的值，以便：a）控制加法器逻辑（5）的进位逻辑和/或b）控制归一化逻辑（6）的阶段。

2. 发明授权

US5912453A Multiple application chip card with decoupled programs 失效
标题翻译：具有解耦程序的多应用芯片卡
公开(公告)号：US5912453A
公开(公告)日：1999-06-15
申请号：US720162
申请日：1996-09-25
申请人： Klaus Gungl , Son Dao Trong
发明人： Klaus Gungl , Son Dao Trong
IPC分类号： G06F12/14 , G06F21/02 , G06F21/24 , G06K17/00 , G06K19/07 , G06K19/073 , G07F7/10 , G11C5/00 , G06K19/00
CPC分类号： G07F7/1008 , G06F12/145 , G06K19/072 , G06Q20/341 , G06Q20/35765
摘要： The integration of multiple application programs on one chip card is described, whereby the application programs stored on it do not have access to each other, which is achieved through a separation and de-coupling of the individual programs from one another. A first embodiment has several mutually-independent units, consisting respectively of a processor unit and a memory unit. Communication of these independent units with the external world and also with each other takes place through a control unit. A communication of the independent units with each other can only take place through the respective processor units, so that the linked memory units may not be accessed by circumvention of the processor unit. In a further embodiment, the separation of different applications on a chip card with only one processor takes place through the insertion of a separation of the application segments in the memory area of the chip card. The separation has as a result that each application may only access one predetermined area within the memory, and that access outside of the specified memory area is disabled for this application.
摘要翻译：描述了将多个应用程序集成在单个芯片卡上，由此存储在其上的应用程序不能彼此访问，这通过各个程序彼此的分离和解耦来实现。第一实施例具有分别由处理器单元和存储器单元组成的若干相互独立的单元。这些独立单位与外部世界的交流，也是通过控制单元进行的。独立单元彼此的通信只能通过相应的处理器单元进行，从而通过规避处理器单元可能不能访问所链接的存储器单元。在另一实施例中，通过在芯片卡的存储器区域中插入应用程序段的分离，仅在一个处理器的芯片卡上分离不同的应用程序。结果是，每个应用程序只能访问存储器内的一个预定区域，并且对该应用程序禁用对指定存储器区域之外的访问。

3. 发明授权

US5517438A Fast multiply-add instruction sequence in a pipeline floating-point processor 失效
标题翻译：快速乘法加法指令序列在流水线浮点处理器中
公开(公告)号：US5517438A
公开(公告)日：1996-05-14
申请号：US278522
申请日：1994-07-20
申请人： Son Dao-Trong , Juergen Haas , Rolf Mueller
发明人： Son Dao-Trong , Juergen Haas , Rolf Mueller
IPC分类号： G06F9/38 , G06F7/00 , G06F7/487 , G06F7/508 , G06F7/527 , G06F7/53 , G06F7/533 , G06F7/544 , G06F7/76 , G06F7/38
CPC分类号： G06F7/5443 , G06F2207/3884 , G06F7/483
摘要： A pipeline floating point processor in which the addition pipelining is reorganized so that no wait cycle is needed when the addition uses the result of an immediately foregoing multiplication (fast multiply-add instruction). The reorganization implies the following changes of an existing data flow of the pipeline floating processor: data feed-back via path ND of normalized data from the multiplier M into the aligners AL1 and AL2; shift left one digit feature on both sides of the data path for taking account of a possible leading zero digit of the product, and special zeroing of potential guard digits by Z1 and Z2; exponent build by 9 bits for overflow and underflow recognition, and due to an underflow the exponent result, is reset to zero on the fly by a true zero unit (T/C).
摘要翻译：一种流水线浮点处理器，其中重新组合加法流水线，使得当加法使用紧前相关乘法的结果（快速乘法指令）时，不需要等待周期。重组意味着流水线浮动处理器的现有数据流的以下改变：经由来自乘法器M的归一化数据的路径ND的数据反馈到对准器AL1和AL2; 考虑到产品的可能的前导零位，并且通过Z1和Z2对潜在的保护数字进行特殊归零，在数据路径的两侧左移一位数字特征; 指数由9位构成，用于溢出和下溢识别，并且由于下溢，指数结果将通过真零单位（T / C）在运行中复位为零。

4. 发明授权

US5506800A Self-checking complementary adder unit 失效
标题翻译：自检互补加法器单元
公开(公告)号：US5506800A
公开(公告)日：1996-04-09
申请号：US215997
申请日：1994-03-22
申请人： Son Dao-Trong
发明人： Son Dao-Trong
IPC分类号： G06F7/499 , G06F7/492 , G06F7/493 , G06F7/50 , G06F7/507 , G06F7/508 , G06F11/16 , G06F11/00
CPC分类号： G06F11/1608 , G06F11/10 , G06F7/507
摘要： A self-checking complementary adder unit used for high performance subtractions comprises two carry select adders (30 and 36) each of which consists of a pair of byte or digit organized ripple carry adders (31, 32 and 37, 38) generating in parallel virtual sums from true and complemented operands based on the assumption that the carry-in signal is 1 or 0. Depending on byte or digit carry signals generated by carry look ahead circuits (33, 39), partial sums are selected from the virtual sums to form a real sum. The outputs of both carry select adders are connected to a multiplexer (42) which is controlled by the high order carry-out signal from one of the carry look ahead circuits representing the sign of a real sum. The multiplexer selects one of the real sums as the result of a subtraction. A sum checker compares cross-wise the parity bits of the virtual sums from both carry select adders and also compares the related carry-out signals from both the ripple carry adders and carry look ahead circuits. The compare results are combined by a logic circuit to generate a result check signal.
摘要翻译：用于高性能减法的自检互补加法器单元包括两个进位选择加法器（30和36），每个进位选择加法器由一对字符或数字组织波纹携带加法器（31,32和37,38）组成，并行虚拟基于进位信号为1或0的假设，从真实和补充的操作数得到的总和。根据由携带前瞻电路（33,39）产生的字节或数字进位信号，从虚拟和中选择部分和一个真正的总和两个进位选择加法器的输出连接到多路复用器（42），该多路复用器（42）由表示真实和的符号的进位查看电路之一的高阶进位输出信号控制。多路复用器选择一个实数和作为减法的结果。和检查器将来自两个进位选择加法器的虚拟和的奇偶校验位进行交叉比较，并且还比较来自波纹携带加法器的相关进位输出信号并携带预先电路。比较结果由逻辑电路组合以产生结果检查信号。

5. 发明授权

US5363321A Digital circuit for calculating a logarithm of a number 失效
标题翻译：用于计算数字对数的数字电路
公开(公告)号：US5363321A
公开(公告)日：1994-11-08
申请号：US69954
申请日：1993-05-28
申请人： Son Dao Trong , Klaus Helwig , Markus Loch
发明人： Son Dao Trong , Klaus Helwig , Markus Loch
IPC分类号： G06F7/556 , G06F7/00
CPC分类号： G06F7/556
摘要： A digital circuit computes the logarithm of a number. The circuit makes the computation by first determining a multiplicity of factors f.sub.i from a predetermined set of factors such that the product of the multiplicity of factors f.sub.i and the number equals the base of the logarithm. A memory stores the logarithms of all the numbers in the predetermined set. The circuit then looks-up and sums the logarithms of the multiplicity of factors f.sub.i, and then subtracts the sum from one to yield the logarithm of the number.
摘要翻译：数字电路计算一个数字的对数。该电路通过首先从预定因子集合确定多项因子fi使得计算，使得多项因子f i和数量的乘积等于对数的基数。存储器存储预定集合中所有数字的对数。然后，电路查找并求和多项因子fi的对数，然后从一个减去总和以产生数字的对数。

6. 发明授权

US07730117B2 System and method for a floating point unit with feedback prior to normalization and rounding 失效
标题翻译：在归一化和舍入之前具有反馈的浮点单元的系统和方法
公开(公告)号：US07730117B2
公开(公告)日：2010-06-01
申请号：US11054110
申请日：2005-02-09
申请人： Bruce M. Fleischer , Juergen Haess , Michael Kroener , Martin S. Schmookler , Eric M. Schwarz , Son Dao-Trong
发明人： Bruce M. Fleischer , Juergen Haess , Michael Kroener , Martin S. Schmookler , Eric M. Schwarz , Son Dao-Trong
IPC分类号： G06F7/38 , G06F15/00
CPC分类号： G06F7/483 , G06F7/499 , G06F7/49936 , G06F7/49947 , G06F7/5443 , G06F2207/382
摘要： A system for performing floating point arithmetic operations including an input register adapted for receiving an operand. The system also includes a mechanism for performing a shift or masking operation in response to determining that the operand is in an un-normalized format. The system also includes instructions for performing single precision incrementing of the operand in response to determining that the operand is single precision, that the operand requires the incrementing based on the results of a previous operation and that the previous operation did not perform the incrementing. The operand was created in the previous operation. The system further includes instructions for performing double precision incrementing of the operand in response to determining that the operand is double precision, that the operand requires the incrementing based on the results of the previous operation and that the previous operation did not perform the incrementing.
摘要翻译：一种用于执行浮点算术运算的系统，包括适于接收操作数的输入寄存器。该系统还包括响应于确定操作数处于非归一化格式而执行移位或掩蔽操作的机制。该系统还包括用于响应于确定操作数是单一精度来执行操作数的单精度递增的指令，操作数需要基于先前操作的结果而增加，并且先前的操作未执行递增。操作数是在以前的操作中创建的。该系统还包括响应于确定操作数是双精度来执行操作数的双精度递增的指令，操作数需要基于先前操作的结果而增加，并且先前的操作不执行递增。

7. 发明授权

US07188233B2 System and method for performing floating point store folding 失效
标题翻译：执行浮点存储折叠的系统和方法
公开(公告)号：US07188233B2
公开(公告)日：2007-03-06
申请号：US11054686
申请日：2005-02-09
申请人： Juergen Haess , Michael Kroener , Dung Quoc Nguyen , Lawrence J. Powell, Jr. , Eric M. Schwarz , Son Dao-Trong , Raymond C. Yeung
发明人： Juergen Haess , Michael Kroener , Dung Quoc Nguyen , Lawrence J. Powell, Jr. , Eric M. Schwarz , Son Dao-Trong , Raymond C. Yeung
IPC分类号： G06F9/312
CPC分类号： G06F9/3826 , G06F9/30014 , G06F9/3824 , G06F9/3838 , G06F9/3885
摘要： A system for performing floating point arithmetic operations including a plurality of stages making up a pipeline, the stages including a first stage and a last stage. The system also includes a register file adapted for receiving a store instruction for input to the pipeline, where the data associated with the store instruction is dependent on a previous operation still in the pipeline. The system further includes a store register adapted for outputting the data associated with the store instruction to memory and a control unit having instructions. The instructions are directed to inputting the store instruction into the pipeline and to providing a path for forwarding the data associated with the store instruction from the last stage in the pipeline to the store register for use by the store instruction if the previous operation immediately precedes the store operation in the pipeline and if there is a data type match between the store instruction and the previous operation. In addition, the instructions are directed to inputting the store instruction into the pipeline and to providing a path for forwarding the data associated with the store instruction from the first stage in the pipeline to the store register for use by the store instruction if the previous operation precedes the store operation by one or more stage in the pipeline and if there is a data type match between the store instruction and the previous operation.
摘要翻译：一种用于执行浮点算术运算的系统，包括构成流水线的多个级，所述级包括第一级和最后级。该系统还包括适于接收用于输入到流水线的存储指令的寄存器文件，其中与存储指令相关联的数据依赖于仍在流水线中的先前操作。该系统还包括适于将与存储指令相关联的数据输出到存储器的存储寄存器和具有指令的控制单元。这些指令旨在将存储指令输入到流水线中，并且提供一个路径，用于将与流水线中的最后一级相关联的存储指令的数据转发到存储寄存器以供存储指令使用，如果先前的操作紧接在存储操作在流水线中，并且存储指令与先前操作之间存在数据类型匹配。此外，该指令旨在将存储指令输入到流水线中，并且提供用于将与流水线中的第一级相关联的存储指令的数据转发到存储寄存器以供存储指令使用的路径，如果先前的操作在存储操作之前在流水线中的一个或多个阶段，以及存储指令和先前操作之间是否存在数据类型匹配。

8. 发明申请

US20060179286A1 System and method for processing limited out-of-order execution of floating point loads 审中-公开
标题翻译：用于处理浮点负载有限次序执行的系统和方法
公开(公告)号：US20060179286A1
公开(公告)日：2006-08-10
申请号：US11054201
申请日：2005-02-09
申请人： Juergen Haess , Michael Kroener , Dung Nguyen , Eric Schwarz , Son Dao-Trong , Raymond Yeung
发明人： Juergen Haess , Michael Kroener , Dung Nguyen , Eric Schwarz , Son Dao-Trong , Raymond Yeung
IPC分类号： G06F9/44
CPC分类号： G06F9/3867 , G06F9/3838
摘要： A system for performing limited out-of order execution of floating point loads. The system includes a plurality of stages making up a pipeline, the stages including an early stage. The system also includes a mechanism for inputting an arithmetic instruction into the pipeline, the arithmetic instruction including a result address. The mechanism also determines if the arithmetic instruction causes a write after write (WAW) condition to occur before writing a result of the arithmetic instruction to the result address. The determining includes comparing the result address to a load address associated with a load instruction subsequent to the arithmetic instruction in the pipeline. The load data associated with the load instruction was written to the load address in the early stage of the pipeline. A WAW condition occurs if the result address is equal to the load address. Writing a result of the arithmetic instruction is suppressed in response to the WAW condition occurring.
摘要翻译：用于执行浮点负载有限次序执行的系统。该系统包括构成管道的多个阶段，这些阶段包括早期阶段。该系统还包括用于将算术指令输入流水线的机构，算术指令包括结果地址。该机制还确定在将算术指令的结果写入结果地址之前，算术指令是否在写入（WAW）条件之后发生写入。确定包括将结果地址与在流水线中的算术指令之后的加载指令相关联的加载地址进行比较。与加载指令相关联的加载数据在管道的早期阶段被写入加载地址。如果结果地址等于加载地址，则会发生WAW条件。响应于发生的WAW状态，写入算术指令的结果被抑制。

9. 发明申请

US20060179097A1 System and method for a floating point unit with feedback prior to normalization and rounding 失效
标题翻译：在归一化和舍入之前具有反馈的浮点单元的系统和方法
公开(公告)号：US20060179097A1
公开(公告)日：2006-08-10
申请号：US11054110
申请日：2005-02-09
申请人： Bruce Fleischer , Juergen Haess , Michael Kroener , Martin Schmookler , Eric Schwarz , Son Dao-Trong
发明人： Bruce Fleischer , Juergen Haess , Michael Kroener , Martin Schmookler , Eric Schwarz , Son Dao-Trong
IPC分类号： G06F7/38
CPC分类号： G06F7/483 , G06F7/499 , G06F7/49936 , G06F7/49947 , G06F7/5443 , G06F2207/382
摘要： A system for performing floating point arithmetic operations including an input register adapted for receiving an operand. The system also includes a mechanism for performing a shift or masking operation in response to determining that the operand is in an un-normalized format. The system also includes instructions for performing single precision incrementing of the operand in response to determining that the operand is single precision, that the operand requires the incrementing based on the results of a previous operation and that the previous operation did not perform the incrementing. The operand was created in the previous operation. The system further includes instructions for performing double precision incrementing of the operand in response to determining that the operand is double precision, that the operand requires the incrementing based on the results of the previous operation and that the previous operation did not perform the incrementing.
摘要翻译：一种用于执行浮点算术运算的系统，包括适于接收操作数的输入寄存器。该系统还包括响应于确定操作数处于非归一化格式而执行移位或掩蔽操作的机制。该系统还包括用于响应于确定操作数是单一精度来执行操作数的单精度递增的指令，操作数需要基于先前操作的结果而增加，并且先前的操作未执行递增。操作数是在以前的操作中创建的。该系统还包括响应于确定操作数是双精度来执行操作数的双精度递增的指令，操作数需要基于先前操作的结果而增加，并且先前的操作不执行递增。

10. 发明申请

US20060179096A1 System and method for a fused multiply-add dataflow with early feedback prior to rounding 审中-公开
标题翻译：在舍入前采用早期反馈的融合乘法加法数据流的系统和方法
公开(公告)号：US20060179096A1
公开(公告)日：2006-08-10
申请号：US11055232
申请日：2005-02-10
申请人： Bruce Fleischer , Juergen Haess , Michael Kroener , Robert Montoye , Martin Schmookler , Eric Schwarz , Son Dao-Trong
发明人： Bruce Fleischer , Juergen Haess , Michael Kroener , Robert Montoye , Martin Schmookler , Eric Schwarz , Son Dao-Trong
IPC分类号： G06F7/38
CPC分类号： G06F7/483 , G06F7/49947 , G06F7/5443
摘要： A system for performing floating point arithmetic operations including an input register adapted for receiving an operand. The system also includes computer instructions for performing single precision incrementing of the operand in response to determining that the operand is single precision, that the operand requires the incrementing based on the results of a previous operation and that the previous operation did not perform the incrementing. The operand was created in the previous operation. The system further includes instructions for performing double precision incrementing of the operand in response to determining that the operand is double precision, that the operand requires the incrementing based on the results of the previous operation and that the previous operation did not perform the incrementing.
摘要翻译：一种用于执行浮点算术运算的系统，包括适于接收操作数的输入寄存器。该系统还包括用于响应于确定操作数是单精度来执行操作数的单精度递增的计算机指令，操作数基于先前操作的结果需要增加，并且先前的操作未执行递增。操作数是在以前的操作中创建的。该系统还包括响应于确定操作数是双精度来执行操作数的双精度递增的指令，操作数需要基于先前操作的结果而增加，并且先前的操作不执行递增。

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