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1. 发明授权

US06517592B2 Cold trap assembly 有权
标题翻译：冷阱装配
公开(公告)号：US06517592B2
公开(公告)日：2003-02-11
申请号：US09740120
申请日：2000-12-19
申请人： Salvador P. Umotoy , Lawrence Chung-Lai Lei , Russell C. Ellwanger , Ronald L. Rose , Joel Huston , James Jin-Long Chen
发明人： Salvador P. Umotoy , Lawrence Chung-Lai Lei , Russell C. Ellwanger , Ronald L. Rose , Joel Huston , James Jin-Long Chen
IPC分类号： B01D4508
CPC分类号： B01D8/00 , C23C16/4412 , Y10S55/15 , Y10S55/30
摘要： A temperature-controlled exhaust assembly with cold trap capability. One embodiment of the exhaust assembly comprises a multi-heater design which allows for independent multi-zone closed-loop temperature control. Another embodiment comprises a compact multi-valve uni-body design incorporating a single heater for simplified closed-loop temperature control. The cold trap incorporates a heater for temperature control at the inlet of the trap to minimize undesirable deposits. One embodiment also comprises a multi-stage cold trap and a particle trap. As a removable unit, this cold trap provides additional safety in the handling and disposal of the adsorbed condensables.
摘要翻译：具有冷阱能力的温度控制排气组件。排气组件的一个实施例包括允许独立的多区域闭环温度控制的多加热器设计。另一个实施例包括紧凑的多阀单体设计，其包括用于简化闭环温度控制的单个加热器。冷阱包含一个加热器，用于在陷阱入口进行温度控制，以尽量减少不必要的沉积物。一个实施例还包括多级冷阱和颗粒捕集器。作为可拆卸单元，该冷阱在吸附的可冷凝物的处理和处理中提供了额外的安全性。

2. 发明授权

US6159299A Wafer pedestal with a purge ring 有权
标题翻译：晶圆座与清洗环
公开(公告)号：US6159299A
公开(公告)日：2000-12-12
申请号：US247673
申请日：1999-02-09
申请人： Keith K. Koai , Lawrence Chung-Lai Lei , Russell C. Ellwanger
发明人： Keith K. Koai , Lawrence Chung-Lai Lei , Russell C. Ellwanger
IPC分类号： H01L21/68 , C23C16/44 , C23C16/455 , C23C16/458 , H01L21/00 , H01L21/285 , H01L21/31 , H01L21/3205 , H01L21/687 , H01L23/52 , C23C16/00 , H04H1/00
CPC分类号： C23C16/45521 , C23C16/4583 , H01L21/67017 , H01L21/68735
摘要： A wafer pedestal with a purge ring that circumscribes a peripheral edge of the wafer pedestal. The purge ring contains plurality of passages that are located proximate the peripheral edge of said wafer pedestal such that purge gas is directed towards the peripheral edge. Additionally, the purge ring cooperates with an edge ring assembly that circumscribes the purge ring. The purge ring and the edge ring assembly allow a dual-purge flow pattern to be established, which significantly reduces the accumulation of undesirable deposits upon the wafer pedestal.
摘要翻译：具有环绕圆片基座的周缘的清洗环的晶片基座。清洗环包含位于所述晶片基座的周缘附近的多个通道，使得净化气体被引向周边边缘。此外，清洗环与限定清洗环的边缘环组件配合。清洗环和边缘环组件允许建立双清洗流动模式，这显着地减少了不期望的沉积物在晶片基座上的积聚。

3. 发明授权

US07223323B2 Multi-chemistry plating system 失效
标题翻译：多化学电镀系统
公开(公告)号：US07223323B2
公开(公告)日：2007-05-29
申请号：US10616284
申请日：2003-07-08
申请人： Michael X. Yang , Ming Xi , Russell C. Ellwanger , Eric B. Britcher , Bernardo Donoso , Lily L. Pang , Svetlana Sherman , Henry Ho , Anh N. Nguyen , Alexander N. Lerner , Allen L. D'Ambra , Arulkumar Shanmugasundram , Tetsuya Ishikawa , Yevgeniy Rabinovich , Dmitry Lubomirsky , Yeuk-Fai Edwin Mok , Son T. Nguyen
发明人： Michael X. Yang , Ming Xi , Russell C. Ellwanger , Eric B. Britcher , Bernardo Donoso , Lily L. Pang , Svetlana Sherman , Henry Ho , Anh N. Nguyen , Alexander N. Lerner , Allen L. D'Ambra , Arulkumar Shanmugasundram , Tetsuya Ishikawa , Yevgeniy Rabinovich , Dmitry Lubomirsky , Yeuk-Fai Edwin Mok , Son T. Nguyen
IPC分类号： C25B9/12 , C35D3/38 , B08B3/02
CPC分类号： H01L21/6719 , A23D7/00 , A23D7/005 , A23D7/01 , A23J7/00 , B08B3/02 , C25D7/123 , C25D17/001 , C25D17/002 , C25D17/02 , C25D21/02 , C25D21/08 , H01L21/67028 , H01L21/67034 , H01L21/67051 , H01L21/67109 , H01L21/6715 , H01L21/67196 , H01L21/6723 , H01L21/68 , H01L21/6838 , H01L21/68707
摘要： Embodiments of the invention generally provide an electrochemical plating system. The plating system includes a substrate loading station positioned in communication with a mainframe processing platform, at least one substrate plating cell positioned on the mainframe, at least one substrate bevel cleaning cell positioned on the mainframe, and a stacked substrate annealing station positioned in communication with at least one of the mainframe and the loading station, each chamber in the stacked substrate annealing station having a heating plate, a cooling plate, and a substrate transfer robot therein.
摘要翻译：本发明的实施方案通常提供电化学电镀系统。电镀系统包括位于与主机处理平台连通的基板装载站，位于主机上的至少一个基板镀覆单元，位于主机上的至少一个基板斜面清洁单元，以及与主机和加载站中的至少一个，层叠基板退火站中的每个室具有加热板，冷却板和基板传送机器人。

4. 发明授权

US06548402B2 Method of depositing a thick titanium nitride film 有权
标题翻译：沉积厚氮化钛膜的方法
公开(公告)号：US06548402B2
公开(公告)日：2003-04-15
申请号：US09330696
申请日：1999-06-11
申请人： Shulin Wang , Ming Xi , Frederick Wu , Ramanujapuram A. Srinivas , Yehuda Demayo , Zvi Lando , Mei Chang , Russell C. Ellwanger
发明人： Shulin Wang , Ming Xi , Frederick Wu , Ramanujapuram A. Srinivas , Yehuda Demayo , Zvi Lando , Mei Chang , Russell C. Ellwanger
IPC分类号： C23C1634
CPC分类号： H01L21/76846 , C23C16/34 , H01L21/28556 , H01L21/76877
摘要： A method of forming a titanium nitride (TiN) layer using a reaction between ammonia (NH3) and titanium tetrachloride (TiCl4). In one embodiment, an NH3:TiCl4 ratio of about 8.5 is used to deposit a TiN layer at a temperature of about 500° C. at a pressure of about 20 torr. In another embodiment, a composite TiN layer is formed by alternately depositing TiN layers of different thicknesses, using process conditions having different NH3:TiCl4 ratios. In one preferred embodiment, a TiN layer of less than about 20 Å is formed at an NH3:TiCl4 ratio of about 85, followed by a deposition of a thicker TiN layer at an NH3:TiCl4 ratio of about 8.5. By repeating the alternate film deposition using the two different process conditions, a composite TiN layer is formed. This composite TiN layer has an improved overall step coverage and reduced stress, compared to a standard TiN process, and is suitable for small geometry plug fill applications.
摘要翻译：使用氨（NH 3）与四氯化钛（TiCl 4）之间的反应形成氮化钛（TiN）层的方法。在一个实施方案中，使用约8.5的NH 3 :TiCl 4比率在约20托的压力下在约500℃的温度下沉积TiN层。在另一个实施例中，通过使用具有不同NH 3 :TiCl 4比率的工艺条件交替沉积不同厚度的TiN层来形成复合TiN层。在一个优选的实施方案中，以大约85的NH 3 :TiCl 4比例形成小于约的TiN层，然后以约8.5的NH 3 :TiCl 4比率沉积较厚的TiN层。通过使用两种不同的工艺条件重复替代膜沉积，形成复合TiN层。与标准TiN工艺相比，该复合TiN层具有改进的整体台阶覆盖和减小的应力，适用于小型几何填塞应用。

5. 发明授权

US06365495B2 Method for performing metallo-organic chemical vapor deposition of titanium nitride at reduced temperature 失效
标题翻译：在降低温度下进行氮化钛的金属有机化学气相沉积的方法
公开(公告)号：US06365495B2
公开(公告)日：2002-04-02
申请号：US09248183
申请日：1999-02-09
申请人： Shulin Wang , Huan Luo , Keith K. Koai , Ming Xi , Mei Chang , Russell C. Ellwanger
发明人： Shulin Wang , Huan Luo , Keith K. Koai , Ming Xi , Mei Chang , Russell C. Ellwanger
IPC分类号： H01L2128
CPC分类号： H01L21/76862 , C23C16/0245 , C23C16/34 , C23C16/4581 , C23C16/481 , C23C16/5096 , C23C16/56 , H01J37/32174 , H01J2237/336 , H01L21/28512 , H01L21/76841 , H01L21/76864
摘要： A process for chemical vapor deposition of titanium nitride film using thermal decomposition of a metal-organic compound is disclosed. In particular, the deposition of titanium nitride film from tetrakis dimethylamino-titanium (TDMAT) is performed at a temperature preferably below 350° C. in the presence of helium and nitrogen. The process is performed at a total pressure of about 5 torr, a nitrogen dilutant gas flow of at least 500 sccm, preferably about 1000 sccm, and an edge purge gas flow of at least 500 sccm. These process parameters, coupled with an improved thermal conduction between the wafer and the heated pedestal, lead to a conformal deposition of titanium nitride film at a rate of at least 6 Å/sec.
摘要翻译：公开了使用金属 - 有机化合物的热分解来进行氮化钛膜的化学气相沉积的方法。特别地，在氦和氮的存在下，在优选低于350℃的温度下，从四二甲基氨基钛（TDMAT）沉积氮化钛膜。该过程在约5托的总压力，至少500sccm，优选约1000sccm的氮稀释气流和至少500sccm的边缘吹扫气流中进行。这些工艺参数与晶片和加热基座之间的改善的热传导相结合，导致以至少6埃/秒的速率的氮化钛膜的共形沉积。

6. 发明授权

US06206971B1 Integrated temperature controlled exhaust and cold trap assembly 有权
标题翻译：集成温度控制排气和冷阱组件
公开(公告)号：US06206971B1
公开(公告)日：2001-03-27
申请号：US09281998
申请日：1999-03-29
申请人： Salvador P. Umotoy , Lawrence Chung-Lai Lei , Russell C. Ellwanger , Ronald L. Rose , Joel Huston , James Jin-Long Chen
发明人： Salvador P. Umotoy , Lawrence Chung-Lai Lei , Russell C. Ellwanger , Ronald L. Rose , Joel Huston , James Jin-Long Chen
IPC分类号： C23C1600
CPC分类号： B01D8/00 , C23C16/4412 , Y10S55/15 , Y10S55/30
摘要： A temperature-controlled exhaust assembly with cold trap capability. One embodiment of the exhaust assembly comprises a multi-heater design which allows for independent multi-zone closed-loop temperature control. Another embodiment comprises a compact multi-valve uni-body design incorporating a single heater for simplified closed-loop temperature control. The cold trap incorporates a heater for temperature control at the inlet of the trap to minimize undesirable deposits. One embodiment also comprises a multi-stage cold trap and a particle trap. As a removable unit, this cold trap provides additional safety in the handling and disposal of the adsorbed condensables.
摘要翻译：具有冷阱能力的温度控制排气组件。排气组件的一个实施例包括允许独立的多区域闭环温度控制的多加热器设计。另一个实施例包括紧凑的多阀单体设计，其包括用于简化闭环温度控制的单个加热器。冷阱包含一个加热器，用于在陷阱入口进行温度控制，以尽量减少不必要的沉积物。一个实施例还包括多级冷阱和颗粒捕集器。作为可拆卸单元，该冷阱在吸附的可冷凝物的处理和处理中提供了额外的安全性。

7. 发明授权

US4892843A Method of manufacturing a semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US4892843A
公开(公告)日：1990-01-09
申请号：US290921
申请日：1988-12-28
申请人： Johannes E. J. Schmitz , Antonius J. M. Van Dijk , Russell C. Ellwanger
发明人： Johannes E. J. Schmitz , Antonius J. M. Van Dijk , Russell C. Ellwanger
IPC分类号： C23C16/14 , H01L21/28 , H01L21/285 , H01L21/3205 , H01L21/768 , H01L23/52 , H01L23/532
CPC分类号： H01L21/32051 , H01L21/28556 , H01L21/76877 , H01L23/53257 , H01L2924/0002
摘要： The invention relates to a method of manufacturing a semiconductor device, in which a tungsten layer is provided on a surface of a substrate by reduction of tungsten hexafluoride with hydrogen.According to the invention, the contact resistance of the tungsten with the substrate is considerably reduced by first providing a tungsten layer on the substrate by reduction of tungsten hexafluoride with silane.

8. 发明授权

US4594769A Method of forming insulator of selectively varying thickness on patterned conductive layer 失效
标题翻译：在图案化导电层上形成选择性变化厚度的绝缘体的方法
公开(公告)号：US4594769A
公开(公告)日：1986-06-17
申请号：US621001
申请日：1984-06-15
申请人： Russell C. Ellwanger
发明人： Russell C. Ellwanger
IPC分类号： H01L21/3213 , H01L21/3105 , H01L21/311 , H01L21/3205 , H01L21/465
CPC分类号： H01L21/31116 , H01L21/31055
摘要： A structure having substantial surface evenness is created by a method in which an insulating layer (24) that has an upward protrusion (26) is formed on a patterned conductive layer (20) having a corresponding upward protrusion (22). A further layer (28) having a generally planar surface is formed on the insulating layer. Using an etchant that attacks the further layer much more than the insulating layer, the further layer is etched to expose at least part of the insulating protrusion. The further layer and the insulating layer (as it becomes exposed) are then etched with an etchant that attacks both of them at rates not substantially different from each other. This brings the upper surface down without exposing the conductive layer, particularly its upward protrusion.
摘要翻译：通过在具有相应的向上突起（22）的图案化导电层（20）上形成具有向上突起（26）的绝缘层（24）的方法产生具有实质表面均匀性的结构。在绝缘层上形成具有大致平坦表面的另一层（28）。使用比绝缘层更多的攻击另外的层的蚀刻剂，蚀刻另外的层以露出绝缘突起的至少一部分。然后用蚀刻剂蚀刻另外的层和绝缘层（当它暴露时），其蚀刻剂以彼此不显着不同的速率攻击它们。这使得上表面向下而不暴露导电层，特别是其向上突起。

9. 发明授权

US4816879A Schottky-type rectifier having controllable barrier height 失效
标题翻译：肖特基型整流器具有可控制的屏障高度
公开(公告)号：US4816879A
公开(公告)日：1989-03-28
申请号：US447745
申请日：1982-12-08
申请人： Russell C. Ellwanger
发明人： Russell C. Ellwanger
IPC分类号： H01L21/285 , H01L29/47 , H01L29/872 , H01L29/48 , H01L23/48 , H01L29/56 , H01L29/64
CPC分类号： H01L29/47 , H01L21/28537 , H01L29/872
摘要： A Schottky-type diode has a conductor-to-semiconductor barrier height .phi..sub.B that is controlled by adjusting the thickness of a metal silicide layer (22) which forms a rectifying junction (20) with an N-type semiconductor (24). The silicide layer is constituted with two or more metals such as platinum and nickel.
摘要翻译：肖特基型二极管具有通过调节与N型半导体（24）形成整流结（20）的金属硅化物层（22）的厚度来控制的导体与半导体势垒高度phi B。硅化物层由两种或更多种金属构成，例如铂和镍。

10. 发明授权

US4946803A Method for manufacturing a Schottky-type rectifier having controllable barrier height 失效
标题翻译：制造具有可控壁垒的肖特基型整流器的方法
公开(公告)号：US4946803A
公开(公告)日：1990-08-07
申请号：US282232
申请日：1988-12-08
申请人： Russell C. Ellwanger
发明人： Russell C. Ellwanger
IPC分类号： H01L21/285 , H01L29/47 , H01L29/872
CPC分类号： H01L21/28537 , H01L29/47 , H01L29/872 , Y10S148/139 , Y10S148/14
摘要： A Schottky-type diode is fabricated by a process that enables the diodes conductor-to-semiconductor barrier height .phi..sub.B to be controlled by adjusting the thickness of a metal silicide layer (22) which forms a rectifying junction (20) with an N-type semiconductor (24). In fabricating one version of the diode, a metallic layer (70) consisting of two or more metals such as platinum and nickel is deposited on an N-type silicon semiconductor (68) and heated to create a metal silicide layer (72) consisting of a lower layer (62) and an upper layer (74) of different average composition. A portion of the upper layer is then removed, allowing .phi..sub.B to be adjusted suitably.
摘要翻译：肖特基型二极管是通过一种工艺来制造的，该工艺能够通过调节形成整流结（20）的金属硅化物层（22）的厚度来控制二极管导体到半导体势垒高度phi B，型半导体（24）。在制造二极管的一个版本中，将由两种或更多种金属（例如铂和镍）组成的金属层（70）沉积在N型硅半导体（68）上并加热以形成金属硅化物层（72），其由下层（62）和不同平均组成的上层（74）。然后去除上层的一部分，允许适当地调节phi B.

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