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1. 发明授权

US6087894A Low power precision current reference 失效
标题翻译：低功率精密电流参考
公开(公告)号：US6087894A
公开(公告)日：2000-07-11
申请号：US32877
申请日：1998-03-02
申请人： Raymond Louis Barrett, Jr. , Barry W. Herold , Scott Humphreys , Lawrence L. Case
发明人： Raymond Louis Barrett, Jr. , Barry W. Herold , Scott Humphreys , Lawrence L. Case
IPC分类号： G05F3/26 , G05F3/02
CPC分类号： G05F3/262
摘要： A first complementary metal oxide semiconductor (CMOS) current reference circuit (100, 500) has a first and a second current mirror (110, 150) and is implemented using one of bulk wafer technology and silicon on insulator (SOI) technology. The first current mirror (110) has an output stage (130) that includes at least one cascode coupled field effect transistor (FET) (125) having one of a source tied well (when implemented using bulk wafer technology) or a source tied body (when implemented using SOI technology). A second CMOS current reference circuit (600, 800) has a first and a second current mirror (650, 610) and is implemented using SOI technology. The first current mirror (650) has a first bias FET (161) having a gate tied body.
摘要翻译：第一互补金属氧化物半导体（CMOS）电流参考电路（100,500）具有第一和第二电流镜（110,150），并且使用体晶片技术和绝缘体上硅（SOI）技术之一来实现。第一电流镜（110）具有输出级（130），该输出级包括至少一个共源共栅耦合场效应晶体管（FET）（125），其具有源极连接（当使用体晶片技术实现时）或源极体（使用SOI技术实现时）。第二CMOS电流参考电路（600,800）具有第一和第二电流镜（650,610），并且使用SOI技术来实现。第一电流镜（650）具有具有门接合体的第一偏置FET（161）。

2. 发明授权

US5880619A Low power precision voltage splitter 失效
标题翻译：低功率精密分压器
公开(公告)号：US5880619A
公开(公告)日：1999-03-09
申请号：US990548
申请日：1997-12-15
申请人： Raymond Louis Barrett, Jr. , Barry W. Herold , Grazyna A. Pajunen
发明人： Raymond Louis Barrett, Jr. , Barry W. Herold , Grazyna A. Pajunen
IPC分类号： G05F3/24 , G05F1/10 , G05F3/316
CPC分类号： G05F3/247
摘要： A voltage splitter circuit (100) that generates a one-half supply voltage includes a first switched operational transconductance amplifier (switched OTA) (120), a first transistor switch (110) that is controlled by a first clock signal (108) to periodically switch a first supply voltage (135) to a non-inverting input (118) of the first switched OTA, a second switched OTA (115), a second transistor switch (105) that is controlled by an inverted second clock signal (104) to periodically switch a second supply voltage (130) to a non-inverting input (114) of the second switched OTA, a commutating capacitor (112) coupled between the non-inverting input of the first switched OTA and the non-inverting input of the second switched OTA, a first filter capacitor (145) coupled to an output (121) of the first switched OTA, a second filter capacitor (140) coupled to an output (116) of the second switched OTA, and a third switched OTA (125). The first and second clock signals are non-overlapping.
摘要翻译：产生二分之一电源电压的分压器电路（100）包括第一开关操作跨导放大器（开关OTA）（120），由第一时钟信号（108）控制的第一晶体管开关（110）将第一电源电压（135）切换到第一开关OTA的非反相输入端（118），第二开关OTA（115），由反相第二时钟信号（104）控制的第二晶体管开关（105）周期性地将第二电源电压（130）切换到第二开关OTA的非反相输入端（114）;耦合在第一开关OTA的非反相输入端和第一开关OTA的非反相输入端之间的整流电容器（112）第二开关OTA，耦合到第一开关OTA的输出（121）的第一滤波电容器（145），耦合到第二开关OTA的输出端（116）的第二滤波电容器（140）和第三开关OTA （125）。第一和第二时钟信号是不重叠的。

3. 发明授权

US5793825A Method and apparatus for extending an operating frequency range of an instantaneous phase-frequency detector 失效
标题翻译：用于延长瞬时相位频率检测器的工作频率范围的方法和装置
公开(公告)号：US5793825A
公开(公告)日：1998-08-11
申请号：US610034
申请日：1996-03-04
申请人： Scott Robert Humphreys , Raymond Louis Barrett, Jr. , Barry W. Herold
发明人： Scott Robert Humphreys , Raymond Louis Barrett, Jr. , Barry W. Herold
IPC分类号： H03L7/093 , H03D3/24 , H03L7/00 , H04L27/14
CPC分类号： H03L7/093
摘要： A method is used by a detector (102) for extending the operating frequency range of a phase lock loop (100). The detector (102) detects a phase-frequency difference between a reference signal (109) and a generated signal (108) of the phase lock loop (100). The detector (102) includes a divider (202) for counting transitions of the generated signal (108) and a logic element (204) and counter (212) for detecting when the frequency of the generated signal (108) is such that the divider (202) operates outside its linear frequency range in relation to a predetermined transition of the reference signal (109). The detector (102) further includes a register (206) for recording a phase value of the divider (202) coincident with the predetermined transition, or a constant phase value (304, 306) when the frequency of the generated signal (108) is operating outside of the linear range of the divider (202).
摘要翻译：检测器（102）使用一种方法来扩展锁相环（100）的工作频率范围。检测器（102）检测参考信号（109）和锁相环（100）的产生信号（108）之间的相位 - 频率差。检测器（102）包括用于对生成的信号（108）和逻辑元件（204）和计数器（212）的转换进行计数的分频器（202），用于检测所产生的信号（108）的频率何时使分频器（202）相对于参考信号（109）的预定转换在其线性频率范围之外操作。检测器（102）还包括一个寄存器（206），用于当所产生的信号（108）的频率为（108）为...时，用于记录与预定转换一致的分频器的相位值或恒定相位值（304,306）操作在分压器（202）的线性范围之外。

4. 发明授权

US06275540B1 Selective call receiver having an apparatus for modifying an analog signal to a digital signal and method therefor 失效
标题翻译：具有用于将模拟信号修改为数字信号的装置的选择性呼叫接收机及其方法
公开(公告)号：US06275540B1
公开(公告)日：2001-08-14
申请号：US08941913
申请日：1997-10-01
申请人： Raymond Louis Barrett, Jr. , James G. Mittel , Barry W. Herold
发明人： Raymond Louis Barrett, Jr. , James G. Mittel , Barry W. Herold
IPC分类号： H04L2706
CPC分类号： H04B1/0003 , H03M3/40 , H03M3/43 , H03M3/456 , H04B1/30
摘要： A selective call receiver (500) includes a radio receiver (501) and a processor (508). The radio receiver includes an antenna (502), a combination circuit (204), a bandpass filter (208), mixers (212, 214), analog-to-digital converters (222, 224), digital mixers (234, 236), a second combination circuit (242), and a digital-to-analog converter (246). The combination circuit receives an analog signal from the antenna and combines the same with an analog feedback signal generated by the digital-to-analog converter. The bandpass filter filters the output of the combination circuit and supplies its output to the mixers which down-convert the signal to baseband signals. These signals are modified by the analog-to-digital converters to digital signals which are up-converted by the digital mixers. The outputs of the digital mixers are combined by the second combination circuit to a digital output that is modified by the digital-to-analog converter to the analog feedback signal.
摘要翻译：选呼接收机（500）包括无线接收机（501）和处理器（508）。无线电接收机包括天线（502），组合电路（204），带通滤波器（208），混频器（212,214），模拟 - 数字转换器（222,224），数字混频器（234,236），第二组合电路（242）和数模转换器（246）。组合电路从天线接收模拟信号，并将其与数模转换器产生的模拟反馈信号相组合。带通滤波器对组合电路的输出进行滤波，并将其输出提供给将信号下变频为基带信号的混频器。这些信号被模数转换器修改为由数字混频器进行上变频的数字信号。数字混频器的输出由第二组合电路组合到由数模转换器修改为模拟反馈信号的数字输出。

5. 发明授权

US06218973B1 Binary random number generator 有权
标题翻译：二进制随机数发生器
公开(公告)号：US06218973B1
公开(公告)日：2001-04-17
申请号：US09262933
申请日：1999-03-05
申请人： Raymond Louis Barrett, Jr. , Barry W. Herold
发明人： Raymond Louis Barrett, Jr. , Barry W. Herold
IPC分类号： H03M300
CPC分类号： H04L9/001 , G06F7/588
摘要： A random number generator includes a sample clock having a sample clock rate, a chaotic oscillator having a characteristic upper frequency, and an output section. The chaotic oscillator includes a quantized linear section and a non-linear section. The quantized linear section includes multiple quantized integrators coupled to the sample clock and intercoupled in a linear intercoupling. The non-linear section is coupled in a feedback manner with the quantized linear section. The output section generates a random binary output signal having the sample clock rate, formed by a logical combination of binary signals, of which one binary signal is generated by each of the multiple quantized integrators. Each quantized integrator includes an analog to digital converter that preferably includes a sigma delta converter that generates one of the binary signals.
摘要翻译：随机数发生器包括具有采样时钟频率的采样时钟，具有特征上限频率的混沌振荡器和输出部分。混沌振荡器包括量化的线性部分和非线性部分。量化的线性部分包括耦合到采样时钟的多个量化积分器并且以线性相互耦合相互耦合。非线性部分以反馈方式与量化的线性部分耦合。输出部分产生具有由二进制信号的逻辑组合形成的采样时钟速率的随机二进制输出信号，其中每个多个量化积分器产生一个二进制信号。每个量化积分器包括模数转换器，其优选地包括生成二进制信号之一的Σ-Δ转换器。

6. 发明授权

US5754598A Method and apparatus for controlling a phase lock loop 失效
标题翻译：用于控制锁相环的方法和装置
公开(公告)号：US5754598A
公开(公告)日：1998-05-19
申请号：US652054
申请日：1996-05-23
申请人： Raymond Louis Barrett, Jr. , Barry W. Herold , Grazyna Anna Pajunen
发明人： Raymond Louis Barrett, Jr. , Barry W. Herold , Grazyna Anna Pajunen
IPC分类号： H03L7/089 , H03L7/093 , H03L7/183 , H03D3/18 , H03D3/24
CPC分类号： H03L7/183 , H03L7/089 , H03L7/093
摘要： A phase lock loop of a synthesizer (143) is controlled by applying (506) modern optimal control techniques for a predetermined period in a computing engine (222), in response to an error being introduced into a signal of the phase lock loop, and by utilizing (510) classical control techniques for controlling the phase lock loop after the predetermined period.
摘要翻译：响应于引入到锁相环的信号中的误差，在计算引擎（222）中应用（506）现有的最优控制技术来控制合成器（143）的锁相环，并且通过利用（510）经典控制技术来控制预定时段之后的锁相环。

7. 发明授权

US5651037A Apparatus for preforming discrete-time analog queuing and computing in a communication system 失效
标题翻译：用于在通信系统中预处理离散时间模拟排队和计算的装置
公开(公告)号：US5651037A
公开(公告)日：1997-07-22
申请号：US538930
申请日：1995-10-04
申请人： Raymond Louis Barrett, Jr. , Barry W. Herold , Grazyna Anna Pajunen
发明人： Raymond Louis Barrett, Jr. , Barry W. Herold , Grazyna Anna Pajunen
IPC分类号： F02B75/02 , H03J1/00 , H03D3/24
CPC分类号： H03J1/0008 , F02B2075/027
摘要： A communication receiver (100) utilizing a synthesizer (143) employs a discrete-time phase locked loop which includes a reference oscillator (135), a phase error detector (202), a discrete-time analog computing element (206), an integrator (210), a controlled frequency generator (211, 212), and a frequency divider (214). The discrete-time analog computing element implements a discrete-time analog lead-lag network circuit. This circuit includes a clock and logic circuit (216), at least one discrete-time analog queuing element (218), and an analog computing engine (222). The queuing element (218) includes N analog signal lines, N analog storage lines, N control lines, and N.sup.2 controllable switches. Each controllable switch is coupled between each of the N analog signal lines and each of the N analog storage lines. In addition, N charge storage elements are coupled between each of the N analog storage lines and a common circuit node. The N control lines control the controllable switches in a predetermined sequence.
摘要翻译：利用合成器（143）的通信接收机（100）采用离散时间锁相环，其包括参考振荡器（135），相位误差检测器（202），离散时间模拟计算元件（206），积分器（210），受控频率发生器（211,212）和分频器（214）。离散时间模拟计算元件实现离散时间模拟超前延迟网络电路。该电路包括时钟和逻辑电路（216），至少一个离散时间模拟排队元件（218）和模拟计算引擎（222）。排队元件（218）包括N个模拟信号线，N个模拟存储线，N个控制线和N2个可控开关。每个可控开关耦合在N个模拟信号线和N个模拟存储线中的每一个之间。此外，N个电荷存储元件耦合在N个模拟存储线中的每一个和公共电路节点之间。 N个控制线以预定的顺序控制可控开关。

8. 发明授权

US5644743A Hybrid analog-digital phase error detector 失效
标题翻译：混合模拟数字相位误差检测器
公开(公告)号：US5644743A
公开(公告)日：1997-07-01
申请号：US567387
申请日：1995-12-04
申请人： Raymond Louis Barrett, Jr. , Barry W. Herold , Grazyna Anna Pajunen , Walter L. Davis
发明人： Raymond Louis Barrett, Jr. , Barry W. Herold , Grazyna Anna Pajunen , Walter L. Davis
IPC分类号： H03D13/00 , H03L7/087 , H03D3/24
CPC分类号： H03L7/087 , H03D13/00
摘要： A hybrid analog-digital phase error detector (107) is utilized for detecting a phase error between first and second clock signals (132, 104). Digital and analog phase error detectors (108, 116) are connected to the first and second clock signals (132, 104), and are utilized for producing digital and analog phase error values (110, 118). The digital and analog controllers (112, 120) connected to the digital and analog phase error detectors (108, 116) execute digital and analog control algorithms based on the digital and analog phase error values (110, 118) to produce digital and analog control signals (114, 122). A summer (124) connected to the outputs of the digital and analog controllers (112, 120) combines the analog control signal (122) and the digital control signal (114) to produce a composite control signal (126) representing the phase error.
摘要翻译：混合模拟数字相位误差检测器（107）用于检测第一和第二时钟信号（132,104）之间的相位误差。数字和模拟相位误差检测器（108,116）连接到第一和第二时钟信号（132,104），并用于产生数字和模拟相位误差值（110,118）。连接到数字和模拟相位误差检测器（108,116）的数字和模拟控制器（112,120）基于数字和模拟相位误差值（110,118）执行数字和模拟控制算法，以产生数字和模拟控制信号（114,122）。连接到数字和模拟控制器（112,120）的输出的加法器（124）组合模拟控制信号（122）和数字控制信号（114）以产生表示相位误差的复合控制信号（126）。

9. 发明授权

US06888573B2 Digital pixel sensor with anti-blooming control 失效
标题翻译：数字像素传感器具有防起霜控制
公开(公告)号：US06888573B2
公开(公告)日：2005-05-03
申请号：US10285250
申请日：2002-10-31
申请人： Barry W. Herold
发明人： Barry W. Herold
IPC分类号： H01L27/148 , H01L29/768 , H04N3/14 , H04N5/359 , H04N5/3745 , H04N9/64
CPC分类号： H04N5/37455 , H04N5/35527
摘要： An anti-blooming charge accumulation pixel using an anti-blooming element coupled to the pixel prevents blooming by ensuring that a voltage of a charge accumulation device of the pixel is always returned to a clamping voltage following comparison events. The anti-blooming element is used to return the voltage across a photodiode to the supply voltage when both a low voltage comparison and a high voltage comparison have occurred. A control block is used to determine an input signal to the anti-blooming element based upon the result of a low voltage comparison and a high voltage comparison. The input signal can be used to drive the anti-blooming element to a desired logic level, thereby causing the voltage across the charge accumulation device to be the clamping voltage. The use of the anti-blooming element eliminates blooming to adjacent pixels, independent of an integration time of the pixel.
摘要翻译：使用耦合到该像素的抗起霜元件的抗起霜电荷累积像素通过确保像素的电荷累积装置的电压在比较事件之后总是返回到钳位电压来防止起霜。当发生低电压比较和高电压比较时，抗起霜元件用于将光电二极管两端的电压返回到电源电压。基于低电压比较和高电压比较的结果，使用控制块来确定到防晕元件的输入信号。输入信号可用于将防晕元件驱动到期望的逻辑电平，从而使电荷累积装置两端的电压成为钳位电压。使用抗起霜元件消除了对相邻像素的喷射，而与像素的积分时间无关。

10. 发明授权

US5349695A Selective call receiver having CMOS power-on reset circuit 失效
标题翻译：具有CMOS上电复位电路的选择性呼叫接收机
公开(公告)号：US5349695A
公开(公告)日：1994-09-20
申请号：US984827
申请日：1992-12-03
申请人： Zhong K. Zhong , Barry W. Herold
发明人： Zhong K. Zhong , Barry W. Herold
IPC分类号： H03K17/22 , H04W52/02 , H04W88/02 , H04Q3/02 , H03K17/30
CPC分类号： H03K17/223 , H04W52/028 , H04W88/022
摘要： A selective call receiver (100) operates to recover an information signal and is capable of receiving a battery supplying a first voltage (203) that is multiplied to generate a second voltage (212). The selective call receiver (100) includes [comprises] a processor (106) that extracts message information contained within the recovered information signal for presentation and a power-on reset circuit (112) that generates a power-on reset signal having [comprising] first and second portions corresponding with a processor reset and a processor execute state, respectively. The power-on reset signal changes from the processor reset to the processor execute state when the second voltage (212) exceeds a sum of a PMOS threshold voltage and a NMOS threshold voltage, thereby completing a power-on reset of the processor (106).
摘要翻译：选呼接收机（100）操作以恢复信息信号，并且能够接收提供被乘以以产生第二电压（212）的第一电压（203）的电池。选择呼叫接收机（100）包括[包括]提取包含在所恢复的信息信号中以用于呈现的消息信息的处理器（106）和产生具有[包含]的上电复位信号的上电复位电路（112）分别对应于处理器复位和处理器执行状态的第一和第二部分。当第二电压（212）超过PMOS阈值电压和NMOS阈值电压之和时，上电复位信号从处理器复位变为处理器执行状态，从而完成处理器（106）的上电复位，。

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