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1. 发明授权

US08068573B1 Phase dithered digital communications system 有权
标题翻译：相位抖动数字通信系统
公开(公告)号：US08068573B1
公开(公告)日：2011-11-29
申请号：US11740967
申请日：2007-04-27
申请人： Nadim Khlat , Richard A. Summe , Scott Robert Humphreys , Chris Ngo
发明人： Nadim Khlat , Richard A. Summe , Scott Robert Humphreys , Chris Ngo
IPC分类号： H04L7/00 , H03L7/00
CPC分类号： H03K3/84 , H03K7/04 , H04B15/06
摘要： The present invention is a phase dithered digital communications system that includes a digital receiver, and uses phase dithering to spread the energy of one or more system clocks to minimize receiver de-sensitization. Phase dithering uses a single frequency for each system clock; however, the energy of each system clock is spread over a range of frequencies by changing the duty-cycle of each clock half-cycle. A non-phase dithered clock drives the sampling clock of a receiver analog-to-digital converter to provide accurate correlation with received information, which may allow use of a higher frequency sampling clock than in frequency dithered designs. Phase dithered clocks and non-phase dithered clocks may have constant frequencies that are related to each other by a ratio of two integers; therefore, the time base used for extracting received data is always correlated and accurate.
摘要翻译：本发明是一种相位抖动数字通信系统，其包括数字接收机，并且使用相位抖动来扩展一个或多个系统时钟的能量以最小化接收机去敏感。相位抖动对每个系统时钟使用单个频率; 然而，每个系统时钟的能量通过改变每个时钟半周期的占空比在一个频率范围内扩展。非相抖动时钟驱动接收器模拟 - 数字转换器的采样时钟，以提供与接收信息的精确相关性，这可能允许使用比在频率抖动设计中更高频率的采样时钟。相位抖动时钟和非相位抖动时钟可以具有通过两个整数的比率彼此相关的恒定频率; 因此，用于提取接收到的数据的时基总是相关和准确的。

2. 发明授权

US07412215B1 System and method for transitioning from one PLL feedback source to another 有权
标题翻译：从一个PLL反馈源转换到另一个PLL反馈源的系统和方法
公开(公告)号：US07412215B1
公开(公告)日：2008-08-12
申请号：US11144119
申请日：2005-06-03
申请人： Alexander Wayne Hietala , Jeffery Peter Ortiz , Scott Robert Humphreys
发明人： Alexander Wayne Hietala , Jeffery Peter Ortiz , Scott Robert Humphreys
IPC分类号： H04B1/04
CPC分类号： H04B1/0475 , H03L7/081 , H03L7/087 , H03L7/16 , H03L2207/12
摘要： A system and method are provided for switching from one phase-locked loop feedback source to another in a radio frequency (RF) transmitter. The RF transmitter includes a phase-locked loop (PLL) that provides a phase-modulated RF input signal and power amplifier circuitry that amplifies the RF input signal to provide an RF output signal. The PLL includes switching circuitry that couples a feedback path of the PLL to an output of the PLL for open loop operation and couples the feedback path of the PLL to an output of the power amplifier circuitry for closed loop operation. Prior to switching the feedback path from the output of the PLL to the output of the power amplifier circuitry, time alignment circuitry operates to time-align feedback signals from the outputs of the PLL and the power amplifier circuitry such that switching from open loop operation to closed loop operation causes minimal phase disturbance.
摘要翻译：提供了一种用于在射频（RF）发射机中从一个锁相环反馈源切换到另一个的系统和方法。 RF发射器包括提供相位调制RF输入信号的锁相环（PLL）和放大RF输入信号以提供RF输出信号的功率放大器电路。 PLL包括将PLL的反馈路径耦合到PLL的输出以用于开环操作的开关电路，并将PLL的反馈路径耦合到用于闭环操作的功率放大器电路的输出。在将反馈路径从PLL的输出切换到功率放大器电路的输出之前，时间对准电路用于对来自PLL和功率放大器电路的输出的反馈信号进行时间对准，使得从开环操作切换到闭环运行导致最小的相位扰动。

3. 发明授权

US07288999B1 Pre-distortion system for a synthesizer having modulation applied in the reference path 有权
标题翻译：具有在参考路径中应用的调制的合成器的预失真系统
公开(公告)号：US07288999B1
公开(公告)日：2007-10-30
申请号：US11347956
申请日：2006-02-06
申请人： Alexander Wayne Hietala , Ryan Lee Bunch , Scott Robert Humphreys , Barry Travis Hunt, Jr.
发明人： Alexander Wayne Hietala , Ryan Lee Bunch , Scott Robert Humphreys , Barry Travis Hunt, Jr.
IPC分类号： H03L7/197 , H04L25/49
CPC分类号： H03L7/1976 , H03C3/0966 , H03L7/23 , H03L2207/12
摘要： A system providing a phase or frequency modulated signal is provided. In general, the system includes a phase locked loop (PLL) having a fractional-N divider in a reference path of the PLL operating to divide a reference frequency based on a pre-distorted modulation signal. Pre-distortion circuitry operates to provide the pre-distorted modulation signal by pre-distorting a modulation signal such that a convolution, or cascade, of the pre-distortion and a transfer function of the PLL results in a substantially flat frequency response for a range of modulation rates greater than a bandwidth of the PLL.
摘要翻译：提供了提供相位或频率调制信号的系统。通常，该系统包括在PLL的参考路径中具有分数N分频器的锁相环（PLL），其操作以基于预失真调制信号来划分参考频率。预失真电路通过对调制信号进行预失真来提供预失真调制信号，使得预失真和PLL的传递函数的卷积或级联导致范围内的基本平坦的频率响应的调制率大于PLL的带宽。

4. 发明授权

US06731145B1 Phase-locked loop having loop gain and frequency response calibration 有权
标题翻译：锁相环具有环路增益和频率响应校准
公开(公告)号：US06731145B1
公开(公告)日：2004-05-04
申请号：US10409291
申请日：2003-04-08
申请人： Scott Robert Humphreys , Barry Travis Hunt, Jr.
发明人： Scott Robert Humphreys , Barry Travis Hunt, Jr.
IPC分类号： H03L706
CPC分类号： H03L7/18 , H03L7/1075
摘要： The invention provides an apparatus and method for calibrating both the pole/zero locations and the gain of a charge pump phase-locked loop's (PLL's) frequency response with one calibration operation. In one embodiment, the calibration is performed using a bandgap voltage reference and a stable frequency reference in order to measure a slew rate (I/C), defined as a current-to-capacitance ratio, and then adjusting the RC time constant (tRC) by adjusting the capacitance value. The adjustment setting is used in the loop filter capacitors, thereby calibrating the pole and zero locations of the PLL, which depend on the RC product. The charge pump reference current is proportional to the ratio of the bandgap voltage to the resistor value. When the capacitance is adjusted, the slew rate is calibrated as well, wherein the slew rate represents a portion of the loop gain of the PLL.
摘要翻译：本发明提供一种用于通过一次校准操作来校准电极/锁相环（PLL）频率响应的极点/零点位置和增益的装置和方法。在一个实施例中，使用带隙电压参考和稳定频率参考来执行校准，以便测量被定义为电流 - 电容比的转换速率（I / C），然后调整RC时间常数（tRC ）通过调整电容值。调节设置用于环路滤波电容器，从而校准PLL的极点和零点位置，这取决于RC产品。电荷泵参考电流与带隙电压与电阻值的比例成正比。当调整电容时，压摆率也被校准，其中转换速率表示PLL的环路增益的一部分。

5. 发明授权

US06710664B2 Coarse tuning for fractional-N synthesizers 有权
$Coarse tuning for fractional-N synthesizers$
标题翻译：分数N合成器的粗调
公开(公告)号：US06710664B2
公开(公告)日：2004-03-23
申请号：US10127289
申请日：2002-04-22
申请人： Scott Robert Humphreys , Ralph Christopher Nieri
发明人： Scott Robert Humphreys , Ralph Christopher Nieri
IPC分类号： H03L700
CPC分类号： H03L7/113 , H03L7/087 , H03L7/10 , H03L7/1974 , H03L7/1976
摘要： The present invention provides an efficient coarse tuning process for fractional-N synthesizers. In general, a divided reference signal and a divided controllable oscillator (CO) signal from the phase lock loop (PLL) of a synthesizer are each further divided by a common factor M to provide an average reference signal and an average CO signal, respectively. Averaging the divided CO signal reduces jitter caused by fractional-N division of the CO signal. The frequencies of the average CO signal and the average reference signal are compared and the result is used to select an appropriate tuning curve for operating the CO.
摘要翻译：本发明为分数N合成器提供了有效的粗调程序。通常，来自合成器的锁相环（PLL）的分频参考信号和分频可控振荡器（CO）信号分别被公共因子M除以分别提供平均参考信号和平均CO信号。分割的CO信号平均减少由CO信号的分数N除法引起的抖动。比较平均CO信号和平均参考信号的频率，结果用于选择用于操作CO的适当调谐曲线。

6. 发明授权

US06370365B1 Selective call radio having an integrated frequency conversion circuit 有权
标题翻译：具有集成频率转换电路的选择性呼叫无线电
公开(公告)号：US06370365B1
公开(公告)日：2002-04-09
申请号：US09205312
申请日：1998-12-04
申请人： Edgar Herbert Callaway, Jr. , Scott Robert Humphreys , Keith Edward Jackoski
发明人： Edgar Herbert Callaway, Jr. , Scott Robert Humphreys , Keith Edward Jackoski
IPC分类号： H04B104
CPC分类号： H03D7/161 , H04B1/28
摘要： A selective call radio (300) includes receiver (200). The receiver in turn includes an antenna (202) for receiving a radio signal having a first operating frequency, an amplifier(204) coupled thereto for generating an amplified signal; and a frequency translation circuit (208). The frequency translation circuit includes a selectivity filter (212) and an integrated frequency conversion circuit (216). The selectivity is coupled to the amplified signal for generating a filtered signal. The integrated frequency conversion circuit is coupled to the filtered signal and is incorporated into at least one IC (integrated circuit). The integrated frequency conversion circuit includes an oscillator (220), a divider (224), and a mixer (218). A first input of the mixer is coupled to the filtered signal generated by the selectivity filter. The divider is coupled to the oscillator and its output is coupled to a second input of the mixer. The mixer generates an output signal having a second operating frequency, the second operating frequency having a frequency value different from the frequency value of the first operating frequency of the radio signal.
摘要翻译：选呼通话（300）包括接收机（200）。接收机又包括用于接收具有第一工作频率的无线电信号的天线（202），与其耦合的放大器（204），用于产生放大信号; 和频率转换电路（208）。频率转换电路包括选择性滤波器（212）和集成频率转换电路（216）。选择性耦合到放大的信号以产生滤波信号。集成频率转换电路耦合到滤波后的信号，并被并入到至少一个IC（集成电路）中。集成频率转换电路包括振荡器（220），分频器（224）和混频器（218）。混频器的第一输入端耦合到由选择滤波器产生的滤波信号。分频器耦合到振荡器，其输出耦合到混频器的第二输入端。混频器产生具有第二工作频率的输出信号，第二工作频率具有与无线电信号的第一工作频率的频率值不同的频率值。

7. 发明授权

US06211583B1 High speed current switch 有权
标题翻译：高速电流开关
公开(公告)号：US06211583B1
公开(公告)日：2001-04-03
申请号：US09395267
申请日：1999-09-13
申请人： Scott Robert Humphreys
发明人： Scott Robert Humphreys
IPC分类号： H03M166
CPC分类号： H03K17/04106 , H03K17/162 , Y10T307/865
摘要： A high-speed current switch (36) comprises a differential switch (14), a current source (12), an op-amp (32), a feedback switch (38), a hold capacitor (40), a biasing transistor (42), and a second current switch (44). The high-speed current switch (36) receives a complementary control signal (46) and a control signal (48), and generates an output current (26).
摘要翻译：高速电流开关（36）包括差分开关（14），电流源（12），运算放大器（32），反馈开关（38），保持电容器（40），偏置晶体管 42）和第二电流开关（44）。高速电流开关（36）接收互补控制信号（46）和控制信号（48），并产生输出电流（26）。

8. 发明授权

US5805095A Two's complement digital to analog converter 失效
标题翻译：二进制补码数模转换器
公开(公告)号：US5805095A
公开(公告)日：1998-09-08
申请号：US781252
申请日：1997-01-10
申请人： Scott Robert Humphreys , Raymond Louis Barrett, Jr. , Lawrence Loren Case
发明人： Scott Robert Humphreys , Raymond Louis Barrett, Jr. , Lawrence Loren Case
IPC分类号： H03M1/66
CPC分类号： H03M1/66
摘要： A two's complement digital to analog converter (300) is for converting a two's complement binary value to an analog output current, and includes a control circuit (310) which generates controlled value bits, a digital to analog current converter (DACC) (320), and an augmenter (330). The DACC (320) generates a DACC analog current which is a portion of the analog output current and which has an absolute value which is related to the binary value of the controlled value bits. The augmenter (330), which is coupled to a most significant bit of the two's complement binary value, generates a portion of the analog output current by modifying the absolute value of the DACC analog current by a least significant bit current increment when the most significant bit indicates a negative value of the two's complement binary value.
摘要翻译：二进制补码数模转换器（300）用于将二进制补码二进制值转换为模拟输出电流，并且包括产生受控值位的控制电路（310），数模转换器（DACC）（320），以及增强器（330）。 DACC（320）产生作为模拟输出电流的一部分的DACC模拟电流，其具有与控制值位的二进制值相关的绝对值。耦合到二进制补码二进制值的最高有效位的增益器（330）通过在最高有效位电流增量时修改DACC模拟电流的绝对值来产生模拟输出电流的一部分位表示二进制补码二进制值的负值。

9. 发明授权

US08857983B2 Ophthalmic lens assembly having an integrated antenna structure 有权
标题翻译：具有集成天线结构的眼科镜组件
公开(公告)号：US08857983B2
公开(公告)日：2014-10-14
申请号：US13358579
申请日：2012-01-26
申请人： Randall Braxton Pugh , Daniel B. Otts , Frederick A. Flitsch , Adam Toner , Scott Robert Humphreys
发明人： Randall Braxton Pugh , Daniel B. Otts , Frederick A. Flitsch , Adam Toner , Scott Robert Humphreys
IPC分类号： G02C7/08 , G02C7/04
CPC分类号： G02C7/049 , A61F2/1624 , A61F2250/0001 , A61F2250/0002 , B29D11/00038 , B29D11/00817 , G02C7/04 , G02C7/083 , H01Q1/22 , H01Q1/2225 , H01Q7/00
摘要： Antennas and antenna systems may be designed and configured for incorporation into mechanical devices, including medical devices, such as ophthalmic devices, including contact lenses. These antennas and antenna systems may be utilized to transmit data from the mechanical device to a receiver, to receive data from a transmitter, and/or to inductively charge an electromechanical cell or the like incorporated into the mechanical device.
摘要翻译：天线和天线系统可以被设计和配置成并入到机械装置中，包括医疗装置，诸如眼科装置，包括隐形眼镜。这些天线和天线系统可用于将数据从机械设备传送到接收机，从发射机接收数据，和/或感应地对组装在机械设备中的机电电池等进行充电。

10. 发明申请

US20130343248A1 WIRELESS COMMUNICATION PROTOCOL FOR LOW POWER RECEIVERS 有权
标题翻译：低功率接收机的无线通信协议
公开(公告)号：US20130343248A1
公开(公告)日：2013-12-26
申请号：US13531874
申请日：2012-06-25
申请人： Adam Toner , Scott Robert Humphreys , Randall Braxton Pugh , Daniel B. Otts , William Chester Neeley
发明人： Adam Toner , Scott Robert Humphreys , Randall Braxton Pugh , Daniel B. Otts , William Chester Neeley
IPC分类号： H04W52/02
CPC分类号： H04W56/0085 , Y02D70/00 , Y02D70/26
摘要： A wireless protocol for a communication system is set forth herein which may be utilized for communication between a transmitter and a receiver over any type of communication channel. The wireless communication protocol provides for the reduction of receiver active or on time which in turn lowers power consumption. The wireless communication protocol enables the complexity and receiver size to be reduced. The methodology employed in the protocol utilizes a unique message frame in conjunction with repeated transmission and periodic receiver searching.
摘要翻译：本文阐述了用于通信系统的无线协议，其可以用于任何类型的通信信道上的发射机和接收机之间的通信。无线通信协议提供减少接收器的有效或准时，从而降低功耗。无线通信协议使复杂度和接收机尺寸得以减小。在协议中使用的方法利用独特的消息帧结合重复的传输和周期性的接收机搜索。

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