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1. 发明授权

US5640681A Boot-strapped cascode current mirror 失效
标题翻译：引导带状共源共栅电流镜
公开(公告)号：US5640681A
公开(公告)日：1997-06-17
申请号：US149886
申请日：1993-11-10
申请人： Raymond Louis Barrett, Jr. , Barry Wayne Herold , Grazyna A. Pajunen
发明人： Raymond Louis Barrett, Jr. , Barry Wayne Herold , Grazyna A. Pajunen
IPC分类号： G05F3/26 , H04B7/00 , G05F3/16
CPC分类号： G05F3/262
摘要： A cascode current mirror circuit includes a cascode connected input stage (401) that operates to conduct an input current (400) in response to an input voltage of an input signal coupled to an effective transconductance of the cascode connected input stage (401). An input mirroring transistor (404) operates to control a mirror reference current (406) in response to the input voltage of the input signal. A diode connected transistor (409) coupled to a second control node of the cascode connected input stage (410) generates a control bias proportional to the mirror reference current (406) and to the input signal. A cascode connected output stage (411) has a first control node (413) coupled to the input signal and a second control node (414) coupled to the diode connected transistor (409) and the second control node (410) of the cascode connected input stage (401) for establishing an output current (415) that is substantially equivalent to the input current (400).
摘要翻译：共源共栅电流镜电路包括共源共栅连接的输入级（401），其操作以响应耦合到共源共栅连接的输入级（401）的有效跨导的输入信号的输入电压来传导输入电流（400）。输入镜像晶体管（404）用于响应于输入信号的输入电压来控制镜参考电流（406）。耦合到共源共栅连接的输入级（410）的第二控制节点的二极管连接晶体管（409）产生与镜参考电流（406）成比例的控制偏置和输入信号。级联连接的输出级（411）具有耦合到输入信号的第一控制节点（413）和耦合到二极管连接的晶体管（409）的第二控制节点（414）和连接的共源共栅的第二控制节点（410）输入级（401），用于建立基本上等于输入电流（400）的输出电流（415）。

2. 发明授权

US5880619A Low power precision voltage splitter 失效
标题翻译：低功率精密分压器
公开(公告)号：US5880619A
公开(公告)日：1999-03-09
申请号：US990548
申请日：1997-12-15
申请人： Raymond Louis Barrett, Jr. , Barry W. Herold , Grazyna A. Pajunen
发明人： Raymond Louis Barrett, Jr. , Barry W. Herold , Grazyna A. Pajunen
IPC分类号： G05F3/24 , G05F1/10 , G05F3/316
CPC分类号： G05F3/247
摘要： A voltage splitter circuit (100) that generates a one-half supply voltage includes a first switched operational transconductance amplifier (switched OTA) (120), a first transistor switch (110) that is controlled by a first clock signal (108) to periodically switch a first supply voltage (135) to a non-inverting input (118) of the first switched OTA, a second switched OTA (115), a second transistor switch (105) that is controlled by an inverted second clock signal (104) to periodically switch a second supply voltage (130) to a non-inverting input (114) of the second switched OTA, a commutating capacitor (112) coupled between the non-inverting input of the first switched OTA and the non-inverting input of the second switched OTA, a first filter capacitor (145) coupled to an output (121) of the first switched OTA, a second filter capacitor (140) coupled to an output (116) of the second switched OTA, and a third switched OTA (125). The first and second clock signals are non-overlapping.
摘要翻译：产生二分之一电源电压的分压器电路（100）包括第一开关操作跨导放大器（开关OTA）（120），由第一时钟信号（108）控制的第一晶体管开关（110）将第一电源电压（135）切换到第一开关OTA的非反相输入端（118），第二开关OTA（115），由反相第二时钟信号（104）控制的第二晶体管开关（105）周期性地将第二电源电压（130）切换到第二开关OTA的非反相输入端（114）;耦合在第一开关OTA的非反相输入端和第一开关OTA的非反相输入端之间的整流电容器（112）第二开关OTA，耦合到第一开关OTA的输出（121）的第一滤波电容器（145），耦合到第二开关OTA的输出端（116）的第二滤波电容器（140）和第三开关OTA （125）。第一和第二时钟信号是不重叠的。

3. 发明授权

US5825213A Method and apparatus for frequency synthesis 失效
标题翻译：用于频率合成的方法和装置
公开(公告)号：US5825213A
公开(公告)日：1998-10-20
申请号：US766953
申请日：1996-12-16
申请人： Raymond Louis Barrett, Jr. , Barry Herold , Grazyna A. Pajunen
发明人： Raymond Louis Barrett, Jr. , Barry Herold , Grazyna A. Pajunen
IPC分类号： H03L7/183 , H03L7/18
CPC分类号： H03L7/183
摘要： A method and apparatus for frequency synthesis replaces a conventional divide-by-N counter with a low-power binary ripple counter (108). The method and apparatus employs a difference comparison scheme (114) that provides arbitrarily precise channel spacing, and allows loop sample rate to be selected independent of channel spacing.
摘要翻译：一种用于频率合成的方法和装置用一个低功率二进制纹波计数器（108）代替常规的除N计数器。该方法和装置采用提供任意精确的信道间隔的差分比较方案（114），并且允许独立于信道间隔选择环路采样率。

4. 发明授权

US5770980A Fast starting oscillator 失效
标题翻译：快速启动振荡器
公开(公告)号：US5770980A
公开(公告)日：1998-06-23
申请号：US773244
申请日：1996-12-23
申请人： Raymond Louis Barrett, Jr. , John Wayne Simmons , Barry Herold , Grazyna A. Pajunen
发明人： Raymond Louis Barrett, Jr. , John Wayne Simmons , Barry Herold , Grazyna A. Pajunen
IPC分类号： H03B1/00 , H03B5/36 , H03B5/06
CPC分类号： H03B5/368 , H03B2200/0008 , H03B2200/0026 , H03B2200/0034 , H03B2200/0038 , H03B2200/0058 , H03B2200/0062 , H03B2200/0082 , H03B2200/0094 , H03B2201/0208 , H03B5/364
摘要： A low power, fast starting oscillator (10) of the Colpitts type includes an amplifier (12) that provides voltage gain and feeds a source follower circuit (14) that provides a desirable output impedance. A crystal (16) is coupled from an output of the source follower circuit (14) back to the amplifier's input (32). The voltage gain of the amplifier (12) and the output impedance of the source follower circuit (14) are independently selectable to provide an optimum transconductance for the oscillator (10) to start quickly. When oscillations reach a threshold value, the transconductance may be reduced to save power.
摘要翻译： Colpitts型的低功率，快速启动振荡器（10）包括提供电压增益的放大器（12）并且馈送提供期望的输出阻抗的源极跟随器电路（14）。晶体（16）从源极跟随器电路（14）的输出耦合回到放大器的输入端（32）。放大器（12）的电压增益和源极跟随器电路（14）的输出阻抗是可独立选择的，以提供振荡器（10）快速启动的最佳跨导。当振荡达到阈值时，跨导可以减少以节省功率。

5. 发明授权

US5552750A Method and apparatus for determining an instantaneous phase difference between two signals 失效
标题翻译：用于确定两个信号之间的瞬时相位差的方法和装置
公开(公告)号：US5552750A
公开(公告)日：1996-09-03
申请号：US523665
申请日：1995-09-05
申请人： Raymond L. Barrett, Jr. , Barry W. Herold , Grazyna A. Pajunen
发明人： Raymond L. Barrett, Jr. , Barry W. Herold , Grazyna A. Pajunen
IPC分类号： H03D13/00 , H03L7/091 , H03L7/183 , H03L7/18
CPC分类号： H03L7/183 , H03D13/001 , H03L7/091
摘要： A method and apparatus determine an instantaneous phase difference (207) between a reference signal (103) and a controlled signal (120). The reference signal (103) is derived by frequency dividing a first signal by a counter (106) including an output (107) having K sequential states, wherein K is an integer value equal to the frequency of the first signal (103) divided by the frequency of the desired reference signal, and wherein the output (107) changes by no more than one bit between any adjacent states of the K sequential states. The output (107) of the counter (106) is recorded (206) at a time concurrent with a first predetermined event occurring in the controlled signal (120), thereby generating a recorded count value that is free from metastability induced errors. The recorded count value is decoded (208) to produce a sequential state number S.sub.E corresponding to the first predetermined event. The instantaneous phase difference (207) is then calculated (210) from S.sub.E, K, and other predetermined constants.
摘要翻译：方法和装置确定参考信号（103）和受控信号（120）之间的瞬时相位差（207）。参考信号（103）是通过用包括具有K个顺序状态的输出（107）的计数器（106）对第一信号进行分频而导出的，其中K是等于第一信号（103）的频率的整数值除以所述参考信号的频率，并且其中所述输出（107）在所述K个顺序状态的任何相邻状态之间改变不超过一个比特。与受控信号（120）中发生的第一预定事件同时记录（206）计数器（106）的输出（107），从而生成没有亚稳引起的误差的记录计数值。记录的计数值被解码（208）以产生对应于第一预定事件的顺序状态号码SE。然后从SE，K和其他预定常数计算（210）瞬时相位差（207）。

6. 发明授权

US5612614A Current mirror and self-starting reference current generator 失效
标题翻译：电流镜和自启动参考电流发生器
公开(公告)号：US5612614A
公开(公告)日：1997-03-18
申请号：US539388
申请日：1995-10-05
申请人： Raymond L. Barrett, Jr. , Barry Herold , Grazyna A. Pajunen
发明人： Raymond L. Barrett, Jr. , Barry Herold , Grazyna A. Pajunen
IPC分类号： G05F3/26 , G05F3/16
CPC分类号： G05F3/262
摘要： A current mirror (100) has an input stage (104) and an output stage (106), both preferably employing FET's. (Field Effect Transistors) An amplifier (102) equalizes drain-to-source voltages between FET's in the input and output stages to provide a higher output impedance. A resistance (R1), coupled in series with an FET in the output stage (106), provides degenerative feedback. A reference current generator (400) is constructed of two such current mirrors, one being the compliment of the other, to provide one or more stable reference currents. Loop gain of the reference current generator (400) is greater than one at start-up, but degenerative feedback reduces the loop gain to one at a predetermined stable operating point.
摘要翻译：电流镜（100）具有输入级（104）和输出级（106），均优选采用FET。（场效应晶体管）放大器（102）使输入和输出级之间的FET的漏极 - 源极电压相等，以提供更高的输出阻抗。与输出级（106）中的FET串联耦合的电阻（R1）提供退化反馈。参考电流发生器（400）由两个这样的电流镜构成，一个是另一个的补偿，以提供一个或多个稳定的参考电流。参考电流发生器（400）的环路增益在启动时大于1，但退化反馈将环路增益在预定的稳定工作点降低到一个。

7. 发明授权

US5576664A Discrete time digital phase locked loop 失效
标题翻译：离散时间数字锁相环
公开(公告)号：US5576664A
公开(公告)日：1996-11-19
申请号：US556882
申请日：1995-11-02
申请人： Barry W. Herold , Scott R. Humphreys , Phillip Johnson , Raymond L. Barrett, Jr. , Grazyna A. Pajunen
发明人： Barry W. Herold , Scott R. Humphreys , Phillip Johnson , Raymond L. Barrett, Jr. , Grazyna A. Pajunen
IPC分类号： H03L7/091 , H03L7/093 , H03L7/181
CPC分类号： H03L7/091 , H03L7/093 , H03L7/181
摘要： A communication receiver (100) employs a discrete time digital phase locked loop (142) for maintaining a generated signal (144) locked to a reference signal (136). The discrete time digital phase locked loop (142) includes a phase detector (202), an accumulator (219), an adder (227), and a controlled oscillator (232). The accumulator (219) is connected to the phase detector (202) and a reference signal (136) for calculating an accumulator output value equal to a first sum of a current sample generated by the phase detector (202), and all of the plurality of discrete phase error samples produced prior to the current sample. The adder (227) is connected to the phase detector (202) and the accumulator (219) for forming a second sum of the current sample and the accumulator output value. The controlled oscillator (232) receives the second sum, which is utilized for controlling the controlled oscillator (232).
摘要翻译：通信接收器（100）采用离散时间数字锁相环（142）来保持锁定到参考信号（136）的生成信号（144）。离散时间数字锁相环（142）包括相位检测器（202），累加器（219），加法器（227）和受控振荡器（232）。累加器（219）连接到相位检测器（202）和参考信号（136），用于计算等于由相位检测器（202）生成的当前采样的第一和的累加器输出值，并且所有多个在当前样本之前产生的离散相位误差样本。加法器（227）连接到相位检测器（202）和累加器（219），用于形成当前采样和累加器输出值的第二和。受控振荡器（232）接收用于控制受控振荡器（232）的第二和。

8. 发明授权

US5630222A Method and apparatus for generating multiple signals at multiple frequencies 失效
标题翻译：用于在多个频率上产生多个信号的方法和装置
公开(公告)号：US5630222A
公开(公告)日：1997-05-13
申请号：US566518
申请日：1995-12-04
申请人： Raymond L. Barrett, Jr. , Barry W. Herold , Grazyna A. Pajunen
发明人： Raymond L. Barrett, Jr. , Barry W. Herold , Grazyna A. Pajunen
IPC分类号： H03L7/181 , H03L7/23 , H04B1/14
CPC分类号： H03L7/181 , H03L7/23
摘要： A frequency synthesizer (100) is used for generating a plurality of signals operating at a plurality of frequencies that are integer multiples of a reference frequency. The frequency synthesizer (100) includes a plurality of phase lock loops coupled to a single phase error detector. The phase error detector (103) is connected to a reference signal (104), a first generated signal (116) and a sampler signal (136) derived from a second generated signal (132). The phase error detector (103) includes a shared counter (118), and first and second registers (106, 122) connected to the output of the shared counter (118). First and second phase lock loops (101, 105) are used for phase locking to the reference signal (104). The first and second phase lock loops (101, 105) derive phase error signals from the first and second registers (106, 122), thereby adjusting the first and second generated signals (116, 132).
摘要翻译：频率合成器（100）用于产生以参考频率的整数倍的多个频率工作的多个信号。频率合成器（100）包括耦合到单相误差检测器的多个锁相环。相位误差检测器（103）连接到从第二生成信号（132）导出的参考信号（104），第一生成信号（116）和取样器信号（136）。相位误差检测器（103）包括共享计数器（118）以及连接到共享计数器（118）的输出的第一和第二寄存器（106,122）。第一和第二锁相环（101,105）用于相位锁定到参考信号（104）。第一和第二锁相环（101,105）从第一和第二寄存器（106,122）导出相位误差信号，从而调整第一和第二产生信号（116,132）。

9. 发明授权

US5412336A Self-biasing boot-strapped cascode amplifier 失效
标题翻译：自偏置引导式共源共栅放大器
公开(公告)号：US5412336A
公开(公告)日：1995-05-02
申请号：US150660
申请日：1993-11-10
申请人： Raymond L. Barrett, Jr. , Barry W. Herold , Grazyna A. Pajunen
发明人： Raymond L. Barrett, Jr. , Barry W. Herold , Grazyna A. Pajunen
IPC分类号： H03F1/22 , H03F3/68
CPC分类号： H03F1/223
摘要： A cascode amplifier circuit including an input mirroring transistor (401) that generates a first output current (403) in response to the input signal. A diode connected transistor (404) generates a control bias proportional to the first output current. A cascode connected transistor output stage (405) includes a common source transistor (406) coupled to the input signal and the input mirroring transistor (401) for establishing an output current (407) in the cascode connected transistor output stage. A common gate transistor (408) is coupled to the diode connected transistor (404) and the common source transistor (406) for isolating the common source transistor (406) from any change in an output voltage present at an output terminal (409) of the common gate transistor (408) while operating to control the output currently(407) in response to the control bias.
摘要翻译：一种级联放大器电路，包括响应于输入信号产生第一输出电流（403）的输入镜像晶体管（401）。二极管连接的晶体管（404）产生与第一输出电流成比例的控制偏置。共源共栅连接的晶体管输出级（405）包括耦合到输入信号的公共源晶体管（406）和用于在共源共栅连接的晶体管输出级中建立输出电流（407）的输入镜像晶体管（401）。公共栅极晶体管（408）耦合到二极管连接的晶体管（404）和公共源极晶体管（406），用于将公共源极晶体管（406）与存在于输出端子（409）处的输出电压的任何变化隔离公共栅极晶体管（408）在操作时响应于控制偏压来控制当前的输出（407）。

10. 发明授权

US5373249A Complementary cascode push-pull amplifier 失效
标题翻译：互补共源共栅放大器
公开(公告)号：US5373249A
公开(公告)日：1994-12-13
申请号：US150930
申请日：1993-11-10
申请人： Raymond L. Barrett, Jr. , Barry W. Herold , Grazyna A. Pajunen
发明人： Raymond L. Barrett, Jr. , Barry W. Herold , Grazyna A. Pajunen
IPC分类号： H03F3/30 , H03F3/26 , H03F3/16
CPC分类号： H03F3/3001
摘要： A complementary cascode push-pull amplifier circuit includes a bias generator, a complementary bias generator, a cascode input stage (416, 417), a cascode output stage (410, 411), a complementary cascode input stage (456,457), and a complementary cascode output stage (450,451). The bias generator is responsive to a first input signal (420) and generates a bias control voltage. The complementary bias generator is responsive to a second input (421) and generates a complementary bias control voltage. The cascode output stage (410, 411) and the complementary cascode output stage (450,451) each have an output coupled to a common output terminal (510) for generating a portion of an output current signal in response to the respective input signals (420, 421) and in response to the bias control voltage and the complementary bias control voltage being generated.
摘要翻译：互补共源共栅放大器电路包括偏置发生器，互补偏置发生器，共源共栅输入级（416,417），共源共栅输出级（410,411），互补共源共栅输入级（456,457）和互补共源共栅输出级（450,451）。偏置发生器响应于第一输入信号（420）并产生偏置控制电压。互补偏置发生器响应于第二输入（421）并产生互补偏置控制电压。级联输出级（410,411）和互补共源共栅输出级（450,451）各自具有耦合到公共输出端（510）的输出，用于响应于相应的输入信号（420,411）产生输出电流信号的一部分，并且响应于所产生的偏置控制电压和互补偏置控制电压。

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