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1. 发明授权

US5675759A Method and apparatus for register management using issue sequence prior physical register and register association validity information 失效
标题翻译：使用问题序列以前的物理寄存器和寄存器关联有效性信息的寄存器管理方法和装置
公开(公告)号：US5675759A
公开(公告)日：1997-10-07
申请号：US522567
申请日：1995-09-01
申请人： Michael C. Shebanow , Gene W. Shen , Ravi Swami , Niteen A. Patkar
发明人： Michael C. Shebanow , Gene W. Shen , Ravi Swami , Niteen A. Patkar
IPC分类号： G06F9/38
CPC分类号： G06F9/384 , G06F9/3855 , G06F9/3857 , G06F9/3863
摘要： In a microprocessor, an apparatus is included for coordinating the use of physical registers in the microprocessor. Upon receiving an instruction, the coordination apparatus extracts source and destination logical registers from the instruction. For the destination logical register, the apparatus assigns a physical address to correspond to the logical register. In so doing, the apparatus stores the former relationship between the logical register and another physical register. Storing this former relationship allows the apparatus to backstep to a particular instruction when an execution exception is encountered. Also, the apparatus checks the instruction to determine whether it is a speculative branch instruction. If so, then the apparatus creates a checkpoint by storing selected state information. This checkpoint provides a reference point to which the processor may later backup if it is determined that a speculated branch was incorrectly predicted. Overall, the apparatus coordinates the use of physical registers in the processor in such a way that: (1) logical/physical register relationships are easily changeable; and (2) backup and backstep procedures are accommodated.
摘要翻译：在微处理器中，包括用于协调微处理器中物理寄存器的使用的装置。在接收到指令之后，协调装置从指令中提取源和目的地逻辑寄存器。对于目的地逻辑寄存器，设备分配一个物理地址以对应于逻辑寄存器。在这样做时，该装置存储逻辑寄存器与另一物理寄存器之间的之前的关系。存储这种以前的关系允许设备在遇到执行异常时后退到特定的指令。此外，该装置检查指令以确定它是否是推测性分支指令。如果是这样，则设备通过存储所选择的状态信息来创建检查点。如果确定推测的分支被错误地预测，该检查点将提供处理器稍后备份的参考点。总的来说，该装置协调处理器中物理寄存器的使用，使得：（1）逻辑/物理寄存器关系容易改变; 和（2）备份和后台程序。

2. 发明授权

US5644742A Processor structure and method for a time-out checkpoint 失效
标题翻译：用于超时检查点的处理器结构和方法
公开(公告)号：US5644742A
公开(公告)日：1997-07-01
申请号：US473223
申请日：1995-06-07
申请人： Gene W. Shen , John Szeto , Niteen A. Patkar , Michael C. Shebanow
发明人： Gene W. Shen , John Szeto , Niteen A. Patkar , Michael C. Shebanow
IPC分类号： G06F9/312 , G06F9/38 , G06F11/14 , G06F11/00
CPC分类号： G06F9/3004 , G06F11/1407 , G06F9/30043 , G06F9/3834 , G06F9/3836 , G06F9/384 , G06F9/3842 , G06F9/3855 , G06F9/3857 , G06F9/3863 , G06F9/3865
摘要： Time-out checkpoints are formed based on a predetermined time-out condition or interval since the last checkpoint was formed rather than forming a checkpoint to store current processor state based merely on decoded Instruction attributes. Such time-out conditions may include the number of instructions issued or the number of clock cycles elapsed, for example. Time-out checkpointing limits the maximum number of instructions within a checkpoint boundary and bounds the time period for recovery from an exception condition. The processor can restore time-out based checkpointed state faster than an instruction decode based checkpoint technique in the event of an exception so long as the instruction window size is greater than the maximum number of instructions within a checkpoint boundary, end such method eliminates processor state restoration dependency on instruction window size. Time-out checkpoints may be implemented with conventional checkpoints, or in a novel logical and physical register rename map checkpointing technique. Timeout checkpoint formation may be used with conventional processor backup techniques as well as with a novel backtracking technique including processor backup and backstepping.
摘要翻译：基于预定的超时条件或时间间隔形成超时检查点，因为上次检查点形成而不是形成一个检查点，以仅仅基于解码的指令属性来存储当前的处理器状态。例如，这种超时条件可以包括发出的指令的数量或经过的时钟周期的数量。超时检查点限制检查点边界内的最大指令数，并限制从异常情况恢复的时间段。只要指令窗口大小大于检查点边界内的最大指令数，处理器就可以比基于指令解码的检查点技术更快地恢复超时的检查点状态，结束这种方法消除处理器状态恢复依赖于指令窗口大小。超时检查点可以用常规检查点或新颖的逻辑和物理寄存器重命名映射检查点技术来实现。超时检查点的形成可以与常规的处理器备份技术一起使用，还可以使用包括处理器备份和后台步骤的新型回溯技术。

3. 发明授权

US07263642B1 Testing replicated sub-systems in a yield-enhancing chip-test environment using on-chip compare to expected results for parallel scan chains testing critical and repairable sections of each sub-system 有权
标题翻译：使用片上比较的产量增强芯片测试环境中的复制子系统与平行扫描链的预期结果进行测试，以测试每个子系统的关键和可修复部分
公开(公告)号：US07263642B1
公开(公告)日：2007-08-28
申请号：US11162595
申请日：2005-09-15
申请人： Samy R. Makar , Niteen A. Patkar
发明人： Samy R. Makar , Niteen A. Patkar
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G01R31/318566
摘要： A multi-processor chip has several processor cores that are simultaneously tested in parallel. The processor cores each have identical scan chains that produce identical test results absent defects. Expected test data is scanned from an external tester onto the chip and replicated to each processor core's scan chain. The expected test data is compared to scan chain outputs at each processor core. Any mismatches set a test-fail bit for that processor core. Each processor core has repairable scan chains and a separate critical scan chain. Failures in the critical scan chain in any processor core cause the whole chip to fail. Processor cores are disabled that have failures in their repairable scan chains, allowing the chip to be repairable by using the remaining processor cores. Critical scan chains include logic that drives to other blocks on the chip, while repairable scan chains have logic embedded deep within a processor core.
摘要翻译：多处理器芯片具有并行测试的多个处理器内核。处理器核心各具有相同的扫描链，产生没有缺陷的相同测试结果。将预期的测试数据从外部测试仪扫描到芯片上并复制到每个处理器核心的扫描链。将预期的测试数据与每个处理器核心处的扫描链输出进行比较。任何不匹配都会为该处理器核心设置测试失败位。每个处理器核心都具有可修复的扫描链和单独的关键扫描链。任何处理器核心中的关键扫描链中的故障都会导致整个芯片发生故障。处理器内核被禁用，其可修复的扫描链中有故障，从而允许使用剩余的处理器内核来修复芯片。关键的扫描链包括驱动芯片上其他块的逻辑，而可修复的扫描链具有深入处理器内核的逻辑。

4. 发明授权

US5751985A Processor structure and method for tracking instruction status to maintain precise state 失效
标题翻译：用于跟踪指令状态以保持精确状态的处理器结构和方法
公开(公告)号：US5751985A
公开(公告)日：1998-05-12
申请号：US487801
申请日：1995-06-07
申请人： Gene W. Shen , John Szeto , Niteen A. Patkar , Michael C. Shebanow
发明人： Gene W. Shen , John Szeto , Niteen A. Patkar , Michael C. Shebanow
IPC分类号： G06F9/312 , G06F9/38 , G06F11/14 , G06F9/30
CPC分类号： G06F9/3004 , G06F11/1407 , G06F9/30043 , G06F9/3834 , G06F9/3836 , G06F9/384 , G06F9/3842 , G06F9/3855 , G06F9/3857 , G06F9/3863 , G06F9/3865
摘要： Apparatus and method provide for tracking and maintaining precise state by assigning a unique identification tag to each instruction at the time of issue, associating the tag with a storage location in a first active instruction data structure, updating the data stored in the storage location in response to instruction activity status changes for each instruction, and maintaining a plurality of pointers to the storage locations that move in response to the instruction activity status. Status information includes an activity data item, such as an activity bit, that is set at the time the instruction is issued and cleared when execution completes without error. Pointers are established that point to the last issued instruction, the last committed instruction pointer, and reclaimed instruction pointer. These three pointers are moved forward toward the later issued (newer) instructions along the data structure based on comparisons of the active-bit for each location associated with one instruction in the data structure and predetermined rules. Exceptions or error conditions for any instruction prevent changing the active-bit so that movement of the pointers is controlled and prevented under these error conditions.
摘要翻译：装置和方法通过在发出时向每个指令分配唯一的识别标签来提供跟踪和保持精确状态，将标签与第一活动指令数据结构中的存储位置相关联，响应地更新存储在存储位置中的数据指示每个指令的指令活动状态变化，以及保持指向响应于指令活动状态移动的存储位置的多个指针。状态信息包括活动数据项，例如在指令发出时设置的活动位，并且当执行完成而没有错误时被清除。指针指向最后发出的指令，最后提交的指令指针和回收指令指针。基于与数据结构中的一个指令和预定规则相关联的每个位置的活动位的比较，这三个指针沿着数据结构朝向稍后发布的（较新的）指令向前移动。任何指令的异常或错误条件都会阻止更改有效位，以便在这些错误条件下控制和防止指针的移动。

5. 发明授权

US5966530A Structure and method for instruction boundary machine state restoration 失效
标题翻译：指令边界机状态恢复的结构和方法
公开(公告)号：US5966530A
公开(公告)日：1999-10-12
申请号：US872982
申请日：1997-06-11
申请人： Gene W. Shen , John Szeto , Niteen A. Patkar , Michael C. Shebanow
发明人： Gene W. Shen , John Szeto , Niteen A. Patkar , Michael C. Shebanow
IPC分类号： G06F9/312 , G06F9/38 , G06F11/14 , G06F11/00
CPC分类号： G06F9/3004 , G06F11/1407 , G06F9/30043 , G06F9/3834 , G06F9/3836 , G06F9/384 , G06F9/3842 , G06F9/3855 , G06F9/3857 , G06F9/3863 , G06F9/3865
摘要： A high-performance processor is disclosed with structure and methods for: (1) aggressively scheduling long latency instructions including load/store instructions while maintaining precise state; (2) maintaining and restoring state at any instruction boundary; (3) tracking instruction status; (4) checkpointing instructions; (5) creating, maintaining, and using a time-out checkpoint; (6) tracking floating-point exceptions; (7) creating, maintaining, and using a watchpoint for plural, simultaneous, unresolved-branch evaluation; and (9) increasing processor throughput while maintaining precise state. In one embodiment of the invention, a method of restoring machine state in a processor at any instruction boundary is disclosed. For any instruction which may modify control registers, the processor is either synchronized prior to execution or an instruction checkpoint is stored to preserve state; and for any instruction that creates a program counter discontinuity an instruction checkpoint is stored. Instruction execution status is monitored to detect a fault condition and if a fault occurs, the instruction identifier is saved according to predetermined rules and used as an endpoint to backup the program counter. If the faulting instruction is a checkpointed instruction, then the state information is restored from the checkpoint prior to reexecuting the faulting instruction, but if one of the instructions for which state was stored is sequentially between the faulting instruction and the last issued instruction, then (i) backing-up said processor to the closest checkpoint after the faulting instruction, (ii) back stepping the processor to restore state, and (iii) decrementing the program counter to the faulting instruction.
摘要翻译：公开了一种具有以下结构和方法的高性能处理器：（1）在保持精确状态的同时积极调度包括加载/存储指令的长延迟指令; （2）在任何指令边界维持和恢复状态; （3）跟踪指令状态; （4）检查点指令; （5）创建，维护和使用超时检查点; （6）跟踪浮点异常; （7）创建，维护和使用观察点进行复数，同时，未解决的分支评估; 和（9）提高处理器吞吐量同时保持精确的状态。在本发明的一个实施例中，公开了一种在任何指令边界处在处理器中恢复机器状态的方法。对于可能修改控制寄存器的任何指令，处理器在执行之前要么同步，要么存储指令检查点才能保持状态; 并且对于创建程序计数器不连续性的任何指令，存储指令检查点。监视指令执行状态以检测故障状态，如果发生故障，则根据预定规则保存指令标识符，并用作备份程序计数器的端点。如果故障指令是检查点指令，则在重新执行故障指令之前从检查点恢复状态信息，但是如果在故障指令和最后发出的指令之间顺序地存储了哪个状态的指令之一，则（ i）在故障指令之后，将所述处理器备份到最靠近的检查点，（ii）将处理器重新执行以恢复状态，以及（iii）将程序计数器递减到故障指令。

6. 发明授权

US5659721A Processor structure and method for checkpointing instructions to maintain precise state 失效
标题翻译：用于检查指令的处理器结构和方法以保持精确状态
公开(公告)号：US5659721A
公开(公告)日：1997-08-19
申请号：US476419
申请日：1995-06-07
申请人： Gene W. Shen , John Szeto , Niteen A. Patkar , Michael C. Shebanow
发明人： Gene W. Shen , John Szeto , Niteen A. Patkar , Michael C. Shebanow
IPC分类号： G06F9/312 , G06F9/38 , G06F11/14 , G06F11/00
CPC分类号： G06F9/3004 , G06F11/1407 , G06F9/30043 , G06F9/3834 , G06F9/3836 , G06F9/384 , G06F9/3842 , G06F9/3855 , G06F9/3857 , G06F9/3863 , G06F9/3865
摘要： Time-out checkpoints are formed based on a predetermined time-out condition or interval since the last checkpoint was formed rather than forming a checkpoint to store current processor state based merely on decoded instruction attributes. Such time-cut conditions may include the number of instructions issued or the number of clock cycles elapsed, for example. Time-out checkpointing limits the maximum number of instructions within a checkpoint boundary and bounds the time period for recovery from an exception condition. The processor can restore time-out based checkpointed state faster than an instruction decode based checkpoint technique in the event of an exception so long as the instruction window size is greater than the maximum number of instructions within a checkpoint boundary, and such method eliminates processor state restoration dependency on instruction window size. Time-out checkpoints may be implemented with conventional. checkpoints, or in a novel logical and physical register rename map checkpointing technique. Timeout checkpoint formation may be used with conventional processor backup techniques as well as with a novel backtracking technique including processor backup and backstepping.
摘要翻译：基于预定的超时条件或时间间隔形成超时检查点，因为上一次检查点形成而不是形成检查点，以便仅仅依赖于解码的指令属性来存储当前的处理器状态。这样的时间切割条件可以包括例如发出的指令的数量或经过的时钟周期的数量。超时检查点限制检查点边界内的最大指令数，并限制从异常情况恢复的时间段。只要指令窗口大小大于检查点边界内的指令的最大数量，处理器可以在发生异常的情况下比基于指令解码的检查点技术更快地恢复基于超时的检查点状态，并且这种方法消除了处理器状态恢复依赖于指令窗口大小。超时检查点可以用常规的方式实现。检查点或新颖的逻辑和物理寄存器重命名映射检查技术。超时检查点的形成可以与常规的处理器备份技术一起使用，还可以使用包括处理器备份和后台步骤的新型回溯技术。

7. 发明授权

US06449671B1 Method and apparatus for busing data elements 失效
标题翻译：调用数据元素的方法和装置
公开(公告)号：US06449671B1
公开(公告)日：2002-09-10
申请号：US09328971
申请日：1999-06-09
申请人： Niteen A. Patkar , Stephen C. Purcell , Shalesh Thusoo , Korbin S. Van Dyke
发明人： Niteen A. Patkar , Stephen C. Purcell , Shalesh Thusoo , Korbin S. Van Dyke
IPC分类号： G06F1300
CPC分类号： G06F12/0806
摘要： A method and apparatus for busing data elements within a computing system includes processing that begins by providing, on a shared bus, a first control signal relating to a first transaction during a first bus cycle. The processing continues by providing a second control signal relating to a second transaction and a first address signal relating to the first transaction during a second bus cycle. The processing continues by providing a third control signal relating to a third transaction and a second address signal relating to a second transaction during a third bus cycle. The processing then continues by providing a first status relating to the first transaction and a third addressing signal relating to the third transaction during a fourth bus cycle. The processing then continues by providing a second status relating to the second transaction during a fifth bus cycle. The processing then continues by providing first data relating to the first transaction when the first status is a hit and providing third status relating to the third transaction during a sixth bus cycle.
摘要翻译：用于在计算系统内传送数据元素的方法和装置包括开始于在共享总线上提供在第一总线周期期间与第一事务相关的第一控制信号的处理。通过在第二总线周期期间提供与第二事务相关的第二控制信号和与第一事务相关的第一地址信号来继续处理。通过在第三总线周期期间提供与第三事务相关的第三控制信号和与第二事务相关的第二地址信号来继续处理。然后通过在第四总线周期期间提供与第一事务相关的第一状态和与第三事务相关的第三寻址信号来继续处理。然后通过在第五总线周期期间提供与第二事务相关的第二状态来继续处理。然后，当第一状态是命中时，通过提供与第一事务有关的第一数据继续处理，并在第六总线周期期间提供与第三事务有关的第三状态。

8. 发明授权

US5708788A Method for adjusting fetch program counter in response to the number of instructions fetched and issued 失效
标题翻译：响应于提取和发出的指令数量来调整提取程序计数器的方法
公开(公告)号：US5708788A
公开(公告)日：1998-01-13
申请号：US524294
申请日：1995-09-05
申请人： Akira Katsuno , Niteen A Patkar , Sunil W. Savkar , Michael C. Shebanow
发明人： Akira Katsuno , Niteen A Patkar , Sunil W. Savkar , Michael C. Shebanow
IPC分类号： G06F9/32 , G06F9/38 , G06F9/30
CPC分类号： G06F9/3814 , G06F9/321 , G06F9/3802
摘要： A clocked instruction flow is managed subject to issue and fetch constraints through a plurality of instruction latches which receive instructions from selected memory locations. By checking the number of instructions fetched and issued, the fetch program counter is adjusted responsive to the status of selected state variables indicating instructions issued and fetched. The instruction latches are fully scheduled from cycle to cycle with instructions, by fetching instructions in accordance with a fetch program counter.
摘要翻译：通过从选择的存储器位置接收指令的多个指令锁存器来管理时钟指令流程，发出和获取约束。通过检查提取和发出的指令数量，响应于指示发出和取出的指令的所选状态变量的状态来调整取出程序计数器。指令锁存器通过指令从周期到周期完全调度，通过根据获取程序计数器获取指令。

9. 发明授权

US5651124A Processor structure and method for aggressively scheduling long latency instructions including load/store instructions while maintaining precise state 失效
标题翻译：处理器结构和方法，用于在保持精确状态的同时积极调度长延迟指令，包括加载/存储指令
公开(公告)号：US5651124A
公开(公告)日：1997-07-22
申请号：US478025
申请日：1995-06-07
申请人： Gene W. Shen , John Szeto , Niteen A. Patkar , Michael C. Shebanow , Michael A. Simone
发明人： Gene W. Shen , John Szeto , Niteen A. Patkar , Michael C. Shebanow , Michael A. Simone
IPC分类号： G06F9/312 , G06F9/38 , G06F11/14 , G06F11/00
CPC分类号： G06F9/3004 , G06F11/1407 , G06F9/30043 , G06F9/3834 , G06F9/3836 , G06F9/384 , G06F9/3842 , G06F9/3855 , G06F9/3857 , G06F9/3863 , G06F9/3865
摘要： Time-out checkpoints are formed based on a predetermined time-out condition or interval since the last checkpoint was formed rather than forming a checkpoint to store current processor state based merely on decoded instruction attributes. Such time-out conditions may include the number of instructions issued or the number of clock cycles elapsed, for example. Time-out checkpointing limits the maximum number of instructions within a checkpoint boundary and bounds the time period for recovery from an exception condition. The processor can restore time-out based checkpointed state faster than an instruction decode based checkpoint technique in the event of an exception so long as the instruction window size is greater than the maximum number of instructions within a checkpoint boundary, and such method eliminates processor state restoration dependency on instruction window size. Time-out checkpoints may be implemented with conventional checkpoints, or in a novel logical and physical register rename map checkpointing technique. Timeout checkpoint formation may be used with conventional processor backup techniques as well as with a novel backtracking technique including processor backup and backstepping.
摘要翻译：基于预定的超时条件或时间间隔形成超时检查点，因为上一次检查点形成而不是形成检查点，以便仅仅依赖于解码的指令属性来存储当前的处理器状态。例如，这种超时条件可以包括发出的指令的数量或经过的时钟周期的数量。超时检查点限制检查点边界内的最大指令数，并限制从异常情况恢复的时间段。只要指令窗口大小大于检查点边界内的指令的最大数量，处理器可以在发生异常的情况下比基于指令解码的检查点技术更快地恢复基于超时的检查点状态，并且这种方法消除了处理器状态恢复依赖于指令窗口大小。超时检查点可以用常规检查点或新颖的逻辑和物理寄存器重命名映射检查点技术来实现。超时检查点的形成可以与常规的处理器备份技术一起使用，还可以使用包括处理器备份和后台步骤的新型回溯技术。

10. 发明授权

US5649136A Processor structure and method for maintaining and restoring precise state at any instruction boundary 失效
标题翻译：用于在任何指令边界维持和恢复精确状态的处理器结构和方法
公开(公告)号：US5649136A
公开(公告)日：1997-07-15
申请号：US483958
申请日：1995-06-07
申请人： Gene W. Shen , John Szeto , Niteen A. Patkar , Michael C. Shebanow
发明人： Gene W. Shen , John Szeto , Niteen A. Patkar , Michael C. Shebanow
IPC分类号： G06F9/312 , G06F9/38 , G06F11/14 , G06F11/00
CPC分类号： G06F9/3004 , G06F11/1407 , G06F9/30043 , G06F9/3834 , G06F9/3836 , G06F9/384 , G06F9/3842 , G06F9/3855 , G06F9/3857 , G06F9/3863 , G06F9/3865
摘要： A high-performance processor is disclosed with structure and methods for: (1) aggressively scheduling long latency instructions including load/store instructions while maintaining precise state; (2) maintaining and restoring precise state at any instruction boundary; (3) tracking instruction status to maintain precise state; (4) checkpointing instructions to maintain precise state; (5) creating, maintaining, and using a time-out checkpoint; (6) tracking floating-point exceptions; (7) creating, maintaining, and using a watchpoint for plural, simultaneous, unresolved-branch evaluation; and (9) increasing processor throughput while maintaining precise state.
摘要翻译：公开了一种具有以下结构和方法的高性能处理器：（1）在保持精确状态的同时积极调度包括加载/存储指令的长延迟指令; （2）在任何指令边界保持和恢复精确状态; （3）跟踪指令状态以保持精确状态; （4）检查点指令保持精确状态; （5）创建，维护和使用超时检查点; （6）跟踪浮点异常; （7）创建，维护和使用观察点进行复数，同时，未解决的分支评估; 和（9）提高处理器吞吐量同时保持精确的状态。

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