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1. 发明授权

US5708788A Method for adjusting fetch program counter in response to the number of instructions fetched and issued 失效
标题翻译：响应于提取和发出的指令数量来调整提取程序计数器的方法
公开(公告)号：US5708788A
公开(公告)日：1998-01-13
申请号：US524294
申请日：1995-09-05
申请人： Akira Katsuno , Niteen A Patkar , Sunil W. Savkar , Michael C. Shebanow
发明人： Akira Katsuno , Niteen A Patkar , Sunil W. Savkar , Michael C. Shebanow
IPC分类号： G06F9/32 , G06F9/38 , G06F9/30
CPC分类号： G06F9/3814 , G06F9/321 , G06F9/3802
摘要： A clocked instruction flow is managed subject to issue and fetch constraints through a plurality of instruction latches which receive instructions from selected memory locations. By checking the number of instructions fetched and issued, the fetch program counter is adjusted responsive to the status of selected state variables indicating instructions issued and fetched. The instruction latches are fully scheduled from cycle to cycle with instructions, by fetching instructions in accordance with a fetch program counter.
摘要翻译：通过从选择的存储器位置接收指令的多个指令锁存器来管理时钟指令流程，发出和获取约束。通过检查提取和发出的指令数量，响应于指示发出和取出的指令的所选状态变量的状态来调整取出程序计数器。指令锁存器通过指令从周期到周期完全调度，通过根据获取程序计数器获取指令。

2. 发明授权

US5225372A Method of making a semiconductor device having an improved metallization structure 失效
标题翻译：制造具有改进的金属化结构的半导体器件的方法
公开(公告)号：US5225372A
公开(公告)日：1993-07-06
申请号：US632696
申请日：1990-12-24
申请人： Sunil W. Savkar , Edward O. Travis
发明人： Sunil W. Savkar , Edward O. Travis
IPC分类号： H01L21/285 , H01L21/3205 , H01L21/768
CPC分类号： H01L21/32051 , H01L21/28512 , H01L21/76889
摘要： An improved semiconductor device interconnect comprising a conductive layer (30) with an underlying diffusion barrier metal (26) is attached to a doped glass layer (20) by an intermediate metal adhesion layer (22). The metal adhesion layer (22) is deposited onto the doped glass layer (30) prior to the formation of contact openings (24) in the doped glass layer (30) and the subsequent formation of the interconnect metallization. In one embodiment, a titanium diffusion barrier (26) is deposited onto a doped glass layer (30) having an aluminum metal adhesion layer (22) thereon and contact openings (24) therethrough. The titanium is annealed to form a silicide (28) in a substrate region (14) exposed by the contact opening (24) and an aluminum interconnect (32) is formed contacting the silicide region (28).
摘要翻译：包括具有下面的扩散阻挡金属（26）的导电层（30）的改进的半导体器件互连通过中间金属粘合层（22）附着到掺杂的玻璃层（20）。在掺杂的玻璃层（30）中形成接触开口（24）并随后形成互连金属化之后，将金属粘合层（22）沉积到掺杂的玻璃层（30）上。在一个实施例中，在其上具有铝金属粘附层（22）的掺杂玻璃层（30）和穿过其中的接触开口（24）上沉积钛扩散阻挡层（26）。将钛退火以在由接触开口（24）暴露的衬底区域（14）中形成硅化物（28），并且形成接触硅化物区域（28）的铝互连（32）。

3. 发明授权

US5896528A Superscalar processor with multiple register windows and speculative return address generation 失效
标题翻译：具有多个寄存器窗口和推测返回地址生成的超标量处理器
公开(公告)号：US5896528A
公开(公告)日：1999-04-20
申请号：US522845
申请日：1995-09-01
申请人： Akira Katsuno , Sunil W. Savkar , Michael C. Shebanow
发明人： Akira Katsuno , Sunil W. Savkar , Michael C. Shebanow
IPC分类号： G06F9/32 , G06F9/38 , G06F9/42
CPC分类号： G06F9/3806 , G06F9/30054 , G06F9/30058 , G06F9/30127 , G06F9/4426
摘要： A superscaler processor capable of executing multiple instructions concurrently. The processor includes a program counter which identifies instructions for execution by multiple execution units. Further included is a register file made up of multiple register window pointer selects one of the multiple register windows. In response to the value of the current window pointer, a return prediction table provides a speculative program counter value, indicative of a return address of an instruction for a subroutine, corresponding to the selected register window. A watchpoint register stores the speculative program counter value. A fetch program counter, in response to the speculative program counter value, stores the instructions for execution after they have been identified by the program counter.
摘要翻译：能够同时执行多个指令的超标量处理器。该处理器包括一个程序计数器，用于识别由多个执行单元执行的指令。另外包括由多个寄存器窗口指针组成的寄存器文件，用于选择多个寄存器窗口之一。响应于当前窗口指针的值，返回预测表提供与所选择的寄存器窗口相对应的指示子程序的指令的返回地址的推测程序计数器值。观察点寄存器存储推测程序计数器值。获取程序计数器响应于推测程序计数器值，在由程序计数器识别之后存储用于执行的指令。

4. 发明授权

US5860152A Method and apparatus for rapid computation of target addresses for relative control transfer instructions 失效
标题翻译：用于快速计算相对控制传输指令的目标地址的方法和装置
公开(公告)号：US5860152A
公开(公告)日：1999-01-12
申请号：US956251
申请日：1997-10-22
申请人： Sunil W. Savkar
发明人： Sunil W. Savkar
IPC分类号： G06F9/32
CPC分类号： G06F9/324 , G06F9/322
摘要： A method and apparatus accepts a relative control transfer instruction and generates a compact absolute control transfer instruction which may have a number of bits one greater than the relative control transfer instruction and including flags to rapidly construct the target address of the relative control transfer instruction. The compact absolute control transfer instruction is generated by sign extending the displacement of the relative control transfer instructions and adding it to a set of least significant bits from the control transfer instruction address, and optionally coupling some or all of the bits from the result with the original opcode or a different opcode. The target address of the relative control transfer instruction is determined by using, incrementing or decrementing, depending on the state of the flags, a group of the most significant bits from the relative control transfer instruction address and appending the result with the least significant bits from the result of the addition described above.
摘要翻译：一种方法和装置接受相对控制传送指令，并产生紧密的绝对控制传送指令，该指令可以具有比相对控制传送指令大一位的位数，并且包括快速构建相对控制传送指令的目标地址的标志。紧凑的绝对控制传送指令是通过扩展相对控制传送指令的位移并将其从控制传送指令地址添加到一组最低有效位的符号来产生的，并且可选地将结果中的一些或全部位与原始操作码或不同的操作码。相对控制传送指令的目标地址是根据标志的状态通过使用，递增或递减来确定的，来自相对控制传送指令地址的最高有效位组，并将结果与最低有效位相加上述添加的结果。

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