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1. 发明授权

US07861066B2 Mechanism for predicting and suppressing instruction replay in a processor 有权
标题翻译：在处理器中预测和抑制指令重放的机制
公开(公告)号：US07861066B2
公开(公告)日：2010-12-28
申请号：US11780684
申请日：2007-07-20
申请人： Ashutosh S. Dhodapkar , Michael G. Butler , Gene W. Shen
发明人： Ashutosh S. Dhodapkar , Michael G. Butler , Gene W. Shen
IPC分类号： G06F9/30
CPC分类号： G06F9/3861 , G06F9/3836 , G06F9/3838 , G06F9/3844
摘要： A mechanism for suppressing instruction replay includes a processor having one or more execution units and a scheduler that issue instruction operations for execution by the one or more execution units. The scheduler may also cause instruction operations that are determined to be incorrectly executed to be replayed, or reissued. In addition, a prediction unit within the processor may predict whether a given instruction operation will replay and to provide an indication that the given instruction operation will replay. The processor also includes a decode unit that may decode instructions and in response to detecting the indication, may flag the given instruction operation. The scheduler may further inhibit issue of the flagged instruction operation until a status associated with the flagged instruction is good.
摘要翻译：用于抑制指令重放的机构包括具有一个或多个执行单元的处理器和发出由一个或多个执行单元执行的指令操作的调度器。调度器还可以导致被确定为不正确执行以重播或重新发行的指令操作。此外，处理器内的预测单元可以预测给定指令操作是否将重放，并提供给定指令操作将重放的指示。处理器还包括解码单元，其可以解码指令并且响应于检测到指示，可以标记给定的指令操作。调度器可以进一步禁止标记指令操作的发生，直到与被标记的指令相关联的状态良好。

2. 发明申请

US20090024838A1 MECHANISM FOR SUPPRESSING INSTRUCTION REPLAY IN A PROCESSOR 有权
标题翻译：用于在加工商中禁止指示性重置的机制
公开(公告)号：US20090024838A1
公开(公告)日：2009-01-22
申请号：US11780684
申请日：2007-07-20
申请人： Ashutosh S. Dhodapkar , Michael G. Butler , Gene W. Shen
发明人： Ashutosh S. Dhodapkar , Michael G. Butler , Gene W. Shen
IPC分类号： G06F9/30
CPC分类号： G06F9/3861 , G06F9/3836 , G06F9/3838 , G06F9/3844
摘要： A mechanism for suppressing instruction replay includes a processor having one or more execution units and a scheduler that issue instruction operations for execution by the one or more execution units. The scheduler may also cause instruction operations that are determined to be incorrectly executed to be replayed, or reissued. In addition, a prediction unit within the processor may predict whether a given instruction operation will replay and to provide an indication that the given instruction operation will replay. The processor also includes a decode unit that may decode instructions and in response to detecting the indication, may flag the given instruction operation. The scheduler may further inhibit issue of the flagged instruction operation until a status associated with the flagged instruction is good.
摘要翻译：用于抑制指令重放的机构包括具有一个或多个执行单元的处理器和发出由一个或多个执行单元执行的指令操作的调度器。调度器还可以导致被确定为不正确执行以重播或重新发行的指令操作。此外，处理器内的预测单元可以预测给定指令操作是否将重放，并提供给定指令操作将重放的指示。处理器还包括解码单元，其可以解码指令并且响应于检测到指示，可以标记给定的指令操作。调度器可以进一步禁止标记指令操作的发生，直到与被标记的指令相关联的状态良好。

3. 发明申请

US20090019257A1 Method and Apparatus for Length Decoding and Identifying Boundaries of Variable Length Instructions 有权
标题翻译：用于长度解码和识别可变长度指令边界的方法和装置
公开(公告)号：US20090019257A1
公开(公告)日：2009-01-15
申请号：US11775456
申请日：2007-07-10
申请人： Gene W. Shen , Sean Lie
发明人： Gene W. Shen , Sean Lie
IPC分类号： G06F15/76
CPC分类号： G06F9/3822 , G06F9/30152 , G06F9/3814 , G06F9/382
摘要： A mechanism for superscalar decode of variable length instructions. A length decode unit may obtain a plurality of instruction bytes based on a scan window of a predetermined size. The instruction bytes may be associated with a plurality of variable length instructions, which are scheduled to be executed by a processing unit. The length decode unit may, for each instruction byte, estimate the start of a next variable length instruction following a current variable length instruction, and store a first pointer. A pre-pick unit may, for each instruction byte, use the first pointer to estimate the start of a subsequent variable length instruction following the next variable length instruction within the scan window, and store a second pointer. A pick unit may use a start pointer and related first and second pointers to determine the actual start of the variable length instructions within the scan window, and generate instruction pointers.
摘要翻译：用于可变长度指令的超标量解码的机制。长度解码单元可以基于预定大小的扫描窗口获得多个指令字节。指令字节可以与被调度为由处理单元执行的多个可变长度指令相关联。对于每个指令字节，长度解码单元可以估计当前可变长度指令之后的下一可变长度指令的开始，并存储第一指针。对于每个指令字节，预选单元可以使用第一指针来估计在扫描窗口内的下一个可变长度指令之后的后续可变长度指令的开始，并存储第二指针。拾取单元可以使用起始指针和相关的第一和第二指针来确定扫描窗口内的可变长度指令的实际开始，并且生成指令指针。

4. 发明授权

US5651124A Processor structure and method for aggressively scheduling long latency instructions including load/store instructions while maintaining precise state 失效
标题翻译：处理器结构和方法，用于在保持精确状态的同时积极调度长延迟指令，包括加载/存储指令
公开(公告)号：US5651124A
公开(公告)日：1997-07-22
申请号：US478025
申请日：1995-06-07
申请人： Gene W. Shen , John Szeto , Niteen A. Patkar , Michael C. Shebanow , Michael A. Simone
发明人： Gene W. Shen , John Szeto , Niteen A. Patkar , Michael C. Shebanow , Michael A. Simone
IPC分类号： G06F9/312 , G06F9/38 , G06F11/14 , G06F11/00
CPC分类号： G06F9/3004 , G06F11/1407 , G06F9/30043 , G06F9/3834 , G06F9/3836 , G06F9/384 , G06F9/3842 , G06F9/3855 , G06F9/3857 , G06F9/3863 , G06F9/3865
摘要： Time-out checkpoints are formed based on a predetermined time-out condition or interval since the last checkpoint was formed rather than forming a checkpoint to store current processor state based merely on decoded instruction attributes. Such time-out conditions may include the number of instructions issued or the number of clock cycles elapsed, for example. Time-out checkpointing limits the maximum number of instructions within a checkpoint boundary and bounds the time period for recovery from an exception condition. The processor can restore time-out based checkpointed state faster than an instruction decode based checkpoint technique in the event of an exception so long as the instruction window size is greater than the maximum number of instructions within a checkpoint boundary, and such method eliminates processor state restoration dependency on instruction window size. Time-out checkpoints may be implemented with conventional checkpoints, or in a novel logical and physical register rename map checkpointing technique. Timeout checkpoint formation may be used with conventional processor backup techniques as well as with a novel backtracking technique including processor backup and backstepping.
摘要翻译：基于预定的超时条件或时间间隔形成超时检查点，因为上一次检查点形成而不是形成检查点，以便仅仅依赖于解码的指令属性来存储当前的处理器状态。例如，这种超时条件可以包括发出的指令的数量或经过的时钟周期的数量。超时检查点限制检查点边界内的最大指令数，并限制从异常情况恢复的时间段。只要指令窗口大小大于检查点边界内的指令的最大数量，处理器可以在发生异常的情况下比基于指令解码的检查点技术更快地恢复基于超时的检查点状态，并且这种方法消除了处理器状态恢复依赖于指令窗口大小。超时检查点可以用常规检查点或新颖的逻辑和物理寄存器重命名映射检查点技术来实现。超时检查点的形成可以与常规的处理器备份技术一起使用，还可以使用包括处理器备份和后台步骤的新型回溯技术。

5. 发明授权

US5649136A Processor structure and method for maintaining and restoring precise state at any instruction boundary 失效
标题翻译：用于在任何指令边界维持和恢复精确状态的处理器结构和方法
公开(公告)号：US5649136A
公开(公告)日：1997-07-15
申请号：US483958
申请日：1995-06-07
申请人： Gene W. Shen , John Szeto , Niteen A. Patkar , Michael C. Shebanow
发明人： Gene W. Shen , John Szeto , Niteen A. Patkar , Michael C. Shebanow
IPC分类号： G06F9/312 , G06F9/38 , G06F11/14 , G06F11/00
CPC分类号： G06F9/3004 , G06F11/1407 , G06F9/30043 , G06F9/3834 , G06F9/3836 , G06F9/384 , G06F9/3842 , G06F9/3855 , G06F9/3857 , G06F9/3863 , G06F9/3865
摘要： A high-performance processor is disclosed with structure and methods for: (1) aggressively scheduling long latency instructions including load/store instructions while maintaining precise state; (2) maintaining and restoring precise state at any instruction boundary; (3) tracking instruction status to maintain precise state; (4) checkpointing instructions to maintain precise state; (5) creating, maintaining, and using a time-out checkpoint; (6) tracking floating-point exceptions; (7) creating, maintaining, and using a watchpoint for plural, simultaneous, unresolved-branch evaluation; and (9) increasing processor throughput while maintaining precise state.
摘要翻译：公开了一种具有以下结构和方法的高性能处理器：（1）在保持精确状态的同时积极调度包括加载/存储指令的长延迟指令; （2）在任何指令边界保持和恢复精确状态; （3）跟踪指令状态以保持精确状态; （4）检查点指令保持精确状态; （5）创建，维护和使用超时检查点; （6）跟踪浮点异常; （7）创建，维护和使用观察点进行复数，同时，未解决的分支评估; 和（9）提高处理器吞吐量同时保持精确的状态。

6. 发明授权

US07818542B2 Method and apparatus for length decoding variable length instructions 有权
标题翻译：长度解码可变长度指令的方法和装置
公开(公告)号：US07818542B2
公开(公告)日：2010-10-19
申请号：US11775451
申请日：2007-07-10
申请人： Gene W. Shen , Sean Lie
发明人： Gene W. Shen , Sean Lie
IPC分类号： G06F9/30 , G06F9/32
CPC分类号： G06F9/30152 , G06F9/3814 , G06F9/382 , G06F9/3822
摘要： A mechanism for superscalar decode of variable length instructions. The decode mechanism may be included within a processing unit, and may comprise a length decode unit. The length decode unit may obtain a plurality of instruction bytes. The instruction bytes may be associated with a plurality of variable length instructions, which are to be executed by the processing unit. The length decode unit may perform a length decode operation for each of the plurality of instruction bytes. For each instruction byte, the length decode unit may estimate the instruction length of a current variable length instruction associated with a current instruction byte. Furthermore, during the length decode operation, for each instruction byte, the length decode unit may estimate the start of a next variable length instruction based on the estimated instruction length of the current variable length instruction, and store a first pointer to the estimated start of the next variable length instruction.
摘要翻译：用于可变长度指令的超标量解码的机制。解码机构可以包括在处理单元内，并且可以包括长度解码单元。长度解码单元可以获得多个指令字节。指令字节可以与由处理单元执行的多个可变长度指令相关联。长度解码单元可以对多个指令字节中的每一个执行长度解码操作。对于每个指令字节，长度解码单元可以估计与当前指令字节相关的当前可变长度指令的指令长度。此外，在长度解码操作期间，对于每个指令字节，长度解码单元可以基于当前可变长度指令的估计指令长度来估计下一个可变长度指令的开始，并将第一个指针存储到下一个可变长度指令。

7. 发明申请

US20090024836A1 MULTIPLE-CORE PROCESSOR WITH HIERARCHICAL MICROCODE STORE 有权
标题翻译：具有分层微处理器的多核处理器
公开(公告)号：US20090024836A1
公开(公告)日：2009-01-22
申请号：US11779642
申请日：2007-07-18
申请人： Gene W. Shen , Bruce R. Holloway , Sean Lie , Michael G. Butler
发明人： Gene W. Shen , Bruce R. Holloway , Sean Lie , Michael G. Butler
IPC分类号： G06F9/26
CPC分类号： G06F9/28 , G06F9/223
摘要： A multiple-core processor having a hierarchical microcode store. A processor may include multiple processor cores, each configured to independently execute instructions defined according to a programmer-visible instruction set architecture (ISA). Each core may include a respective local microcode unit configured to store microcode entries. The processor may also include a remote microcode unit accessible by each of the processor cores. Any given one of the processor cores may be configured to generate a given microcode entrypoint corresponding to a particular microcode entry including one or more operations to be executed by the given processor core, and to determine whether the particular microcode entry is stored within the respective local microcode unit of the given core. In response to determining that the particular microcode entry is not stored within the respective local microcode unit, the given core may convey a request for the particular microcode entry to the remote microcode unit.
摘要翻译：具有分级微代码存储器的多核处理器。处理器可以包括多个处理器核心，每个处理器核心被配置为独立地执行根据编程器 - 可见指令集架构（ISA）定义的指令。每个核心可以包括被配置为存储微代码条目的相应的本地微代码单元。处理器还可以包括可由每个处理器核心访问的远程微代码单元。任何给定的一个处理器核心可以被配置为生成对应于特定微代码条目的给定微代码入口点，该特定微代码条目包括要由给定处理器核心执行的一个或多个操作，并且确定特定微代码条目是否存储在各自的本地给定核心的微码单元。响应于确定特定微代码条目未存储在相应的本地微代码单元内，给定的核心可以向远程微代码单元传达特定微代码条目的请求。

8. 发明授权

US5751985A Processor structure and method for tracking instruction status to maintain precise state 失效
标题翻译：用于跟踪指令状态以保持精确状态的处理器结构和方法
公开(公告)号：US5751985A
公开(公告)日：1998-05-12
申请号：US487801
申请日：1995-06-07
申请人： Gene W. Shen , John Szeto , Niteen A. Patkar , Michael C. Shebanow
发明人： Gene W. Shen , John Szeto , Niteen A. Patkar , Michael C. Shebanow
IPC分类号： G06F9/312 , G06F9/38 , G06F11/14 , G06F9/30
CPC分类号： G06F9/3004 , G06F11/1407 , G06F9/30043 , G06F9/3834 , G06F9/3836 , G06F9/384 , G06F9/3842 , G06F9/3855 , G06F9/3857 , G06F9/3863 , G06F9/3865
摘要： Apparatus and method provide for tracking and maintaining precise state by assigning a unique identification tag to each instruction at the time of issue, associating the tag with a storage location in a first active instruction data structure, updating the data stored in the storage location in response to instruction activity status changes for each instruction, and maintaining a plurality of pointers to the storage locations that move in response to the instruction activity status. Status information includes an activity data item, such as an activity bit, that is set at the time the instruction is issued and cleared when execution completes without error. Pointers are established that point to the last issued instruction, the last committed instruction pointer, and reclaimed instruction pointer. These three pointers are moved forward toward the later issued (newer) instructions along the data structure based on comparisons of the active-bit for each location associated with one instruction in the data structure and predetermined rules. Exceptions or error conditions for any instruction prevent changing the active-bit so that movement of the pointers is controlled and prevented under these error conditions.
摘要翻译：装置和方法通过在发出时向每个指令分配唯一的识别标签来提供跟踪和保持精确状态，将标签与第一活动指令数据结构中的存储位置相关联，响应地更新存储在存储位置中的数据指示每个指令的指令活动状态变化，以及保持指向响应于指令活动状态移动的存储位置的多个指针。状态信息包括活动数据项，例如在指令发出时设置的活动位，并且当执行完成而没有错误时被清除。指针指向最后发出的指令，最后提交的指令指针和回收指令指针。基于与数据结构中的一个指令和预定规则相关联的每个位置的活动位的比较，这三个指针沿着数据结构朝向稍后发布的（较新的）指令向前移动。任何指令的异常或错误条件都会阻止更改有效位，以便在这些错误条件下控制和防止指针的移动。

9. 发明授权

US5673426A Processor structure and method for tracking floating-point exceptions 失效
公开(公告)号：US5673426A
公开(公告)日：1997-09-30
申请号：US484795
申请日：1995-06-07
申请人： Gene W. Shen , John Szeto , Michael C. Shebanow
发明人： Gene W. Shen , John Szeto , Michael C. Shebanow
IPC分类号： G06F9/312 , G06F9/38 , G06F11/14 , G06F7/46
CPC分类号： G06F9/3004 , G06F11/1407 , G06F9/30043 , G06F9/3834 , G06F9/3836 , G06F9/384 , G06F9/3842 , G06F9/3855 , G06F9/3857 , G06F9/3863 , G06F9/3865
摘要： An out of program control order execution data processor that comprises an issue unit, execution means, a floating point exception unit a precise state unit, a floating point status register, and writing means. The issue unit issues instructions in program control order for execution. The issued instructions include floating point instructions and non-floating point instructions. The execution means executes the issued instructions such that at least the floating point instructions may be executed out of program control order by the execution means. The floating point exception unit includes a data storage structure including storage elements. Each issued instruction corresponds to one of the storage elements. Each storage element has a floating point instruction identifying field and a floating point trap type field. The floating point exception unit also includes first logic to write, for each issued instruction, data in the floating point instruction identifying field of the corresponding storage element which indicates whether or not the corresponding issued instruction is a floating point instruction. It further includes second logic to write, for each issued floating point instruction which causes during execution one or more floating point execution exceptions that will result in a corresponding one of a plurality of predefined types of floating point execution traps, data in the floating point trap type field of the corresponding storage element which identifies the one of the predefined types of floating point execution traps that will result. The precise state means retires each issued instruction which does not cause an execution exception during execution and for which all issued instructions preceding it in program control order have been retired. When a first one of the predefined execution exceptions is caused by an issued instruction, the execution means continues execution of issued instructions and the precise state means engages in execution trap sequencing by continuing to retire issued instructions until it encounters an issued instruction that cannot be retired. The issued instruction that cannot be retired being one of (a) the issued instruction that caused the first execution exception, and (b) an issued instruction that was issued earlier than the issued instruction that caused the first execution exception but which caused a second execution exception occurring later than the first execution exception. The floating point status register has a floating point trap type field. The writing means writes data to the floating point trap type field of the floating point status register which identifies the type of floating point execution trap identified by the data in the floating point trap type field of the storage element corresponding to the instruction that cannot be retired when the data in the floating point identifying field of the storage element corresponding to the instruction that cannot be retired indicates that the instruction that cannot be retired is a floating point instruction.

10. 发明申请

US20080195844A1 Redirect Recovery Cache 有权
标题翻译：重定向恢复缓存
公开(公告)号：US20080195844A1
公开(公告)日：2008-08-14
申请号：US11674566
申请日：2007-02-13
申请人： Gene W. Shen , Sean Lie
发明人： Gene W. Shen , Sean Lie
IPC分类号： G06F9/312
CPC分类号： G06F9/3844 , G06F9/3808 , G06F9/3861
摘要： In one embodiment, a processor comprises a branch resolution unit and a redirect recovery cache. The branch resolution unit is configured to detect a mispredicted branch operation, and to transmit a redirect address for fetching instructions from a correct target of the branch operation responsive to detecting the mispredicted branch operation. The redirect recovery cache comprises a plurality of cache entries, each cache entry configured to store operations corresponding to instructions fetched in response to respective mispredicted branch operations. The redirect recovery cache is coupled to receive the redirect address and, if the redirect address is a hit in the redirect recovery cache, the redirect recovery cache is configured to supply operations from the hit cache entry to a pipeline of the processor, bypassing at least one initial pipeline stage.
摘要翻译：在一个实施例中，处理器包括分支解决单元和重定向恢复高速缓存。分支解决单元被配置为检测错误的分支操作，并且响应于检测到错误的分支操作，发送用于从分支操作的正确目标获取指令的重定向地址。重定向恢复高速缓存包括多个高速缓存条目，每个高速缓存条目被配置为存储对应于响应于相应的错误预测的分支操作而获取的指令的操作。重定向恢复缓存被耦合以接收重定向地址，并且如果重定向地址是重定向恢复高速缓存中的命中，则重定向恢复高速缓存被配置为将命中高速缓存条目的操作提供给处理器的流水线，至少绕过一个初始流水线阶段。

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