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1. 发明授权

US5966530A Structure and method for instruction boundary machine state restoration 失效
标题翻译：指令边界机状态恢复的结构和方法
公开(公告)号：US5966530A
公开(公告)日：1999-10-12
申请号：US872982
申请日：1997-06-11
申请人： Gene W. Shen , John Szeto , Niteen A. Patkar , Michael C. Shebanow
发明人： Gene W. Shen , John Szeto , Niteen A. Patkar , Michael C. Shebanow
IPC分类号： G06F9/312 , G06F9/38 , G06F11/14 , G06F11/00
CPC分类号： G06F9/3004 , G06F11/1407 , G06F9/30043 , G06F9/3834 , G06F9/3836 , G06F9/384 , G06F9/3842 , G06F9/3855 , G06F9/3857 , G06F9/3863 , G06F9/3865
摘要： A high-performance processor is disclosed with structure and methods for: (1) aggressively scheduling long latency instructions including load/store instructions while maintaining precise state; (2) maintaining and restoring state at any instruction boundary; (3) tracking instruction status; (4) checkpointing instructions; (5) creating, maintaining, and using a time-out checkpoint; (6) tracking floating-point exceptions; (7) creating, maintaining, and using a watchpoint for plural, simultaneous, unresolved-branch evaluation; and (9) increasing processor throughput while maintaining precise state. In one embodiment of the invention, a method of restoring machine state in a processor at any instruction boundary is disclosed. For any instruction which may modify control registers, the processor is either synchronized prior to execution or an instruction checkpoint is stored to preserve state; and for any instruction that creates a program counter discontinuity an instruction checkpoint is stored. Instruction execution status is monitored to detect a fault condition and if a fault occurs, the instruction identifier is saved according to predetermined rules and used as an endpoint to backup the program counter. If the faulting instruction is a checkpointed instruction, then the state information is restored from the checkpoint prior to reexecuting the faulting instruction, but if one of the instructions for which state was stored is sequentially between the faulting instruction and the last issued instruction, then (i) backing-up said processor to the closest checkpoint after the faulting instruction, (ii) back stepping the processor to restore state, and (iii) decrementing the program counter to the faulting instruction.
摘要翻译：公开了一种具有以下结构和方法的高性能处理器：（1）在保持精确状态的同时积极调度包括加载/存储指令的长延迟指令; （2）在任何指令边界维持和恢复状态; （3）跟踪指令状态; （4）检查点指令; （5）创建，维护和使用超时检查点; （6）跟踪浮点异常; （7）创建，维护和使用观察点进行复数，同时，未解决的分支评估; 和（9）提高处理器吞吐量同时保持精确的状态。在本发明的一个实施例中，公开了一种在任何指令边界处在处理器中恢复机器状态的方法。对于可能修改控制寄存器的任何指令，处理器在执行之前要么同步，要么存储指令检查点才能保持状态; 并且对于创建程序计数器不连续性的任何指令，存储指令检查点。监视指令执行状态以检测故障状态，如果发生故障，则根据预定规则保存指令标识符，并用作备份程序计数器的端点。如果故障指令是检查点指令，则在重新执行故障指令之前从检查点恢复状态信息，但是如果在故障指令和最后发出的指令之间顺序地存储了哪个状态的指令之一，则（ i）在故障指令之后，将所述处理器备份到最靠近的检查点，（ii）将处理器重新执行以恢复状态，以及（iii）将程序计数器递减到故障指令。

2. 发明授权

US5659721A Processor structure and method for checkpointing instructions to maintain precise state 失效
标题翻译：用于检查指令的处理器结构和方法以保持精确状态
公开(公告)号：US5659721A
公开(公告)日：1997-08-19
申请号：US476419
申请日：1995-06-07
申请人： Gene W. Shen , John Szeto , Niteen A. Patkar , Michael C. Shebanow
发明人： Gene W. Shen , John Szeto , Niteen A. Patkar , Michael C. Shebanow
IPC分类号： G06F9/312 , G06F9/38 , G06F11/14 , G06F11/00
CPC分类号： G06F9/3004 , G06F11/1407 , G06F9/30043 , G06F9/3834 , G06F9/3836 , G06F9/384 , G06F9/3842 , G06F9/3855 , G06F9/3857 , G06F9/3863 , G06F9/3865
摘要： Time-out checkpoints are formed based on a predetermined time-out condition or interval since the last checkpoint was formed rather than forming a checkpoint to store current processor state based merely on decoded instruction attributes. Such time-cut conditions may include the number of instructions issued or the number of clock cycles elapsed, for example. Time-out checkpointing limits the maximum number of instructions within a checkpoint boundary and bounds the time period for recovery from an exception condition. The processor can restore time-out based checkpointed state faster than an instruction decode based checkpoint technique in the event of an exception so long as the instruction window size is greater than the maximum number of instructions within a checkpoint boundary, and such method eliminates processor state restoration dependency on instruction window size. Time-out checkpoints may be implemented with conventional. checkpoints, or in a novel logical and physical register rename map checkpointing technique. Timeout checkpoint formation may be used with conventional processor backup techniques as well as with a novel backtracking technique including processor backup and backstepping.
摘要翻译：基于预定的超时条件或时间间隔形成超时检查点，因为上一次检查点形成而不是形成检查点，以便仅仅依赖于解码的指令属性来存储当前的处理器状态。这样的时间切割条件可以包括例如发出的指令的数量或经过的时钟周期的数量。超时检查点限制检查点边界内的最大指令数，并限制从异常情况恢复的时间段。只要指令窗口大小大于检查点边界内的指令的最大数量，处理器可以在发生异常的情况下比基于指令解码的检查点技术更快地恢复基于超时的检查点状态，并且这种方法消除了处理器状态恢复依赖于指令窗口大小。超时检查点可以用常规的方式实现。检查点或新颖的逻辑和物理寄存器重命名映射检查技术。超时检查点的形成可以与常规的处理器备份技术一起使用，还可以使用包括处理器备份和后台步骤的新型回溯技术。

3. 外观设计

USD450543S1 Napkin holder 失效
公开(公告)号：USD450543S1
公开(公告)日：2001-11-20
申请号：US29133543
申请日：2000-12-01
申请人： Pamela S. Hannum , Charles E. Buchanan , John Szeto , William J. Calderwood
设计人： Pamela S. Hannum , Charles E. Buchanan , John Szeto , William J. Calderwood

4. 发明授权

US5644742A Processor structure and method for a time-out checkpoint 失效
标题翻译：用于超时检查点的处理器结构和方法
公开(公告)号：US5644742A
公开(公告)日：1997-07-01
申请号：US473223
申请日：1995-06-07
申请人： Gene W. Shen , John Szeto , Niteen A. Patkar , Michael C. Shebanow
发明人： Gene W. Shen , John Szeto , Niteen A. Patkar , Michael C. Shebanow
IPC分类号： G06F9/312 , G06F9/38 , G06F11/14 , G06F11/00
CPC分类号： G06F9/3004 , G06F11/1407 , G06F9/30043 , G06F9/3834 , G06F9/3836 , G06F9/384 , G06F9/3842 , G06F9/3855 , G06F9/3857 , G06F9/3863 , G06F9/3865
摘要： Time-out checkpoints are formed based on a predetermined time-out condition or interval since the last checkpoint was formed rather than forming a checkpoint to store current processor state based merely on decoded Instruction attributes. Such time-out conditions may include the number of instructions issued or the number of clock cycles elapsed, for example. Time-out checkpointing limits the maximum number of instructions within a checkpoint boundary and bounds the time period for recovery from an exception condition. The processor can restore time-out based checkpointed state faster than an instruction decode based checkpoint technique in the event of an exception so long as the instruction window size is greater than the maximum number of instructions within a checkpoint boundary, end such method eliminates processor state restoration dependency on instruction window size. Time-out checkpoints may be implemented with conventional checkpoints, or in a novel logical and physical register rename map checkpointing technique. Timeout checkpoint formation may be used with conventional processor backup techniques as well as with a novel backtracking technique including processor backup and backstepping.
摘要翻译：基于预定的超时条件或时间间隔形成超时检查点，因为上次检查点形成而不是形成一个检查点，以仅仅基于解码的指令属性来存储当前的处理器状态。例如，这种超时条件可以包括发出的指令的数量或经过的时钟周期的数量。超时检查点限制检查点边界内的最大指令数，并限制从异常情况恢复的时间段。只要指令窗口大小大于检查点边界内的最大指令数，处理器就可以比基于指令解码的检查点技术更快地恢复超时的检查点状态，结束这种方法消除处理器状态恢复依赖于指令窗口大小。超时检查点可以用常规检查点或新颖的逻辑和物理寄存器重命名映射检查点技术来实现。超时检查点的形成可以与常规的处理器备份技术一起使用，还可以使用包括处理器备份和后台步骤的新型回溯技术。

5. 外观设计

USD457780S1 Handle for cheese grater 失效
标题翻译：奶酪磨刀柄
公开(公告)号：USD457780S1
公开(公告)日：2002-05-28
申请号：US29133545
申请日：2000-12-01
申请人： Pamela S. Hannum , Charles E. Buchanan , John Szeto , William J. Calderwood
设计人： Pamela S. Hannum , Charles E. Buchanan , John Szeto , William J. Calderwood

6. 发明授权

US5751985A Processor structure and method for tracking instruction status to maintain precise state 失效
标题翻译：用于跟踪指令状态以保持精确状态的处理器结构和方法
公开(公告)号：US5751985A
公开(公告)日：1998-05-12
申请号：US487801
申请日：1995-06-07
申请人： Gene W. Shen , John Szeto , Niteen A. Patkar , Michael C. Shebanow
发明人： Gene W. Shen , John Szeto , Niteen A. Patkar , Michael C. Shebanow
IPC分类号： G06F9/312 , G06F9/38 , G06F11/14 , G06F9/30
CPC分类号： G06F9/3004 , G06F11/1407 , G06F9/30043 , G06F9/3834 , G06F9/3836 , G06F9/384 , G06F9/3842 , G06F9/3855 , G06F9/3857 , G06F9/3863 , G06F9/3865
摘要： Apparatus and method provide for tracking and maintaining precise state by assigning a unique identification tag to each instruction at the time of issue, associating the tag with a storage location in a first active instruction data structure, updating the data stored in the storage location in response to instruction activity status changes for each instruction, and maintaining a plurality of pointers to the storage locations that move in response to the instruction activity status. Status information includes an activity data item, such as an activity bit, that is set at the time the instruction is issued and cleared when execution completes without error. Pointers are established that point to the last issued instruction, the last committed instruction pointer, and reclaimed instruction pointer. These three pointers are moved forward toward the later issued (newer) instructions along the data structure based on comparisons of the active-bit for each location associated with one instruction in the data structure and predetermined rules. Exceptions or error conditions for any instruction prevent changing the active-bit so that movement of the pointers is controlled and prevented under these error conditions.
摘要翻译：装置和方法通过在发出时向每个指令分配唯一的识别标签来提供跟踪和保持精确状态，将标签与第一活动指令数据结构中的存储位置相关联，响应地更新存储在存储位置中的数据指示每个指令的指令活动状态变化，以及保持指向响应于指令活动状态移动的存储位置的多个指针。状态信息包括活动数据项，例如在指令发出时设置的活动位，并且当执行完成而没有错误时被清除。指针指向最后发出的指令，最后提交的指令指针和回收指令指针。基于与数据结构中的一个指令和预定规则相关联的每个位置的活动位的比较，这三个指针沿着数据结构朝向稍后发布的（较新的）指令向前移动。任何指令的异常或错误条件都会阻止更改有效位，以便在这些错误条件下控制和防止指针的移动。

7. 发明授权

US5673426A Processor structure and method for tracking floating-point exceptions 失效
公开(公告)号：US5673426A
公开(公告)日：1997-09-30
申请号：US484795
申请日：1995-06-07
申请人： Gene W. Shen , John Szeto , Michael C. Shebanow
发明人： Gene W. Shen , John Szeto , Michael C. Shebanow
IPC分类号： G06F9/312 , G06F9/38 , G06F11/14 , G06F7/46
CPC分类号： G06F9/3004 , G06F11/1407 , G06F9/30043 , G06F9/3834 , G06F9/3836 , G06F9/384 , G06F9/3842 , G06F9/3855 , G06F9/3857 , G06F9/3863 , G06F9/3865
摘要： An out of program control order execution data processor that comprises an issue unit, execution means, a floating point exception unit a precise state unit, a floating point status register, and writing means. The issue unit issues instructions in program control order for execution. The issued instructions include floating point instructions and non-floating point instructions. The execution means executes the issued instructions such that at least the floating point instructions may be executed out of program control order by the execution means. The floating point exception unit includes a data storage structure including storage elements. Each issued instruction corresponds to one of the storage elements. Each storage element has a floating point instruction identifying field and a floating point trap type field. The floating point exception unit also includes first logic to write, for each issued instruction, data in the floating point instruction identifying field of the corresponding storage element which indicates whether or not the corresponding issued instruction is a floating point instruction. It further includes second logic to write, for each issued floating point instruction which causes during execution one or more floating point execution exceptions that will result in a corresponding one of a plurality of predefined types of floating point execution traps, data in the floating point trap type field of the corresponding storage element which identifies the one of the predefined types of floating point execution traps that will result. The precise state means retires each issued instruction which does not cause an execution exception during execution and for which all issued instructions preceding it in program control order have been retired. When a first one of the predefined execution exceptions is caused by an issued instruction, the execution means continues execution of issued instructions and the precise state means engages in execution trap sequencing by continuing to retire issued instructions until it encounters an issued instruction that cannot be retired. The issued instruction that cannot be retired being one of (a) the issued instruction that caused the first execution exception, and (b) an issued instruction that was issued earlier than the issued instruction that caused the first execution exception but which caused a second execution exception occurring later than the first execution exception. The floating point status register has a floating point trap type field. The writing means writes data to the floating point trap type field of the floating point status register which identifies the type of floating point execution trap identified by the data in the floating point trap type field of the storage element corresponding to the instruction that cannot be retired when the data in the floating point identifying field of the storage element corresponding to the instruction that cannot be retired indicates that the instruction that cannot be retired is a floating point instruction.

8. 发明授权

US5651124A Processor structure and method for aggressively scheduling long latency instructions including load/store instructions while maintaining precise state 失效
标题翻译：处理器结构和方法，用于在保持精确状态的同时积极调度长延迟指令，包括加载/存储指令
公开(公告)号：US5651124A
公开(公告)日：1997-07-22
申请号：US478025
申请日：1995-06-07
申请人： Gene W. Shen , John Szeto , Niteen A. Patkar , Michael C. Shebanow , Michael A. Simone
发明人： Gene W. Shen , John Szeto , Niteen A. Patkar , Michael C. Shebanow , Michael A. Simone
IPC分类号： G06F9/312 , G06F9/38 , G06F11/14 , G06F11/00
CPC分类号： G06F9/3004 , G06F11/1407 , G06F9/30043 , G06F9/3834 , G06F9/3836 , G06F9/384 , G06F9/3842 , G06F9/3855 , G06F9/3857 , G06F9/3863 , G06F9/3865
摘要： Time-out checkpoints are formed based on a predetermined time-out condition or interval since the last checkpoint was formed rather than forming a checkpoint to store current processor state based merely on decoded instruction attributes. Such time-out conditions may include the number of instructions issued or the number of clock cycles elapsed, for example. Time-out checkpointing limits the maximum number of instructions within a checkpoint boundary and bounds the time period for recovery from an exception condition. The processor can restore time-out based checkpointed state faster than an instruction decode based checkpoint technique in the event of an exception so long as the instruction window size is greater than the maximum number of instructions within a checkpoint boundary, and such method eliminates processor state restoration dependency on instruction window size. Time-out checkpoints may be implemented with conventional checkpoints, or in a novel logical and physical register rename map checkpointing technique. Timeout checkpoint formation may be used with conventional processor backup techniques as well as with a novel backtracking technique including processor backup and backstepping.
摘要翻译：基于预定的超时条件或时间间隔形成超时检查点，因为上一次检查点形成而不是形成检查点，以便仅仅依赖于解码的指令属性来存储当前的处理器状态。例如，这种超时条件可以包括发出的指令的数量或经过的时钟周期的数量。超时检查点限制检查点边界内的最大指令数，并限制从异常情况恢复的时间段。只要指令窗口大小大于检查点边界内的指令的最大数量，处理器可以在发生异常的情况下比基于指令解码的检查点技术更快地恢复基于超时的检查点状态，并且这种方法消除了处理器状态恢复依赖于指令窗口大小。超时检查点可以用常规检查点或新颖的逻辑和物理寄存器重命名映射检查点技术来实现。超时检查点的形成可以与常规的处理器备份技术一起使用，还可以使用包括处理器备份和后台步骤的新型回溯技术。

9. 发明授权

US5649136A Processor structure and method for maintaining and restoring precise state at any instruction boundary 失效
标题翻译：用于在任何指令边界维持和恢复精确状态的处理器结构和方法
公开(公告)号：US5649136A
公开(公告)日：1997-07-15
申请号：US483958
申请日：1995-06-07
申请人： Gene W. Shen , John Szeto , Niteen A. Patkar , Michael C. Shebanow
发明人： Gene W. Shen , John Szeto , Niteen A. Patkar , Michael C. Shebanow
IPC分类号： G06F9/312 , G06F9/38 , G06F11/14 , G06F11/00
CPC分类号： G06F9/3004 , G06F11/1407 , G06F9/30043 , G06F9/3834 , G06F9/3836 , G06F9/384 , G06F9/3842 , G06F9/3855 , G06F9/3857 , G06F9/3863 , G06F9/3865
摘要： A high-performance processor is disclosed with structure and methods for: (1) aggressively scheduling long latency instructions including load/store instructions while maintaining precise state; (2) maintaining and restoring precise state at any instruction boundary; (3) tracking instruction status to maintain precise state; (4) checkpointing instructions to maintain precise state; (5) creating, maintaining, and using a time-out checkpoint; (6) tracking floating-point exceptions; (7) creating, maintaining, and using a watchpoint for plural, simultaneous, unresolved-branch evaluation; and (9) increasing processor throughput while maintaining precise state.
摘要翻译：公开了一种具有以下结构和方法的高性能处理器：（1）在保持精确状态的同时积极调度包括加载/存储指令的长延迟指令; （2）在任何指令边界保持和恢复精确状态; （3）跟踪指令状态以保持精确状态; （4）检查点指令保持精确状态; （5）创建，维护和使用超时检查点; （6）跟踪浮点异常; （7）创建，维护和使用观察点进行复数，同时，未解决的分支评估; 和（9）提高处理器吞吐量同时保持精确的状态。

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