专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07315055B2 Silicon-oxide-nitride-oxide-silicon (SONOS) memory devices having recessed channels 失效
标题翻译：具有凹陷通道的氧化硅 - 氧化物 - 氮化物 - 氧化物 - 硅（SONOS）存储器件
公开(公告)号：US07315055B2
公开(公告)日：2008-01-01
申请号：US10999306
申请日：2004-11-30
申请人： Myoung-kwan Cho , Sung-hoi Hur , Eun-suk Cho
发明人： Myoung-kwan Cho , Sung-hoi Hur , Eun-suk Cho
IPC分类号： H01L29/76
CPC分类号： H01L27/11568 , H01L27/115 , H01L29/7923
摘要： Unit cells of silicon-oxide-nitride-oxide-silicon (SONOS) memory devices are provided. The unit cells include an integrated circuit substrate and a SONOS memory cell on the integrated circuit substrate. The SONOS memory cell includes a source region, a drain region and a gate contact. The integrated circuit substrate defines a trench between the source and drain regions and the gate contact is provided in the trench. A floor of the trench extends further into the integrated circuit substrate than lower surfaces of the source and drain regions. Related methods of fabricating SONOS memory cells are also provided.
摘要翻译：提供了氧化硅 - 氮化物 - 氧化物 - 硅（SONOS）存储器件的单位电池。单元电池包括集成电路基板和集成电路基板上的SONOS存储单元。 SONOS存储单元包括源极区，漏极区和栅极接触。集成电路基板在源极和漏极区域之间限定沟槽，并且在沟槽中设置栅极接触。沟槽的底部比源极和漏极区域的下表面进一步延伸到集成电路衬底内。还提供了制造SONOS存储单元的相关方法。

2. 发明申请

US20060141715A1 Integrated circuit devices having contact holes exposing gate electrodes in active regions and methods of fabricating the same 有权
标题翻译：具有暴露有源区域中的栅电极的接触孔的集成电路器件及其制造方法
公开(公告)号：US20060141715A1
公开(公告)日：2006-06-29
申请号：US11359840
申请日：2006-02-22
申请人： Jeung-Hwan Park , Myoung-Kwan Cho
发明人： Jeung-Hwan Park , Myoung-Kwan Cho
IPC分类号： H01L21/336
CPC分类号： H01L21/823437 , H01L21/823475 , H01L21/823481
摘要： Integrated circuit devices are provided including an integrated circuit substrate and first, second and third spaced apart insulating regions in the integrated circuit substrate that define first and second active regions. A first gate electrode is provided on the first active region. The first gate electrode has a first portion on the first active region that extends onto the first insulating region and a second portion at an end of the first portion on the first insulating region. A second gate electrode is provided on the second active region. An insulating layer is provided on the first, second and third active regions defining a first gate contact hole that exposes at least a portion of the second portion of the first gate electrode. The first gate electrode is free of a gate contact hole on the first portion of the first gate electrode. A second gate contact hole is provided on the second active region that exposes at least a portion of the second gate electrode. Related methods of fabricating integrated circuit devices are also provided.
摘要翻译：提供集成电路器件，其包括集成电路衬底以及集成电路衬底中的第一，第二和第三间隔绝缘区域，其限定第一和第二有源区域。第一栅电极设置在第一有源区上。第一栅电极在第一有源区上具有延伸到第一绝缘区上的第一部分和位于第一绝缘区上的第一部分末端的第二部分。第二栅电极设置在第二有源区上。绝缘层设置在第一，第二和第三有源区上，限定了暴露第一栅电极的第二部分的至少一部分的第一栅极接触孔。第一栅电极在第一栅电极的第一部分上没有栅极接触孔。在第二有源区上提供第二栅极接触孔，其暴露第二栅电极的至少一部分。还提供了制造集成电路器件的相关方法。

3. 发明授权

US06544845B2 Methods of fabricating nonvolatile memory devices including bird's beak oxide 失效
标题翻译：制造包括鸟喙氧化物的非易失性存储装置的方法
公开(公告)号：US06544845B2
公开(公告)日：2003-04-08
申请号：US09854790
申请日：2001-05-14
申请人： Jong-weon Yoo , Myoung-kwan Cho , Jin-woo Kim
发明人： Jong-weon Yoo , Myoung-kwan Cho , Jin-woo Kim
IPC分类号： H01L21336
CPC分类号： H01L27/105 , H01L27/115 , H01L27/11526 , H01L27/11543 , H01L29/7885
摘要： A nonvolatile memory device which suppress a drain coupling by minimizing an overlap capacitance between a floating gate and a drain. The nonvolatile memory device includes a cell array region in which a plurality of memory cells are two-dimensionally arranged and a peripheral circuit region for driving the memory cells. The memory cells comprise a first conductivity type semiconductor substrate, second conductivity type source and drain regions separated from each other with a channel region therebetween on the main surface of the semiconductor substrate, a gate oxide film formed on the upper portion of the channel region, a floating gate formed on the gate oxide film, an interlayer dielectric film formed on the upper portion of the floating gate, a control gate formed on the interlayer dielectric film, and a bird's beak area formed between the source/drain regions and the floating gate having greater thickness than the gate oxide film.
摘要翻译：一种非易失性存储器件，其通过使浮置栅极和漏极之间的重叠电容最小化来抑制漏极耦合。非易失性存储器件包括其中多个存储单元被二维布置的单元阵列区域和用于驱动存储单元的外围电路区域。存储单元包括第一导电型半导体衬底，在半导体衬底的主表面上彼此分离的沟道区域的第二导电型源极和漏极区域，形成在沟道区域的上部的栅氧化膜，形成在栅极氧化膜上的浮动栅极，形成在浮置栅极的上部的层间电介质膜，形成在层间绝缘膜上的控制栅极和形成在源极/漏极区域与浮置栅极之间的鸟嘴区域具有比栅极氧化膜更大的厚度。

4. 发明授权

US5912488A Stacked-gate flash EEPROM memory devices having mid-channel injection characteristics for high speed programming 失效
标题翻译：具有用于高速编程的中途通道注入特性的堆叠式快闪EEPROM存储器件
公开(公告)号：US5912488A
公开(公告)日：1999-06-15
申请号：US881444
申请日：1997-06-24
申请人： Dae Mann Kim , Myoung-kwan Cho
发明人： Dae Mann Kim , Myoung-kwan Cho
IPC分类号： H01L21/8247 , G11C16/04 , H01L21/336 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L29/66825 , G11C16/0416 , H01L29/7885
摘要： Flash EEPROM memory devices having mid-channel injection characteristics include a substrate having source and drain regions of first conductivity type therein extending adjacent a surface thereof. A stacked-gate electrode is also provided on the surface, between the source and drain regions. To provide improved mid-channel injection characteristics during programming, a preferred semiconductor channel region is provided in the substrate at a location extending opposite the stacked-gate electrode. This channel region comprises a first "source-side" region of second conductivity type (e.g., P+) and a second "drain-side" region of predetermined conductivity type (e.g., P-, N-). The second region has a lower first conductivity type dopant concentration therein than the drain region and a lower second conductivity type dopant concentration therein than said first region, and more preferably has a lower second conductivity type dopant concentration therein than said substrate. During programming, this EEPROM unit cell provides efficient mid-channel injection at high rates and at relatively low voltage levels and avoids many of the limitations associated with conventional stacked-gate EEPROM devices which typically provide less efficient drain-side injection and require relatively high voltage levels during programming. In particular, mid-channel injection of hot electrons from the channel region to the floating gate (within the stacked-gate electrode) is promoted by tailoring the conductivity of the channel region so that pinch-off occurs at a midpoint in the channel region during programming operations.
摘要翻译：具有中等通道注入特性的闪存EEPROM存储器件包括具有第一导电类型的源区和漏区的衬底，其中邻近其表面延伸。在栅极和漏极区域之间的表面上还设置堆叠栅电极。为了在编程期间提供改进的中间通道注入特性，在衬底中在与堆叠栅电极相对的位置处提供优选的半导体沟道区。该沟道区域包括第二导电类型（例如，P +）的第一“源极侧”区域和预定导电类型（例如，P，N-）的第二“漏极侧”区域。所述第二区域比所述第一区域具有比所述漏极区域低的第一导电型掺杂剂浓度和比所述第一区域低的第二导电型掺杂剂浓度，并且更优选地具有比所述衬底更低的第二导电类型掺杂剂浓度。在编程期间，该EEPROM单元提供了高速率和相对较低电压电平的有效的中间通道注入，并避免了与常规堆叠栅极EEPROM器件相关的许多限制，这些限制通常提供较不有效的漏极侧注入并且需要相对较高的电压编程期间的水平。特别地，通过调整通道区域的导电性来促进从通道区域到浮置栅极（堆叠栅极电极内）的热通道的中间通道注入，使得在沟道区域的中点发生夹断编程操作。

5. 发明授权

US5789293A Nonvolatile memory device and manufacturing method thereof 失效
标题翻译：非易失存储器件及其制造方法
公开(公告)号：US5789293A
公开(公告)日：1998-08-04
申请号：US757247
申请日：1996-11-27
申请人： Myoung-kwan Cho , Keon-soo Kim
发明人： Myoung-kwan Cho , Keon-soo Kim
IPC分类号： H01L21/8247 , H01L27/105 , H01L27/115 , H01L29/788 , H01L29/792 , H01L21/336
CPC分类号： H01L27/105 , H01L27/11526 , H01L27/11536
摘要： A nonvolatile memory device and a manufacturing method thereof is disclosed. The device includes a gate electrode of a memory cell arranged in a memory cell region and having a floating gate electrode formed of a first conductive layer, an insulating film formed on the floating gate electrode and a control gate electrode formed of a second conductive layer on the insulating film; a gate electrode formed of a second conductive layer and arranged in a peripheral circuit region surrounding the memory cell region; a resistance device formed of the first conductive layer arranged in a boundary region between the memory cell region and the peripheral circuit region and/or the peripheral circuit region; an insulating film formed on a part of a surface of the resistance device; and a capping layer formed of the second conductive layer on the insulating film. Thus, generation of a stringer can be prevented so that malfunction of a device can be prevented.
摘要翻译：公开了一种非易失性存储器件及其制造方法。该器件包括布置在存储单元区域中并具有由第一导电层形成的浮置栅极的存储单元的栅电极，形成在浮栅上的绝缘膜和由第二导电层形成的控制栅电极绝缘膜; 栅电极，由第二导电层形成，并布置在围绕存储单元区域的外围电路区域中; 布置在存储单元区域和外围电路区域和/或外围电路区域之间的边界区域中的第一导电层形成的电阻装置; 形成在所述电阻装置的表面的一部分上的绝缘膜; 以及由绝缘膜上的第二导电层形成的覆盖层。因此，可以防止产生桁条，从而可以防止装置的故障。

6. 发明授权

US5514889A Non-volatile semiconductor memory device and method for manufacturing the same 失效
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US5514889A
公开(公告)日：1996-05-07
申请号：US107901
申请日：1993-08-18
申请人： Myoung-kwan Cho , Jeoug-hyuk Choi
发明人： Myoung-kwan Cho , Jeoug-hyuk Choi
IPC分类号： H01L21/8247 , H01L27/105 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11546
摘要： An EEPROM device in which a high voltage is applied to the chip during the memory cell operation and a method for the manufacturing the same are disclosed. On a P-type semiconductor substrate, a first N-well is formed in a surface portion of the substrate in the cell array region and a second N-well is formed in a first surface of the substrate in the peripheral circuit region. An EEPROM memory cell is formed on the first P-well and a first NMOS transistor is formed on the second P-well. Also, a second NMOS transistor is formed on a second surface portion of the semiconductor substrate in the peripheral circuit 10 region and a PMOS transistor is formed on the second N-well. The impurity concentrations of the first and second P-wells are controlled in accordance with the characteristic of the MOS transistors to be formed. Further, a second NMOS transistor having a resistance against a high voltage is directly formed on the P-type substrate. Thus, the electric characteristic of the EEPROM device is enhanced.
摘要翻译：公开了一种其中在存储单元操作期间向芯片施加高电压的EEPROM器件及其制造方法。在P型半导体基板上，在单元阵列区域的基板的表面部分形成第一N阱，在外围电路区域的基板的第一表面形成第二N阱。在第一P阱上形成EEPROM存储单元，在第二P阱上形成第一NMOS晶体管。此外，第二NMOS晶体管形成在外围电路10区域中的半导体衬底的第二表面部分上，并且PMOS晶体管形成在第二N阱上。根据要形成的MOS晶体管的特性来控制第一和第二P阱的杂质浓度。此外，在P型衬底上直接形成具有高电压电阻的第二NMOS晶体管。因此，提高了EEPROM器件的电气特性。

7. 发明授权

US07320909B2 Methods of fabricating integrated circuit devices having contact holes exposing gate electrodes in active regions 有权
标题翻译：制造具有接触孔的集成电路器件的方法，所述接触孔在有源区域中暴露栅电极
公开(公告)号：US07320909B2
公开(公告)日：2008-01-22
申请号：US11359840
申请日：2006-02-22
申请人： Jeung-Hwan Park , Myoung-Kwan Cho
发明人： Jeung-Hwan Park , Myoung-Kwan Cho
IPC分类号： H01L21/337
CPC分类号： H01L21/823437 , H01L21/823475 , H01L21/823481
摘要： Integrated circuit devices are provided including an integrated circuit substrate and first, second and third spaced apart insulating regions in the integrated circuit substrate that define first and second active regions. A first gate electrode is provided on the first active region. The first gate electrode has a first portion on the first active region that extends onto the first insulating region and a second portion at an end of the first portion on the first insulating region. A second gate electrode is provided on the second active region. An insulating layer is provided on the first, second and third active regions defining a first gate contact hole that exposes at least a portion of the second portion of the first gate electrode. The first gate electrode is free of a gate contact hole on the first portion of the first gate electrode. A second gate contact hole is provided on the second active region that exposes at least a portion of the second gate electrode. Related methods of fabricating integrated circuit devices are also provided.
摘要翻译：提供集成电路器件，其包括集成电路衬底以及集成电路衬底中的第一，第二和第三间隔绝缘区域，其限定第一和第二有源区域。第一栅电极设置在第一有源区上。第一栅电极在第一有源区上具有延伸到第一绝缘区上的第一部分和位于第一绝缘区上的第一部分末端的第二部分。第二栅电极设置在第二有源区上。绝缘层设置在第一，第二和第三有源区上，限定了暴露第一栅电极的第二部分的至少一部分的第一栅极接触孔。第一栅电极在第一栅电极的第一部分上没有栅极接触孔。在第二有源区上提供第二栅极接触孔，其暴露第二栅电极的至少一部分。还提供了制造集成电路器件的相关方法。

8. 发明授权

US6144064A Split-gate EEPROM device having floating gate with double polysilicon layer 有权
标题翻译：具有双层多晶硅层的浮动栅极的分离栅极EEPROM器件
公开(公告)号：US6144064A
公开(公告)日：2000-11-07
申请号：US275054
申请日：1999-03-23
申请人： Myoung-Kwan Cho , Keon-Soo Kim
发明人： Myoung-Kwan Cho , Keon-Soo Kim
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788
CPC分类号： H01L27/115 , H01L27/11521
摘要： Methods of forming EEPROM memory cells having uniformly thick tunneling oxide layers include the steps of forming a preliminary field oxide isolation region of first thickness at a face of a semiconductor substrate of first conductivity type (e.g., P-type) and then forming a tunneling oxide layer on the face, adjacent the preliminary field oxide isolation region. The memory cell's drain region dopants are then implanted through the preliminary field oxide isolation region and into the substrate to form a preliminary drain region of second conductivity type. The preliminary field oxide isolation region is then grown to a second thickness greater than the first thickness by oxidizing the portion of the substrate containing the implanted dopants, to form a final field oxide isolation region which may have a thickness of about 2000 .ANG.. To prevent unwanted growth of the tunneling oxide layer, a silicon nitride layer is preferably patterned on the tunneling oxide layer and used as an oxidation mask during the step of growing the preliminary field oxide isolation region to a second thickness. The silicon nitride mask is then removed and then a floating gate electrode and insulated control electrode are patterned on the tunneling oxide layer and channel region to complete the memory cell.
摘要翻译：形成具有均匀厚的隧道氧化物层的EEPROM存储单元的方法包括以下步骤：在第一导电类型的半导体衬底（例如，P型）的表面上形成第一厚度的预备场氧化物隔离区，然后形成隧道氧化物层在面上，毗邻初步场氧化物隔离区。然后通过预备场氧化物隔离区域将衬底中的存储单元的漏极区掺杂物注入到衬底中以形成第二导电类型的初级漏区。然后通过氧化含有注入的掺杂剂的衬底的部分，将初始场氧化物隔离区域生长到大于第一厚度的第二厚度，以形成最终的场氧化物隔离区域，其可以具有约2000的厚度。为了防止隧道氧化物层的不期望的生长，优选在隧道氧化物层上图案化氮化硅层，并且在将预备场氧化物隔离区域生长至第二厚度的步骤期间用作氧化掩模。然后去除氮化硅掩模，然后在隧道氧化物层和沟道区上图案化浮栅电极和绝缘控制电极，以完成存储单元。

9. 发明授权

US5712178A Non-volatile semiconductor memory device and method for manufacturing the same 失效
公开(公告)号：US5712178A
公开(公告)日：1998-01-27
申请号：US477323
申请日：1995-06-07
申请人： Myoung-kwan Cho , Jeong-hyuk Choi
发明人： Myoung-kwan Cho , Jeong-hyuk Choi
IPC分类号： H01L21/8247 , H01L27/105 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11546
摘要： An EEPROM device in which a high voltage is applied to the chip during the memory cell operation and a method for the manufacturing the same are disclosed. On a P-type semiconductor substrate, a first N-well is formed in a surface portion of the substrate in the cell array region and a second N-well is formed in a first surface of the substrate in the peripheral circuit region. An EEPROM memory cell is formed on the first P-well and a first NMOS transistor is formed on the second P-well. Also, a second NMOS transistor is formed on a second surface portion of the semiconductor substrate in the peripheral circuit 10 region and a PMOS transistor is formed on the second N-well. The impurity concentrations of the first and second P-wells are controlled in accordance with the characteristic of the MOS transistors to be formed. Further, a second NMOS transistor having a resistance against a high voltage is directly formed on the P-type substrate. Thus, the electric characteristic of the EEPROM device is enhanced.

10. 发明授权

US07547943B2 Non-volatile memory devices that include a selection transistor having a recessed channel and methods of fabricating the same 失效
标题翻译：包括具有凹陷通道的选择晶体管的非易失性存储器件及其制造方法
公开(公告)号：US07547943B2
公开(公告)日：2009-06-16
申请号：US11022181
申请日：2004-12-22
申请人： Myoung-Kwan Cho , Eun-Suk Cho , Wook-Hyun Kwon
发明人： Myoung-Kwan Cho , Eun-Suk Cho , Wook-Hyun Kwon
IPC分类号： H01L29/94
CPC分类号： H01L27/11521 , G11C16/0483 , H01L27/115 , H01L27/11524 , H01L29/66621 , H01L29/66825 , H01L29/7834 , H01L29/7881
摘要： A NAND-type non-volatile memory device includes a substrate and a device isolation layer disposed on the substrate to define an active region. First and second selection transistors are disposed in the active region, such that each of the first and second selection transistors has a recessed channel. A plurality of memory transistors is disposed in the active region between the first selection transistor and the second selection transistor.
摘要翻译： NAND型非易失性存储器件包括衬底和设置在衬底上以限定有源区的器件隔离层。第一和第二选择晶体管设置在有源区域中，使得第一和第二选择晶体管中的每一个具有凹陷通道。多个存储晶体管设置在第一选择晶体管和第二选择晶体管之间的有源区中。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式