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1. 发明授权

US5514889A Non-volatile semiconductor memory device and method for manufacturing the same 失效
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US5514889A
公开(公告)日：1996-05-07
申请号：US107901
申请日：1993-08-18
申请人： Myoung-kwan Cho , Jeoug-hyuk Choi
发明人： Myoung-kwan Cho , Jeoug-hyuk Choi
IPC分类号： H01L21/8247 , H01L27/105 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11546
摘要： An EEPROM device in which a high voltage is applied to the chip during the memory cell operation and a method for the manufacturing the same are disclosed. On a P-type semiconductor substrate, a first N-well is formed in a surface portion of the substrate in the cell array region and a second N-well is formed in a first surface of the substrate in the peripheral circuit region. An EEPROM memory cell is formed on the first P-well and a first NMOS transistor is formed on the second P-well. Also, a second NMOS transistor is formed on a second surface portion of the semiconductor substrate in the peripheral circuit 10 region and a PMOS transistor is formed on the second N-well. The impurity concentrations of the first and second P-wells are controlled in accordance with the characteristic of the MOS transistors to be formed. Further, a second NMOS transistor having a resistance against a high voltage is directly formed on the P-type substrate. Thus, the electric characteristic of the EEPROM device is enhanced.
摘要翻译：公开了一种其中在存储单元操作期间向芯片施加高电压的EEPROM器件及其制造方法。在P型半导体基板上，在单元阵列区域的基板的表面部分形成第一N阱，在外围电路区域的基板的第一表面形成第二N阱。在第一P阱上形成EEPROM存储单元，在第二P阱上形成第一NMOS晶体管。此外，第二NMOS晶体管形成在外围电路10区域中的半导体衬底的第二表面部分上，并且PMOS晶体管形成在第二N阱上。根据要形成的MOS晶体管的特性来控制第一和第二P阱的杂质浓度。此外，在P型衬底上直接形成具有高电压电阻的第二NMOS晶体管。因此，提高了EEPROM器件的电气特性。

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