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1. 发明授权

US07320909B2 Methods of fabricating integrated circuit devices having contact holes exposing gate electrodes in active regions 有权
标题翻译：制造具有接触孔的集成电路器件的方法，所述接触孔在有源区域中暴露栅电极
公开(公告)号：US07320909B2
公开(公告)日：2008-01-22
申请号：US11359840
申请日：2006-02-22
申请人： Jeung-Hwan Park , Myoung-Kwan Cho
发明人： Jeung-Hwan Park , Myoung-Kwan Cho
IPC分类号： H01L21/337
CPC分类号： H01L21/823437 , H01L21/823475 , H01L21/823481
摘要： Integrated circuit devices are provided including an integrated circuit substrate and first, second and third spaced apart insulating regions in the integrated circuit substrate that define first and second active regions. A first gate electrode is provided on the first active region. The first gate electrode has a first portion on the first active region that extends onto the first insulating region and a second portion at an end of the first portion on the first insulating region. A second gate electrode is provided on the second active region. An insulating layer is provided on the first, second and third active regions defining a first gate contact hole that exposes at least a portion of the second portion of the first gate electrode. The first gate electrode is free of a gate contact hole on the first portion of the first gate electrode. A second gate contact hole is provided on the second active region that exposes at least a portion of the second gate electrode. Related methods of fabricating integrated circuit devices are also provided.
摘要翻译：提供集成电路器件，其包括集成电路衬底以及集成电路衬底中的第一，第二和第三间隔绝缘区域，其限定第一和第二有源区域。第一栅电极设置在第一有源区上。第一栅电极在第一有源区上具有延伸到第一绝缘区上的第一部分和位于第一绝缘区上的第一部分末端的第二部分。第二栅电极设置在第二有源区上。绝缘层设置在第一，第二和第三有源区上，限定了暴露第一栅电极的第二部分的至少一部分的第一栅极接触孔。第一栅电极在第一栅电极的第一部分上没有栅极接触孔。在第二有源区上提供第二栅极接触孔，其暴露第二栅电极的至少一部分。还提供了制造集成电路器件的相关方法。

2. 发明申请

US20060141715A1 Integrated circuit devices having contact holes exposing gate electrodes in active regions and methods of fabricating the same 有权
标题翻译：具有暴露有源区域中的栅电极的接触孔的集成电路器件及其制造方法
公开(公告)号：US20060141715A1
公开(公告)日：2006-06-29
申请号：US11359840
申请日：2006-02-22
申请人： Jeung-Hwan Park , Myoung-Kwan Cho
发明人： Jeung-Hwan Park , Myoung-Kwan Cho
IPC分类号： H01L21/336
CPC分类号： H01L21/823437 , H01L21/823475 , H01L21/823481
摘要： Integrated circuit devices are provided including an integrated circuit substrate and first, second and third spaced apart insulating regions in the integrated circuit substrate that define first and second active regions. A first gate electrode is provided on the first active region. The first gate electrode has a first portion on the first active region that extends onto the first insulating region and a second portion at an end of the first portion on the first insulating region. A second gate electrode is provided on the second active region. An insulating layer is provided on the first, second and third active regions defining a first gate contact hole that exposes at least a portion of the second portion of the first gate electrode. The first gate electrode is free of a gate contact hole on the first portion of the first gate electrode. A second gate contact hole is provided on the second active region that exposes at least a portion of the second gate electrode. Related methods of fabricating integrated circuit devices are also provided.
摘要翻译：提供集成电路器件，其包括集成电路衬底以及集成电路衬底中的第一，第二和第三间隔绝缘区域，其限定第一和第二有源区域。第一栅电极设置在第一有源区上。第一栅电极在第一有源区上具有延伸到第一绝缘区上的第一部分和位于第一绝缘区上的第一部分末端的第二部分。第二栅电极设置在第二有源区上。绝缘层设置在第一，第二和第三有源区上，限定了暴露第一栅电极的第二部分的至少一部分的第一栅极接触孔。第一栅电极在第一栅电极的第一部分上没有栅极接触孔。在第二有源区上提供第二栅极接触孔，其暴露第二栅电极的至少一部分。还提供了制造集成电路器件的相关方法。

3. 发明授权

US07034365B2 Integrated circuit devices having contact holes exposing gate electrodes in active regions 有权
标题翻译：具有接触孔的集成电路器件暴露有源区中的栅电极
公开(公告)号：US07034365B2
公开(公告)日：2006-04-25
申请号：US10769649
申请日：2004-01-30
申请人： Jeung-Hwan Park , Myoung-Kwan Cho
发明人： Jeung-Hwan Park , Myoung-Kwan Cho
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L21/823437 , H01L21/823475 , H01L21/823481
摘要： Integrated circuit devices are provided including an integrated circuit substrate and first, second and third spaced apart insulating regions in the integrated circuit substrate that define first and second active regions. A first gate electrode is provided on the first active region. The first gate electrode has a first portion on the first active region that extends onto the first insulating region and a second portion at an end of the first portion on the first insulating region. A second gate electrode is provided on the second active region. An insulating layer is provided on the first, second and third active regions defining a first gate contact hole that exposes at least a portion of the second portion of the first gate electrode. The first gate electrode is free of a gate contact hole on the first portion of the first gate electrode. A second gate contact hole is provided on the second active region that exposes at least a portion of the second gate electrode. Related methods of fabricating integrated circuit devices are also provided.
摘要翻译：提供集成电路器件，其包括集成电路衬底以及集成电路衬底中的第一，第二和第三间隔绝缘区域，其限定第一和第二有源区域。第一栅电极设置在第一有源区上。第一栅电极在第一有源区上具有延伸到第一绝缘区上的第一部分和位于第一绝缘区上的第一部分末端的第二部分。第二栅电极设置在第二有源区上。绝缘层设置在第一，第二和第三有源区上，限定了暴露第一栅电极的第二部分的至少一部分的第一栅极接触孔。第一栅电极在第一栅电极的第一部分上没有栅极接触孔。在第二有源区上提供第二栅极接触孔，其暴露第二栅电极的至少一部分。还提供了制造集成电路器件的相关方法。

4. 发明申请

US20080093655A1 SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME 审中-公开
标题翻译：半导体器件及其形成方法
公开(公告)号：US20080093655A1
公开(公告)日：2008-04-24
申请号：US11986511
申请日：2007-11-21
申请人： Wook-Hyoung Lee , Jeung-Hwan Park , Ki-Yeol Byun
发明人： Wook-Hyoung Lee , Jeung-Hwan Park , Ki-Yeol Byun
IPC分类号： H01L29/788 , H01L21/283
CPC分类号： H01L21/76229 , H01L27/105 , H01L27/11526 , H01L27/11536
摘要： Provided are a semiconductor device and a method of forming the semiconductor device. The semiconductor substrate includes a cell region, a peripheral region, and a boundary region between the cell region and the peripheral region; a plurality of device isolation patterns defining the cell region, the peripheral region, and the boundary region; a plurality of floating gate patterns on the cell region; a gate pattern on the peripheral region; and a residual conductive pattern on the device isolation patterns defining the boundary region, wherein the residual conductive pattern is separated from an outermost one of the floating gate patterns by a distance from about 0.5 times to about 2 times a distance at which the floating gate patterns repeat.
摘要翻译：提供半导体器件和形成半导体器件的方法。半导体衬底包括单元区域，周边区域和单元区域与外围区域之间的边界区域; 限定所述单元区域，所述外围区域和所述边界区域的多个器件隔离图案; 在所述单元区域上的多个浮置栅极图案; 外围区域上的栅极图案; 以及限定所述边界区域的器件隔离图案上的残留导电图案，其中所述残留导电图案与所述浮动栅极图案中的最外面的所述浮动栅极图案分开距离所述浮动栅极图案的距离的约0.5倍至约2倍的距离重复。

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