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1. 发明授权

US07547943B2 Non-volatile memory devices that include a selection transistor having a recessed channel and methods of fabricating the same 失效
标题翻译：包括具有凹陷通道的选择晶体管的非易失性存储器件及其制造方法
公开(公告)号：US07547943B2
公开(公告)日：2009-06-16
申请号：US11022181
申请日：2004-12-22
申请人： Myoung-Kwan Cho , Eun-Suk Cho , Wook-Hyun Kwon
发明人： Myoung-Kwan Cho , Eun-Suk Cho , Wook-Hyun Kwon
IPC分类号： H01L29/94
CPC分类号： H01L27/11521 , G11C16/0483 , H01L27/115 , H01L27/11524 , H01L29/66621 , H01L29/66825 , H01L29/7834 , H01L29/7881
摘要： A NAND-type non-volatile memory device includes a substrate and a device isolation layer disposed on the substrate to define an active region. First and second selection transistors are disposed in the active region, such that each of the first and second selection transistors has a recessed channel. A plurality of memory transistors is disposed in the active region between the first selection transistor and the second selection transistor.
摘要翻译： NAND型非易失性存储器件包括衬底和设置在衬底上以限定有源区的器件隔离层。第一和第二选择晶体管设置在有源区域中，使得第一和第二选择晶体管中的每一个具有凹陷通道。多个存储晶体管设置在第一选择晶体管和第二选择晶体管之间的有源区中。

2. 发明申请

US20060023558A1 Non-volatile memory devices that include a selection transistor having a recessed channel and methods of fabricating the same 失效
公开(公告)号：US20060023558A1
公开(公告)日：2006-02-02
申请号：US11022181
申请日：2004-12-22
申请人： Myoung-Kwan Cho , Eun-Suk Cho , Wook-Hyun Kwon
发明人： Myoung-Kwan Cho , Eun-Suk Cho , Wook-Hyun Kwon
IPC分类号： G11C8/00
CPC分类号： H01L27/11521 , G11C16/0483 , H01L27/115 , H01L27/11524 , H01L29/66621 , H01L29/66825 , H01L29/7834 , H01L29/7881
摘要： A NAND-type non-volatile memory device includes a substrate and a device isolation layer disposed on the substrate to define an active region. First and second selection transistors are disposed in the active region, such that each of the first and second selection transistors has a recessed channel. A plurality of memory transistors is disposed in the active region between the first selection transistor and the second selection transistor.

3. 发明申请

US20060141715A1 Integrated circuit devices having contact holes exposing gate electrodes in active regions and methods of fabricating the same 有权
标题翻译：具有暴露有源区域中的栅电极的接触孔的集成电路器件及其制造方法
公开(公告)号：US20060141715A1
公开(公告)日：2006-06-29
申请号：US11359840
申请日：2006-02-22
申请人： Jeung-Hwan Park , Myoung-Kwan Cho
发明人： Jeung-Hwan Park , Myoung-Kwan Cho
IPC分类号： H01L21/336
CPC分类号： H01L21/823437 , H01L21/823475 , H01L21/823481
摘要： Integrated circuit devices are provided including an integrated circuit substrate and first, second and third spaced apart insulating regions in the integrated circuit substrate that define first and second active regions. A first gate electrode is provided on the first active region. The first gate electrode has a first portion on the first active region that extends onto the first insulating region and a second portion at an end of the first portion on the first insulating region. A second gate electrode is provided on the second active region. An insulating layer is provided on the first, second and third active regions defining a first gate contact hole that exposes at least a portion of the second portion of the first gate electrode. The first gate electrode is free of a gate contact hole on the first portion of the first gate electrode. A second gate contact hole is provided on the second active region that exposes at least a portion of the second gate electrode. Related methods of fabricating integrated circuit devices are also provided.
摘要翻译：提供集成电路器件，其包括集成电路衬底以及集成电路衬底中的第一，第二和第三间隔绝缘区域，其限定第一和第二有源区域。第一栅电极设置在第一有源区上。第一栅电极在第一有源区上具有延伸到第一绝缘区上的第一部分和位于第一绝缘区上的第一部分末端的第二部分。第二栅电极设置在第二有源区上。绝缘层设置在第一，第二和第三有源区上，限定了暴露第一栅电极的第二部分的至少一部分的第一栅极接触孔。第一栅电极在第一栅电极的第一部分上没有栅极接触孔。在第二有源区上提供第二栅极接触孔，其暴露第二栅电极的至少一部分。还提供了制造集成电路器件的相关方法。

4. 发明授权

US07034365B2 Integrated circuit devices having contact holes exposing gate electrodes in active regions 有权
标题翻译：具有接触孔的集成电路器件暴露有源区中的栅电极
公开(公告)号：US07034365B2
公开(公告)日：2006-04-25
申请号：US10769649
申请日：2004-01-30
申请人： Jeung-Hwan Park , Myoung-Kwan Cho
发明人： Jeung-Hwan Park , Myoung-Kwan Cho
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L21/823437 , H01L21/823475 , H01L21/823481
摘要： Integrated circuit devices are provided including an integrated circuit substrate and first, second and third spaced apart insulating regions in the integrated circuit substrate that define first and second active regions. A first gate electrode is provided on the first active region. The first gate electrode has a first portion on the first active region that extends onto the first insulating region and a second portion at an end of the first portion on the first insulating region. A second gate electrode is provided on the second active region. An insulating layer is provided on the first, second and third active regions defining a first gate contact hole that exposes at least a portion of the second portion of the first gate electrode. The first gate electrode is free of a gate contact hole on the first portion of the first gate electrode. A second gate contact hole is provided on the second active region that exposes at least a portion of the second gate electrode. Related methods of fabricating integrated circuit devices are also provided.
摘要翻译：提供集成电路器件，其包括集成电路衬底以及集成电路衬底中的第一，第二和第三间隔绝缘区域，其限定第一和第二有源区域。第一栅电极设置在第一有源区上。第一栅电极在第一有源区上具有延伸到第一绝缘区上的第一部分和位于第一绝缘区上的第一部分末端的第二部分。第二栅电极设置在第二有源区上。绝缘层设置在第一，第二和第三有源区上，限定了暴露第一栅电极的第二部分的至少一部分的第一栅极接触孔。第一栅电极在第一栅电极的第一部分上没有栅极接触孔。在第二有源区上提供第二栅极接触孔，其暴露第二栅电极的至少一部分。还提供了制造集成电路器件的相关方法。

5. 发明授权

US07320909B2 Methods of fabricating integrated circuit devices having contact holes exposing gate electrodes in active regions 有权
标题翻译：制造具有接触孔的集成电路器件的方法，所述接触孔在有源区域中暴露栅电极
公开(公告)号：US07320909B2
公开(公告)日：2008-01-22
申请号：US11359840
申请日：2006-02-22
申请人： Jeung-Hwan Park , Myoung-Kwan Cho
发明人： Jeung-Hwan Park , Myoung-Kwan Cho
IPC分类号： H01L21/337
CPC分类号： H01L21/823437 , H01L21/823475 , H01L21/823481
摘要： Integrated circuit devices are provided including an integrated circuit substrate and first, second and third spaced apart insulating regions in the integrated circuit substrate that define first and second active regions. A first gate electrode is provided on the first active region. The first gate electrode has a first portion on the first active region that extends onto the first insulating region and a second portion at an end of the first portion on the first insulating region. A second gate electrode is provided on the second active region. An insulating layer is provided on the first, second and third active regions defining a first gate contact hole that exposes at least a portion of the second portion of the first gate electrode. The first gate electrode is free of a gate contact hole on the first portion of the first gate electrode. A second gate contact hole is provided on the second active region that exposes at least a portion of the second gate electrode. Related methods of fabricating integrated circuit devices are also provided.
摘要翻译：提供集成电路器件，其包括集成电路衬底以及集成电路衬底中的第一，第二和第三间隔绝缘区域，其限定第一和第二有源区域。第一栅电极设置在第一有源区上。第一栅电极在第一有源区上具有延伸到第一绝缘区上的第一部分和位于第一绝缘区上的第一部分末端的第二部分。第二栅电极设置在第二有源区上。绝缘层设置在第一，第二和第三有源区上，限定了暴露第一栅电极的第二部分的至少一部分的第一栅极接触孔。第一栅电极在第一栅电极的第一部分上没有栅极接触孔。在第二有源区上提供第二栅极接触孔，其暴露第二栅电极的至少一部分。还提供了制造集成电路器件的相关方法。

6. 发明授权

US6144064A Split-gate EEPROM device having floating gate with double polysilicon layer 有权
标题翻译：具有双层多晶硅层的浮动栅极的分离栅极EEPROM器件
公开(公告)号：US6144064A
公开(公告)日：2000-11-07
申请号：US275054
申请日：1999-03-23
申请人： Myoung-Kwan Cho , Keon-Soo Kim
发明人： Myoung-Kwan Cho , Keon-Soo Kim
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788
CPC分类号： H01L27/115 , H01L27/11521
摘要： Methods of forming EEPROM memory cells having uniformly thick tunneling oxide layers include the steps of forming a preliminary field oxide isolation region of first thickness at a face of a semiconductor substrate of first conductivity type (e.g., P-type) and then forming a tunneling oxide layer on the face, adjacent the preliminary field oxide isolation region. The memory cell's drain region dopants are then implanted through the preliminary field oxide isolation region and into the substrate to form a preliminary drain region of second conductivity type. The preliminary field oxide isolation region is then grown to a second thickness greater than the first thickness by oxidizing the portion of the substrate containing the implanted dopants, to form a final field oxide isolation region which may have a thickness of about 2000 .ANG.. To prevent unwanted growth of the tunneling oxide layer, a silicon nitride layer is preferably patterned on the tunneling oxide layer and used as an oxidation mask during the step of growing the preliminary field oxide isolation region to a second thickness. The silicon nitride mask is then removed and then a floating gate electrode and insulated control electrode are patterned on the tunneling oxide layer and channel region to complete the memory cell.
摘要翻译：形成具有均匀厚的隧道氧化物层的EEPROM存储单元的方法包括以下步骤：在第一导电类型的半导体衬底（例如，P型）的表面上形成第一厚度的预备场氧化物隔离区，然后形成隧道氧化物层在面上，毗邻初步场氧化物隔离区。然后通过预备场氧化物隔离区域将衬底中的存储单元的漏极区掺杂物注入到衬底中以形成第二导电类型的初级漏区。然后通过氧化含有注入的掺杂剂的衬底的部分，将初始场氧化物隔离区域生长到大于第一厚度的第二厚度，以形成最终的场氧化物隔离区域，其可以具有约2000的厚度。为了防止隧道氧化物层的不期望的生长，优选在隧道氧化物层上图案化氮化硅层，并且在将预备场氧化物隔离区域生长至第二厚度的步骤期间用作氧化掩模。然后去除氮化硅掩模，然后在隧道氧化物层和沟道区上图案化浮栅电极和绝缘控制电极，以完成存储单元。

7. 发明授权

US5888871A Methods of forming EEPROM memory cells having uniformly thick tunnelling oxide layers 失效
标题翻译：形成具有均匀厚度的隧道氧化物层的EEPROM存储单元的方法
公开(公告)号：US5888871A
公开(公告)日：1999-03-30
申请号：US774100
申请日：1996-12-24
申请人： Myoung-Kwan Cho , Keon-Soo Kim
发明人： Myoung-Kwan Cho , Keon-Soo Kim
IPC分类号： H01L21/8247 , H01L27/115
CPC分类号： H01L27/11521 , H01L27/115
摘要： Methods of forming EEPROM memory cells having uniformly thick tunnelling oxide layers include the steps of forming a preliminary field oxide isolation region of first thickness at a face of a semiconductor substrate of first conductivity type (e.g., P-type) and then forming a tunneling oxide layer on the face, adjacent the preliminary field oxide isolation region. The memory cell's drain region dopants are then implanted through the preliminary field oxide isolation region and into the substrate to form a preliminary drain region of second conductivity type. The preliminary field oxide isolation region is then grown to a second thickness greater than the first thickness by oxidizing the portion of the substrate containing the implanted dopants, to form a final field oxide isolation region which may have a thickness of about 2000 .ANG.. To prevent unwanted growth of the tunnelling oxide layer, a silicon nitride layer is preferably patterned on the tunnelling oxide layer and used as an oxidation mask during the step of growing the preliminary field oxide isolation region to a second thickness. The silicon nitride mask is then removed and then a floating gate electrode and insulated control electrode are patterned on the tunnelling oxide layer and channel region to complete the memory cell.
摘要翻译：形成具有均匀厚的隧道氧化物层的EEPROM存储单元的方法包括以下步骤：在第一导电类型的半导体衬底（例如，P型）的表面上形成第一厚度的预备场氧化物隔离区，然后形成隧道氧化物层在面上，毗邻初步场氧化物隔离区。然后通过预备场氧化物隔离区域将衬底中的存储单元的漏极区掺杂物注入到衬底中以形成第二导电类型的初级漏区。然后通过氧化含有注入的掺杂剂的衬底的部分，将初始场氧化物隔离区域生长到大于第一厚度的第二厚度，以形成最终的场氧化物隔离区域，其可以具有约2000的厚度。为了防止隧道氧化物层的不期望的生长，优选在隧道氧化物层上图案化氮化硅层，并且在将预备场氧化物隔离区域生长至第二厚度的步骤期间用作氧化掩模。然后去除氮化硅掩模，然后在隧道氧化物层和沟道区上图案化浮栅电极和绝缘控制电极，以完成存储单元。

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