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1. 发明授权

US08354708B2 Methods of forming and operating semiconductor device 有权
标题翻译：半导体器件的形成和操作方法
公开(公告)号：US08354708B2
公开(公告)日：2013-01-15
申请号：US13087643
申请日：2011-04-15
申请人： Wook-Hyun Kwon , Byung-Gook Park , Yun-Heub Song , Yoon Kim
发明人： Wook-Hyun Kwon , Byung-Gook Park , Yun-Heub Song , Yoon Kim
IPC分类号： H01L29/792
CPC分类号： H01L27/11568 , H01L29/66833 , H01L29/7923
摘要： Provided are a semiconductor device and a methods of forming and operating the semiconductor device. The semiconductor device may include active pillars extending from a semiconductor substrate and disposed two dimensionally disposed on the semiconductor substrate, upper interconnections connecting the active pillars along one direction, lower interconnections crossing the upper interconnections and disposed between the active pillars, word lines crossing the upper interconnections and disposed between the active pillars, and data storage patterns disposed between the word lines and the active pillars.
摘要翻译：提供半导体器件以及形成和操作半导体器件的方法。半导体器件可以包括从半导体衬底延伸并且二维地设置在半导体衬底上的有源柱，在一个方向上连接有源柱的上部互连，与上部互连交叉的下部互连，并且设置在有源柱之间，跨越上部的字线互连并且布置在活动柱之间，以及布置在字线和活动柱之间的数据存储图案。

2. 发明申请

US20110194356A1 METHODS OF FORMING AND OPERATING SEMICONDUCTOR DEVICE 有权
标题翻译：形成和操作半导体器件的方法
公开(公告)号：US20110194356A1
公开(公告)日：2011-08-11
申请号：US13087643
申请日：2011-04-15
申请人： Wook-Hyun KWON , Byung-Gook PARK , Yun-Heub SONG , Yoon KIM
发明人： Wook-Hyun KWON , Byung-Gook PARK , Yun-Heub SONG , Yoon KIM
IPC分类号： G11C11/34 , H01L21/336
CPC分类号： H01L27/11568 , H01L29/66833 , H01L29/7923
摘要： Provided are a semiconductor device and a methods of forming and operating the semiconductor device. The semiconductor device may include active pillars extending from a semiconductor substrate and disposed two dimensionally disposed on the semiconductor substrate, upper interconnections connecting the active pillars along one direction, lower interconnections crossing the upper interconnections and disposed between the active pillars, word lines crossing the upper interconnections and disposed between the active pillars, and data storage patterns disposed between the word lines and the active pillars.
摘要翻译：提供半导体器件以及形成和操作半导体器件的方法。半导体器件可以包括从半导体衬底延伸并且二维地设置在半导体衬底上的有源柱，在一个方向上连接有源柱的上部互连，与上部互连交叉的下部互连，并且设置在有源柱之间，跨越上部的字线互连并且布置在活动柱之间，以及布置在字线和活动柱之间的数据存储图案。

3. 发明申请

US20080265303A1 METHODS OF FORMING SHALLOW TRENCH ISOLATION STRUCTURES WITH BURIED BIT LINES IN NON-VOLATILE MEMORIES AND DEVICES, CARDS, AND SYSTEMS SO FORMED 失效
标题翻译：形成非易失性存储器和设备，卡和系统中的带有双绞线的浅层分离结构的方法形成
公开(公告)号：US20080265303A1
公开(公告)日：2008-10-30
申请号：US12109761
申请日：2008-04-25
申请人： Wook Hyun Kwon
发明人： Wook Hyun Kwon
IPC分类号： H01L29/00 , H01L21/76
CPC分类号： H01L27/115 , G11C16/0416 , H01L21/76224 , H01L27/11521 , H01L29/42336 , H01L29/7881
摘要： Methods of forming buried bit lines in a non-volatile memory device can include forming impurity regions in a substrate of a non-volatile memory device to provide immediately neighboring buried bit lines for the device and then forming a shallow trench isolation region in the substrate between the immediately neighboring buried bit lines to substantially equalize lengths of the immediately neighboring buried bit lines.
摘要翻译：在非易失性存储器件中形成掩埋位线的方法可以包括在非易失性存储器件的衬底中形成杂质区域，以为器件提供直接相邻的掩埋位线，然后在衬底中形成浅沟槽隔离区域直接相邻的掩埋位线基本上相等的直接相邻的掩埋位线的长度。

4. 发明申请

US20070268749A1 Method for operating non-volatile memory device 审中-公开
标题翻译：操作非易失性存储器件的方法
公开(公告)号：US20070268749A1
公开(公告)日：2007-11-22
申请号：US11802282
申请日：2007-05-22
申请人： Dae-Mann Kim , Wook-Hyun Kwon , Ki-Nam Kim , Chan-Kwang Park , Sang-Pil Sim
发明人： Dae-Mann Kim , Wook-Hyun Kwon , Ki-Nam Kim , Chan-Kwang Park , Sang-Pil Sim
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/10 , G11C11/5671 , G11C16/0483 , G11C16/3409 , G11C16/345
摘要： A method of operating a non-volatile memory device is disclosed. The memory cell includes a channel region separating a source region and a drain region, a tunnel insulating layer, a charge storage layer, and a gate electrode formed over the channel region. The method includes applying a negative voltage to the gate electrode and applying a positive voltage to at least one of the source and drain regions to inject holes into the tunnel insulating layer and thereby remove electrons trapped in the tunnel insulating layer.
摘要翻译：公开了一种操作非易失性存储器件的方法。存储单元包括分离源极区和漏极区的沟道区，隧道绝缘层，电荷存储层和形成在沟道区上的栅电极。该方法包括向栅电极施加负电压并向源区和漏区中的至少一个施加正电压，以将空穴注入到隧道绝缘层中，从而去除俘获在隧道绝缘层中的电子。

5. 发明申请

US20060099756A1 Methods of forming non-volatile memory device having floating gate 失效
标题翻译：形成具有浮动栅极的非易失性存储器件的方法
公开(公告)号：US20060099756A1
公开(公告)日：2006-05-11
申请号：US11268038
申请日：2005-11-07
申请人： Wook-Hyun Kwon
发明人： Wook-Hyun Kwon
IPC分类号： H01L21/8238
CPC分类号： H01L27/11546 , H01L21/82345 , H01L27/105 , H01L27/11526 , H01L29/66825
摘要： Embodiments of the present invention are directed to methods for forming non-volatile memory devices. A substrate is provided that has a cell region, a first peripheral region, and second peripheral region. A tunnel insulating layer is formed on the substrate in the cell region. A preliminary floating gate is formed on the tunnel insulating layer in the cell region. A blocking insulating layer is formed on the substrate in the cell region, the first peripheral region, and the second peripheral region. A conductive layer is formed on the blocking insulating layer in the cell region, the first peripheral region, and the second peripheral region. The conductive layer and the blocking insulating layer in the first and second peripheral regions are removed to expose at least a portion of the substrate in the first and second peripheral regions. First and second gate insulating layers are respectively formed on the exposed substrate of the first and second peripheral regions. An undoped silicon layer is formed on the substrate in the cell region, the first peripheral region, and the second peripheral region. The undoped silicon layer in the first peripheral region is doped with impurities of a first-conductivity-type. The undoped silicon layer in the second peripheral region is doped with impurities of a second-conductivity-type.
摘要翻译：本发明的实施例涉及用于形成非易失性存储器件的方法。提供了具有单元区域，第一周边区域和第二外围区域的基板。在单元区域的基板上形成隧道绝缘层。在电池区域的隧道绝缘层上形成初步浮栅。在单元区域，第一周边区域和第二周边区域中的基板上形成阻挡绝缘层。在单元区域，第一周边区域和第二周边区域中的阻挡绝缘层上形成导电层。去除第一和第二周边区域中的导电层和阻挡绝缘层，以暴露第一和第二周边区域中的至少一部分基板。第一和第二栅极绝缘层分别形成在第一和第二周边区域的暴露的基板上。在单元区域，第一周边区域和第二周边区域的基板上形成未掺杂的硅层。第一周边区域中未掺杂的硅层掺杂有第一导电类型的杂质。第二周边区域中未掺杂的硅层掺杂有第二导电类型的杂质。

6. 发明授权

US06501680B1 Nonvolatile memory, cell array thereof, and method for sensing data therefrom 失效
标题翻译：非易失性存储器，其单元阵列，以及用于检测数据的方法
公开(公告)号：US06501680B1
公开(公告)日：2002-12-31
申请号：US10126584
申请日：2002-04-22
申请人： Wook Hyun Kwon
发明人： Wook Hyun Kwon
IPC分类号： G11C700
CPC分类号： H01L29/7887 , G11C11/5621 , G11C11/5642 , G11C16/0458 , G11C16/26 , G11C2211/5612 , H01L27/115
摘要： Nonvolatile memory, cell array thereof, and method for sensing a data therefrom, the method including the steps of: selecting a flash memory cell having a first floating gate and a second floating gate, a first control gate and a second control gate, and a drain and a source; flowing a current through a first channel under the first floating gate and detecting a current flow through a second channel under the second floating gate, thereby sensing a color state of the second floating gate; flowing a current through the second channel and conducting level writings on the first floating gate, thereby forming different threshold voltages; measuring a cell current of the first channel under the first floating gate; comparing the measured cell current to a reference current, thereby sensing a level state of the first floating gate; and sensing information bits stored in the flash memory cell according to a color state of the second floating gate and a level state of the first floating gate.
摘要翻译：非易失性存储器，其单元阵列以及用于检测数据的方法，所述方法包括以下步骤：选择具有第一浮置栅极和第二浮置栅极，第一控制栅极和第二控制栅极的闪存单元，以及排水和来源; 使电流流过第一浮动栅极下方的第一通道，并检测通过第二浮栅下方的第二通道的电流，从而感测第二浮栅的彩色状态; 使电流流过第二通道并在第一浮栅上导通电平写入，从而形成不同的阈值电压; 测量第一浮动栅下的第一通道的单元电流; 将所测量的电池电流与参考电流进行比较，从而检测第一浮动栅极的电平状态; 以及根据第二浮动栅极的颜色状态和第一浮动栅极的电平状态来感测存储在闪存单元中的信息位。

7. 发明申请

US20080094923A1 Non-volatile memory device capable of reducing threshold voltage distribution 有权
标题翻译：能够降低阈值电压分布的非易失性存储器件
公开(公告)号：US20080094923A1
公开(公告)日：2008-04-24
申请号：US11636205
申请日：2006-12-09
申请人： Wook-Hyun Kwon
发明人： Wook-Hyun Kwon
IPC分类号： G11C7/00
CPC分类号： G11C16/3454 , G11C29/70
摘要： A method for programming a flash memory device which includes a plurality of memory cells arranged in rows and columns. The method includes programming selected memory cells from among the plurality of memory cells according to loaded data bits. Data bits are read from the programmed selected memory cells. It is determined whether each of the programmed memory cells has been successfully programmed based on the results of the reading step. The programming of memory cells that have been determined to have been successfully programmed are inhibited. The programming, reading, determining and inhibiting steps are repeated until each of the selected memory cells has been determined to have been successfully programmed. A memory cell that has been previously determined to have been successfully programmed and inhibited is uninhibited and subsequently re-programmed when it is determined that the previously inhibited memory cell is no longer successfully programmed.
摘要翻译：一种用于编程闪存设备的方法，其包括以行和列排列的多个存储器单元。该方法包括根据加载的数据位来从多个存储器单元中编程所选择的存储器单元。从编程的选定的存储单元中读取数据位。基于读取步骤的结果确定每个已编程的存储器单元是否已被成功编程。已经确定成功编程的存储器单元的编程被禁止。重复编程，读取，确定和禁止步骤，直到所选择的存储器单元被确定为已被成功编程。先前确定已被成功编程和禁止的存储器单元是不受限制的，并且随后在确定先前禁止的存储器单元不再被成功编程时重新编程。

8. 发明授权

US07230853B2 Selective erase method for flash memory 失效
标题翻译：闪存的选择性擦除方法
公开(公告)号：US07230853B2
公开(公告)日：2007-06-12
申请号：US10960542
申请日：2004-10-07
申请人： Wook-Hyun Kwon , Jung-In Han
发明人： Wook-Hyun Kwon , Jung-In Han
IPC分类号： G11C16/06
CPC分类号： G11C16/3445 , G11C16/16 , G11C16/3468 , G11C16/3472 , G11C2216/18
摘要： Selective erase method for a flash memory device including a group of memory cells arranged in rows and columns include performing an erase operation on the group of memory cells and verifying the erase operation on the group of memory cells to determine threshold voltages of the memory cells. At least one row of memory cells including memory cells having a threshold voltage lower than a desired erase threshold voltage is identified. A further erase operation is performed on the group of memory cells excluding memory cells of the at least one row of memory cells including memory cells having a threshold voltage lower than a desired erase threshold voltage.
摘要翻译：包括排列成行和列的一组存储器单元的闪速存储器件的选择性擦除方法包括对该组存储器单元执行擦除操作，并验证存储器单元组的擦除操作以确定存储器单元的阈值电压。识别包括具有低于期望的擦除阈值电压的阈值电压的存储单元的至少一行存储单元。对包括具有低于期望的擦除阈值电压的阈值电压的存储单元的至少一行存储单元的存储单元排除的存储器单元组执行进一步的擦除操作。

9. 发明申请

US20060018163A1 Selective erase method for flash memory 失效
标题翻译：闪存的选择性擦除方法
公开(公告)号：US20060018163A1
公开(公告)日：2006-01-26
申请号：US10960542
申请日：2004-10-07
申请人： Wook-Hyun Kwon , Jung-In Han
发明人： Wook-Hyun Kwon , Jung-In Han
IPC分类号： G11C16/04
CPC分类号： G11C16/3445 , G11C16/16 , G11C16/3468 , G11C16/3472 , G11C2216/18
摘要： Selective erase method for a flash memory device including a group of memory cells arranged in rows and columns include performing an erase operation on the group of memory cells and verifying the erase operation on the group of memory cells to determine threshold voltages of the memory cells. At least one row of memory cells including memory cells having a threshold voltage lower than a desired erase threshold voltage is identified. A further erase operation is performed on the group of memory cells excluding memory cells of the at least one row of memory cells including memory cells having a threshold voltage lower than a desired erase threshold voltage.
摘要翻译：包括排列成行和列的一组存储器单元的闪速存储器件的选择性擦除方法包括对该组存储器单元执行擦除操作，并验证存储器单元组的擦除操作以确定存储器单元的阈值电压。识别包括具有低于期望的擦除阈值电压的阈值电压的存储单元的至少一行存储单元。对包括具有低于期望的擦除阈值电压的阈值电压的存储单元的至少一行存储单元的存储单元排除的存储器单元组执行进一步的擦除操作。

10. 发明授权

US06849506B2 Non-volatile memory device and fabrication method 失效
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US06849506B2
公开(公告)日：2005-02-01
申请号：US10659351
申请日：2003-09-11
申请人： Kee Yeol Na , Wook Hyun Kwon
发明人： Kee Yeol Na , Wook Hyun Kwon
IPC分类号： H01L27/115 , H01L21/336 , H01L29/423
CPC分类号： H01L29/66825 , H01L29/42328
摘要： A non-volatile memory device includes a floating gate formed over a semiconductor substrate. At one end of the floating gate, there is a tapered protrusion having a horn-like or bird's beak shape. A control gate covers the floating gate except for the tapered protrusion. Sidewall spacers are formed adjacent to the floating gate and the control gate. An erasing gate is formed over the tapered protrusion of the floating gate.
摘要翻译：非易失性存储器件包括形成在半导体衬底上的浮栅。在浮动闸门的一端，有一个具有喇叭状或鸟形喙状的锥形突起。除了锥形突起之外，控制门覆盖浮动栅极。侧壁间隔件形成为与浮动栅极和控制栅极相邻。在浮动栅极的锥形突起上形成擦除栅极。

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