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1. 发明授权

US5245206A Capacitors with roughened single crystal plates 失效
标题翻译：具有粗糙单晶板的电容器
公开(公告)号：US5245206A
公开(公告)日：1993-09-14
申请号：US881944
申请日：1992-05-12
申请人： Jack O. Chu , Louis L. Hsu , Toshio Mii , Joseph F. Shepard , Scott R. Stiffler , Manu J. Tejwani , Edward J. Vishnesky
发明人： Jack O. Chu , Louis L. Hsu , Toshio Mii , Joseph F. Shepard , Scott R. Stiffler , Manu J. Tejwani , Edward J. Vishnesky
IPC分类号： H01L27/04 , H01L21/02 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108 , H01L29/94
CPC分类号： H01L28/84 , H01L29/94 , Y10S438/964
摘要： A capacitor is provided having a substrate and a first capacitor plate including a lattice mismatched crystalline material is formed over and supported by a surface of the substrate. A layer of insulating material is formed over and supported by the first capacitor plate. A second capacitor plate including a layer of conductive material is formed over and supported by the layer of insulating material.
摘要翻译：提供一种电容器，其具有衬底，并且包括晶格失配的晶体材料的第一电容器板形成在衬底的表面上并由衬底的表面支撑。一层绝缘材料形成在第一电容器板上并由其支撑。包括导电材料层的第二电容器板形成在绝缘材料层的上方并由其支撑。

2. 发明授权

US5461243A Substrate for tensilely strained semiconductor 失效
标题翻译：用于拉伸应变半导体的基板
公开(公告)号：US5461243A
公开(公告)日：1995-10-24
申请号：US145986
申请日：1993-10-29
申请人： Bruce A. Ek , Subramanian S. Iyer , Philip M. Pitner , Adrian R. Powell , Manu J. Tejwani
发明人： Bruce A. Ek , Subramanian S. Iyer , Philip M. Pitner , Adrian R. Powell , Manu J. Tejwani
IPC分类号： H01L21/02 , H01L21/20 , H01L21/324 , H01L27/12 , H01L31/072 , H01L27/01 , H01L29/06
CPC分类号： H01L21/02532 , H01L21/02381 , H01L21/0245 , H01L21/02488 , H01L21/02502
摘要： A structure with strained and defect free semiconductor layers. In a preferred embodiment, silicon on insulator may be used as a substrate for the growth of fully relaxed SiGe buffer layers. A new strain relief mechanism operates, whereby the SiGe layer relaxes without the generation of threading dislocations within the SiGe layer. This is achieved by depositing SiGe on an SOI substrate with a superficial silicon thickness. Initially the strain in the SiGe layer becomes equalized with the thin Si layer by creating tensile strain in the Si layer. Then the strain created in the thin Si layer is relaxed by plastic deformation during an anneal. Since dislocations are formed, and glide in the thin Si layer, threading dislocations are not introduced into the upper SiGe material. A strained silicon layer for heterostructures may then be formed on the SiGe material.
摘要翻译：具有应变和无缺陷半导体层的结构。在优选实施例中，绝缘体上硅可以用作用于生长完全松弛的SiGe缓冲层的衬底。新的应变消除机构工作，由此SiGe层松弛，而不会在SiGe层内产生穿透位错。这通过在具有表面硅厚度的SOI衬底上沉积SiGe来实现。最初，通过在Si层中产生拉伸应变，SiGe层中的应变与薄Si层相等。那么在薄Si层中产生的应变在退火过程中被塑性变形所松弛。由于形成位错，并且在薄的Si层中滑动，所以穿透位错不会引入上部SiGe材料。然后可以在SiGe材料上形成用于异质结构的应变硅层。

3. 发明授权

US5194397A Method for controlling interfacial oxide at a polycrystalline/monocrystalline silicon interface 失效
标题翻译：在多晶/单晶硅界面处理界面氧化物的方法
公开(公告)号：US5194397A
公开(公告)日：1993-03-16
申请号：US710498
申请日：1991-06-05
申请人： Robert K. Cook , Ronald W. Knepper , Subodh K. Kulkarni , Russell C. Lange , Paul A. Ronsheim , Seshadri Subbanna , Manu J. Tejwani , Bob H. Yun
发明人： Robert K. Cook , Ronald W. Knepper , Subodh K. Kulkarni , Russell C. Lange , Paul A. Ronsheim , Seshadri Subbanna , Manu J. Tejwani , Bob H. Yun
IPC分类号： H01L21/205 , H01L21/225 , H01L21/285 , H01L21/316 , H01L21/331 , H01L29/73 , H01L29/732
CPC分类号： H01L21/02238 , H01L21/02255 , H01L21/02307 , H01L21/2256 , H01L21/28525 , H01L21/31662 , Y10S148/017 , Y10S148/124 , Y10S438/974
摘要： A method of controlling the interfacial oxygen concentration of a monocrystalline/polycrystalline emitter includes the steps of: passivating the monocrystalline silicon surface by immersing the wafer in a diluted HF acid solution; transferring the wafer into a high vacuum environment; heating the wafer to between 400.degree. and 700.degree. C.; exposing the monocrystalline silicon surface to a gas having a partial pressure of oxygen of between 10.sup.-5 to 1 Torr for between 1 and 100 minutes; and, depositing polysilicon onto the monocrystalline silicon surface.

4. 发明授权

US5612255A One dimensional silicon quantum wire devices and the method of manufacture thereof 失效
标题翻译：一维硅量子线器件及其制造方法
公开(公告)号：US5612255A
公开(公告)日：1997-03-18
申请号：US466315
申请日：1995-06-06
申请人： Jonathan D. Chapple-Sokol , Seshadri Subbanna , Manu J. Tejwani
发明人： Jonathan D. Chapple-Sokol , Seshadri Subbanna , Manu J. Tejwani
IPC分类号： H01L21/335 , H01L29/12 , H01L29/423 , H01L31/0352 , H01L31/11 , H01L21/265 , H01L21/44 , H01L21/48
CPC分类号： H01L31/1105 , B82Y10/00 , H01L29/66439 , H01L31/0352 , H01L29/0665 , H01L29/66795 , H01L29/785 , Y10S438/962
摘要： A silicon quantum wire transistor. A silicon substrate is sub-etched leaving a thin ridge (.ltoreq.500 .ANG. tall by .ltoreq.500 .ANG. wide) of silicon a quantum wire, on the substrate surface. An FET may be formed from the quantum wire by depositing or growing gate oxide and depositing gate poly. After defining a gate, the source and drain are defined. Alternatively, an optically activated transistor is formed by defining an emitter and collector and providing a path for illumination to the wire.
摘要翻译：硅量子线晶体管。在衬底表面上，对硅衬底进行次蚀刻，留下一个硅量子线的薄脊（

5. 发明授权

US5293050A Semiconductor quantum dot light emitting/detecting devices 失效
标题翻译：半导体量子点发光/检测装置
公开(公告)号：US5293050A
公开(公告)日：1994-03-08
申请号：US37154
申请日：1993-03-25
申请人： Jonathan D. Chapple-Sokol , Seshadri Subbanna , Manu J. Tejwani
发明人： Jonathan D. Chapple-Sokol , Seshadri Subbanna , Manu J. Tejwani
IPC分类号： H01L21/20 , G02B6/42 , H01L29/06 , H01L31/0352 , H01L31/105 , H01L31/12 , H01L33/06 , H01L33/34
CPC分类号： H01L33/06 , B82Y10/00 , B82Y20/00 , G02B6/42 , H01L31/0352 , H01L31/105 , H01L33/34 , Y10S148/099 , Y10S438/962
摘要： A semiconductor light emitting/detecting device has a first doped silicon layer, an intrinsic silicon epitaxial layer formed on the first doped silicon layer, at least one quantum dot embedded within the intrinsic silicon epitaxial layer, and a second doped silicon layer formed on the second intrinsic silicon epitaxial layer.
摘要翻译：半导体发光/检测装置具有第一掺杂硅层，形成在第一掺杂硅层上的本征硅外延层，嵌入本征硅外延层内的至少一个量子点，以及形成在第二掺杂硅层上的第二掺杂硅层本征硅外延层。

6. 发明授权

US5268324A Modified silicon CMOS process having selectively deposited Si/SiGe FETS 失效
标题翻译：改进的硅CMOS工艺具有选择性沉积的Si / SiGe FET
公开(公告)号：US5268324A
公开(公告)日：1993-12-07
申请号：US890042
申请日：1992-05-27
申请人： John M. Aitken , Vijay P. Kesan , Seshadri Subbanna , Manu J. Tejwani , Subramanian S. Iyer
发明人： John M. Aitken , Vijay P. Kesan , Seshadri Subbanna , Manu J. Tejwani , Subramanian S. Iyer
IPC分类号： H01L21/336 , H01L21/8238 , H01L27/092 , H01L21/70
CPC分类号： H01L29/66477 , H01L21/8238 , H01L27/0928 , Y10S148/082 , Y10S438/902
摘要： A process is disclosed for making CMOS devices with enhanced performance PMOS FETS by integrating germanium technology into a silicon-based fabrication method. Silicon-germanium layers are selectively grown on the surfaces of oxide-isolated PFET pockets of a silicon substrate previously prepared by a conventional silicon CMOS process. A silicon cap is deposited over each Si--Ge layer and gate insulator is formed over the cap provide gate dielectric for the PFETS. Gate insulator is formed over the NFET pockets to provide gate dielectric for the NFETS. Gate structures are completed along with source and drain junctions in accordance with normal practice. Provision also is made for the additional selective growth of a second silicon-germanium layer on the surfaces of oxide-isolated NFET pockets on the same CMOS substrate to enhance the performance of the NFETS as well as that of the PFETS.
摘要翻译：公开了一种通过将锗技术集成到基于硅的制造方法中来制造具有增强性能的PMOS FET的CMOS器件的工艺。硅 - 锗层选择性地生长在预先通过常规硅CMOS工艺制备的硅衬底的氧化物隔离PFET穴的表面上。在每个Si-Ge层上沉积硅帽，并且在盖上形成栅极绝缘体，为PFETS提供栅极电介质。栅极绝缘体形成在NFET槽之上，为NFETS提供栅极电介质。根据正常做法，栅极结构与源极和漏极连接点一起完成。还提供了在同一CMOS衬底上的氧化物隔离的NFET穴的表面上附加选择性地生长第二硅 - 锗层，以增强NFETS以及PFETS的性能。

7. 发明授权

US5420069A Method of making corrosion resistant, low resistivity copper for interconnect metal lines 失效
标题翻译：用于互连金属线的耐腐蚀性，低电阻率铜的方法
公开(公告)号：US5420069A
公开(公告)日：1995-05-30
申请号：US999245
申请日：1992-12-31
申请人： Rajiv V. Joshi , Manu J. Tejwani , Kris V. Srikrishnan
发明人： Rajiv V. Joshi , Manu J. Tejwani , Kris V. Srikrishnan
IPC分类号： H01L21/768 , H01L23/498 , H01L23/532 , H01L21/44
CPC分类号： H01L21/76852 , H01L21/76838 , H01L21/76849 , H01L23/49866 , H01L23/53233 , H01L2924/0002
摘要： The fabrication and use of corrosion resistant Cu/Cu(x)Ge(y) alloy or Cu/Cu.sub.3 Ge phase bilayer interconnect metal lines is disclosed. A solid state, selective process of forming a Cu.sub.3 Ge phase or Cu(x)Ge(y) alloy by reacting GeH.sub.4 gas with Cu surface at low pressure in CVD reactor at temperatures of 200.degree.-450.degree. C. is described. Corrosion resistant semiconductor devices and packaging interconnects where corrosion of copper interconnects was a problem, is now made possible by the Cu/Cu.sub.3 Ge phase or Cu.sub.x Ge.sub.y alloy bilayer of the present invention. A structure where copper vias are completely or partially converted to Cu.sub.3 Ge or Cu.sub.x Ge.sub.y is presented. Also, dissimilar metals like Al--Cu can be connected by Cu.sub.3 Ge phase or Cu.sub.x Ge.sub.y alloy filled vias to improve electromigration performance.
摘要翻译：公开了耐蚀Cu / Cu（x）Ge（y）合金或Cu / Cu3Ge相双层互连金属线的制造和使用。描述了在200-450℃的温度下在CVD反应器中使GeH 4气体与Cu表面在低压下反应形成Cu 3 Ge相或Cu（x）Ge（y）合金的固态选择性过程。通过本发明的Cu / Cu3Ge相或CuxGey合金双层，现在可以实现铜互连的腐蚀问题的耐腐蚀半导体器件和封装互连。提出了铜通孔完全或部分转化为Cu3Ge或CuxGey的结构。此外，不同的金属如Al-Cu可以通过Cu3Ge相或CuxGey合金填充的通孔连接，以提高电迁移性能。

8. 发明授权

US5310451A Method of forming an ultra-uniform silicon-on-insulator layer 失效
标题翻译：形成超均匀绝缘体上硅层的方法
公开(公告)号：US5310451A
公开(公告)日：1994-05-10
申请号：US108272
申请日：1993-08-19
申请人： Manu J. Tejwani , Subramanian S. Iyer
发明人： Manu J. Tejwani , Subramanian S. Iyer
IPC分类号： H01L21/762 , H01L21/306
CPC分类号： H01L21/76251 , Y10S148/012 , Y10S438/977
摘要： A method of forming a thin semiconductor layer having ultra-high thickness uniformity and upon which semiconductor structures can subsequently be formed is disclosed. The method comprises providing a primary substrate having a prescribed total thickness variation (TTV). A stack is formed upon the primary substrate for compressing thickness variation to be transferred into the thin semiconductor layer. An epitaxial silicon layer of a desired SOI thickness is formed upon the stack. The epitaxial silicon layer is then bonded to a mechanical substrate to form a bonded substrate pair, the mechanical substrate having a prescribed TTV and the bonded substrate pair having a combined TTV equal to the sum of the TTVs of the primary and mechanical substrates, respectively. The primary substrate is subsequently removed, wherein the combined TTV of the bonded substrate pair is transferred and compressed into the stack by a first compression amount. The stack is thereafter removed, wherein the combined TTV of the bonded substrate pair is further transferred and compressed a second compression amount into said epitaxial silicon layer, whereby said epitaxial silicon layer remains on said mechanical substrate to form the semiconductor layer of ultra-high thickness uniformity, the thickness uniformity being a controlled function of the first and second compression amounts.
摘要翻译：公开了一种形成具有超高厚度均匀性的薄半导体层并随后可以形成半导体结构的方法。该方法包括提供具有规定的总厚度变化（TTV）的初级衬底。堆叠形成在主基板上，用于压缩厚度变化以被转移到薄半导体层中。在叠层上形成期望的SOI厚度的外延硅层。然后将外延硅层接合到机械衬底以形成键合衬底对，机械衬底具有规定的TTV，并且键合衬底对具有分别等于初级和机械衬底的TTV的总和的组合TTV。随后去除主衬底，其中键合衬底对的组合TTV被传送并以第一压缩量压缩到堆叠中。之后去除堆叠，其中键合衬底对的组合TTV被进一步转印并且以第二压缩量压缩到所述外延硅层中，由此所述外延硅层保留在所述机械衬底上以形成超高厚度的半导体层均匀性，厚度均匀性是第一和第二压缩量的受控函数。

9. 发明授权

US5485032A Antifuse element with electrical or optical programming 失效
标题翻译：具有电气或光学编程的防腐元件
公开(公告)号：US5485032A
公开(公告)日：1996-01-16
申请号：US355206
申请日：1994-12-08
申请人： Dominic J. Schepis , Kris V. Srikrishnan , Seshadri Subbanna , Manu J. Tejwani
发明人： Dominic J. Schepis , Kris V. Srikrishnan , Seshadri Subbanna , Manu J. Tejwani
IPC分类号： H01L21/82 , H01L21/768 , H01L23/525 , H01L29/00
CPC分类号： H01L23/5254 , H01L21/76888 , H01L21/76894 , H01L23/5252 , H01L2924/0002 , Y10S438/933
摘要： A programmable antifuse element comprising adjacent bodies of germanium and aluminum or aluminum allow form a low resistance connection of good mechanical and thermal properties when heated to a temperature where alloying of the aluminum and germanium occurs. Heating for the purpose of programming the antifuse element can be done by electrical resistance heating in the-germanium, which may be doped to achieve a desired resistance value, or by laser irradiation. Due to the high resistance of intrinsic or lightly doped germanium, a resistance change ratio of greater than 10,000:1 is achieved.
摘要翻译：包括锗和铝或铝的相邻体的可编程反熔丝元件在加热到发生铝和锗的合金化的温度时形成良好机械和热性能的低电阻连接。用于编程反熔丝元件的加热可以通过锗中的电阻加热来实现，其可以被掺杂以实现期望的电阻值，或通过激光照射。由于本征或轻掺杂锗的高电阻，实现了大于10,000:1的电阻变化率。

10. 发明授权

US5384152A Method for forming capacitors with roughened single crystal plates 失效
标题翻译：用粗糙单晶板形成电容器的方法
公开(公告)号：US5384152A
公开(公告)日：1995-01-24
申请号：US69473
申请日：1993-06-01
申请人： Jack C. Chu , Louis Lu-Chen Hsu , Toshio Mii , Joseph F. Shepard , Scott R. Stiffler , Manu J. Tejwani , Edward J. Vishnesky
发明人： Jack C. Chu , Louis Lu-Chen Hsu , Toshio Mii , Joseph F. Shepard , Scott R. Stiffler , Manu J. Tejwani , Edward J. Vishnesky
IPC分类号： H01L27/04 , H01L21/02 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108 , H01L29/94 , H01L21/70 , B05D5/12
CPC分类号： H01L28/84 , H01L29/94 , Y10S438/964
摘要： A capacitor is provided having a substrate and a first capacitor plate including a lattice mismatched crystalline material is formed over and supported by a surface of the substrate. A layer of insulating material is formed over and supported by the first capacitor plate. A second capacitor plate including a layer of conductive material is formed over and supported by the layer of insulating material.
摘要翻译：提供一种电容器，其具有衬底，并且包括晶格失配的晶体材料的第一电容器板形成在衬底的表面上并由衬底的表面支撑。一层绝缘材料形成在第一电容器板上并由其支撑。包括导电材料层的第二电容器板形成在绝缘材料层的上方并由其支撑。

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