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1. 发明授权

US6150707A Metal-to-metal capacitor having thin insulator 有权
标题翻译：具有薄绝缘体的金属对金属电容器
公开(公告)号：US6150707A
公开(公告)日：2000-11-21
申请号：US226243
申请日：1999-01-07
申请人： Robert K. Cook , Craig R. Gruszecki , Mark A. Passaro , Frederick A. Scholl
发明人： Robert K. Cook , Craig R. Gruszecki , Mark A. Passaro , Frederick A. Scholl
IPC分类号： H01L21/02 , H01L21/768 , H07L29/41
CPC分类号： H01L28/40 , H01L21/76838
摘要： The present invention provides a method for fabricating a capacitor within a semiconductor device comprising the steps of forming openings in an oxide dielectric to reach a lower conductor layer which will serve as a lower conductor plate of the capacitor; depositing capacitor electrode material, such as tungsten to fill the openings to form a capacitor electrode and planarizing the filled openings using chemical/mechanical polish; depositing a selected oxide capacitor dielectric over the capacitor electrodes and patterning the capacitor dielectric with photoresist to leave dielectric covering the area of the capacitor electrodes; stripping away the photoresist; adding an upper conductor layer on top of the capacitor dielectric to serve as the top plate of the capacitor. The above steps may be repeated to form multiple layers of capacitors within the semiconductor device.
摘要翻译：本发明提供了一种在半导体器件内制造电容器的方法，包括以下步骤：在氧化物电介质中形成开口以到达将用作电容器的下导体板的下导体层; 沉积诸如钨的电容器电极材料以填充开口以形成电容器电极，并使用化学/机械抛光对填充的开口进行平坦化; 在电容器电极上沉积选定的氧化物电容器电介质，并用光致抗蚀剂构图电容器电介质以留下覆盖电容器电极区域的电介质; 剥离光致抗蚀剂; 在电容器电介质的顶部添加上导体层以用作电容器的顶板。可以重复上述步骤以在半导体器件内形成多层电容器。

2. 发明授权

US6001702A Metal to metal capacitor and method for producing same 失效
标题翻译：金属与金属电容器及其制造方法
公开(公告)号：US6001702A
公开(公告)日：1999-12-14
申请号：US14934
申请日：1998-01-28
申请人： Robert K. Cook , Craig R. Gruszecki , Mark A. Passaro , Frederick A. Scholl
发明人： Robert K. Cook , Craig R. Gruszecki , Mark A. Passaro , Frederick A. Scholl
IPC分类号： H01L21/02 , H01L21/20
CPC分类号： H01L28/40
摘要： The present invention provides a method for fabricating a capacitor within a semiconductor device comprising the steps of forming openings in an oxide dielectric to reach a lower conductor layer which will serve as a lower conductor plate of the capacitor; depositing capacitor electrode material, such as tungsten to fill the openings to form a capacitor electrode and planarizing the filled openings using chemical/mechanical polish; depositing a selected oxide capacitor dielectric over the capacitor electrodes and patterning the capacitor dielectric with photoresist to leave dielectric covering the area of the capacitor electrodes; stripping away the photoresist; adding an upper conductor layer on top of the capacitor dielectric to serve as the top plate of the capacitor. The above steps may be repeated to form multiple layers of capacitors within the semiconductor device.
摘要翻译：本发明提供了一种在半导体器件内制造电容器的方法，包括以下步骤：在氧化物电介质中形成开口以到达将用作电容器的下导体板的下导体层; 沉积诸如钨的电容器电极材料以填充开口以形成电容器电极，并使用化学/机械抛光对填充的开口进行平坦化; 在电容器电极上沉积选定的氧化物电容器电介质，并用光致抗蚀剂构图电容器电介质以留下覆盖电容器电极区域的电介质; 剥离光致抗蚀剂; 在电容器电介质的顶部添加上导体层以用作电容器的顶板。可以重复上述步骤以在半导体器件内形成多层电容器。

3. 发明授权

US5323057A Lateral bipolar transistor with insulating trenches 失效
标题翻译：具有绝缘沟槽的侧向双极晶体管
公开(公告)号：US5323057A
公开(公告)日：1994-06-21
申请号：US864722
申请日：1992-04-07
申请人： Robert K. Cook , Mario M. A. Pelella
发明人： Robert K. Cook , Mario M. A. Pelella
IPC分类号： H01L27/06 , H01L21/331 , H01L21/8249 , H01L29/73 , H01L29/735 , H01L27/082 , H01L23/48 , H01L27/102 , H01L31/11
CPC分类号： H01L29/6625 , H01L21/8249 , H01L29/735 , Y10S148/096
摘要： A lateral bipolar transistor and method of making which is compatible with making BICMOS circuits are disclosed. The method includes: Forming on a substrate of one conductivity type at least one layer of a semiconductor material of opposite conductivity type. Forming a first region of opposite conductivity type into one portion of the layer and a highly conductive contact region to the layer in another portion, forming a layer of an insulating material over the layer and providing an aperture therethrough to the first region. Depositing a layer of polycrystalline silicon over the insulating layer and in the aperture so that it is in the aperture and extends a short distance beyond the aperture but not beyond the edge of the first region. Ion implanting a dopant of the opposite conductivity type into the polycrystalline silicon and into the portion of the first region which extends beyond the edge of the polycrystalline to form a second region of opposite conductivity type in the layer and around the first region. Annealing the substrate to drive the dopant from the conductive layer into the first region to form a third region of opposite conductivity type.
摘要翻译：公开了与制造BICMOS电路兼容的横向双极晶体管及其制造方法。该方法包括：在一个导电类型的基底上形成至少一层相反导电类型的半导体材料。将相反导电类型的第一区域形成到该层的一部分中，并且在另一部分中与该层的高导电接触区域形成，并在该层上形成绝缘材料层，并提供穿过该第一区域的孔。在绝缘层和孔中沉积多晶硅层，使得其在孔中并且延伸超过孔但不超过第一区的边缘的较短距离。离子将相反导电类型的掺杂剂注入到多晶硅中并进入第一区域的延伸超过多晶边缘的部分，以在层中和围绕第一区域形成相反导电类型的第二区域。退火衬底以将掺杂剂从导电层驱动到第一区域中以形成相反导电类型的第三区域。

4. 发明授权

US4997775A Method for forming a complementary bipolar transistor structure including a self-aligned vertical PNP transistor 失效
标题翻译：用于形成包括自对准垂直PNP晶体管的互补双极晶体管结构的方法
公开(公告)号：US4997775A
公开(公告)日：1991-03-05
申请号：US487502
申请日：1990-02-26
申请人： Robert K. Cook , Chang-Ming Hsieh , Kiyosi Isihara , Mario M. Pelella
发明人： Robert K. Cook , Chang-Ming Hsieh , Kiyosi Isihara , Mario M. Pelella
IPC分类号： H01L21/331 , H01L21/8228 , H01L27/082 , H01L29/73 , H01L29/732
CPC分类号： H01L21/82285 , H01L27/0826 , Y10S148/011
摘要： A method of forming a complementary bipolar transistor device includes the steps of: providing a substrate of semiconductor material including at least two electrically isolated N-type device regions having a generally planar common surface; forming a P-type buried subcollar region in a first of the device regions; forming an N-type buried subcollector region in a second of the device regions; forming an N-type base region in the common surface of the first device region; forming a layer of P-doped polysilicon over the base region in the first device region and over the second device region; patterning the layer of P-doped polysilicon to form an emitter contact generally centered on the base region of the first device region and a generally annular base contact on the second device region; forming a layer of insulating material over the patterned layer of P-doped polysilicon; forming a layer of N-doped polysilicon generally conformally over the device; patterning the layer of N-doped polysilicon to form a base contact generally surrounding the emitter contact on the first device region and an emitter contact generally surrounded by the base contact on the second device region; and heating the device at least once to drive impurities from the base and emitter contacts on the first and second device regions into the device regions whereby to form a vertical PNP transistor in the first device region and a vertical NPN transistor in the second device region.

5. 发明授权

US5194397A Method for controlling interfacial oxide at a polycrystalline/monocrystalline silicon interface 失效
标题翻译：在多晶/单晶硅界面处理界面氧化物的方法
公开(公告)号：US5194397A
公开(公告)日：1993-03-16
申请号：US710498
申请日：1991-06-05
申请人： Robert K. Cook , Ronald W. Knepper , Subodh K. Kulkarni , Russell C. Lange , Paul A. Ronsheim , Seshadri Subbanna , Manu J. Tejwani , Bob H. Yun
发明人： Robert K. Cook , Ronald W. Knepper , Subodh K. Kulkarni , Russell C. Lange , Paul A. Ronsheim , Seshadri Subbanna , Manu J. Tejwani , Bob H. Yun
IPC分类号： H01L21/205 , H01L21/225 , H01L21/285 , H01L21/316 , H01L21/331 , H01L29/73 , H01L29/732
CPC分类号： H01L21/02238 , H01L21/02255 , H01L21/02307 , H01L21/2256 , H01L21/28525 , H01L21/31662 , Y10S148/017 , Y10S148/124 , Y10S438/974
摘要： A method of controlling the interfacial oxygen concentration of a monocrystalline/polycrystalline emitter includes the steps of: passivating the monocrystalline silicon surface by immersing the wafer in a diluted HF acid solution; transferring the wafer into a high vacuum environment; heating the wafer to between 400.degree. and 700.degree. C.; exposing the monocrystalline silicon surface to a gas having a partial pressure of oxygen of between 10.sup.-5 to 1 Torr for between 1 and 100 minutes; and, depositing polysilicon onto the monocrystalline silicon surface.

6. 发明授权

US4654119A Method for making submicron mask openings using sidewall and lift-off techniques 失效
标题翻译：使用侧壁和剥离技术制造亚微米掩模开口的方法
公开(公告)号：US4654119A
公开(公告)日：1987-03-31
申请号：US799053
申请日：1985-11-18
申请人： Robert K. Cook , Joseph F. Shepard
发明人： Robert K. Cook , Joseph F. Shepard
IPC分类号： H01L21/302 , H01L21/033 , H01L21/3065 , H01L21/306
CPC分类号： H01L21/0331 , H01L21/0337 , Y10S438/945 , Y10S438/947 , Y10S438/951
摘要： A method is disclosed for making submicron openings in a substrate. A mesa is formed on the substrate by reactive ion etching techniques. A film is deposited over the entire structure and the mesa is selectively etched away to yield a submicron-sized opening in the film. Using the film as a mask, the substrate exposed thereby is reactively ion etched. An example is given for producing an emitter mask for a polycrystalline silicon base bipolar transistor.
摘要翻译：公开了一种用于在衬底中制造亚微米开口的方法。通过反应离子蚀刻技术在衬底上形成台面。在整个结构上沉积膜，并且选择性地蚀刻台面以在膜中产生亚微米尺寸的开口。使用该膜作为掩模，由此曝光的基底被反应离子蚀刻。给出了制造用于多晶硅基极双极晶体管的发射极掩模的实例。

7. 发明授权

US5235216A Bipolar transistor using emitter-base reverse bias carrier generation 失效
标题翻译：双极晶体管采用发射极 - 反向偏置载波生成
公开(公告)号：US5235216A
公开(公告)日：1993-08-10
申请号：US729969
申请日：1991-07-15
申请人： Robert K. Cook , Bob H. Yun
发明人： Robert K. Cook , Bob H. Yun
IPC分类号： H01L29/10 , H01L29/732
CPC分类号： H01L29/1004 , H01L29/7322
摘要： A circuit for generating a negative voltage includes: a bipolar transistor including, a) an N type collector region, b) a P type base region, and c) an N type emitter region, the base region width between the emitter region and the collector region being less than about 5,000 angstroms and the dopant concentration of the base region being in the range of about 1-10.times.10.sup.18 atoms/cm.sup.3 ; means for applying a reference potential to the base region; and means for applying a bias potential to the emitter region so as to generate a negative output potential at the collector region. The circuit can likewise comprise a PNP bipolar transistor biased to generate a negative voltage. The circuit can be used on integrated circuit chips to provide a complementary voltage, thereby obviating the requirement for separate, complementary power supplies.
摘要翻译：用于产生负电压的电路包括：双极晶体管，包括：a）N型集电极区域，b）P型基极区域，以及c）N型发射极区域，发射极区域与集电极之间的基极区域宽度区域小于约5,000埃，碱性区域的掺杂剂浓度在约1-10×10 18原子/ cm 3的范围内; 用于向基区施加参考电位的装置; 以及用于向发射极区域施加偏置电位以在集电极区域产生负输出电位的装置。该电路同样可以包括偏置以产生负电压的PNP双极晶体管。该电路可用于集成电路芯片以提供互补电压，从而避免了单独的互补电源的需求。

8. 发明授权

US5187109A Lateral bipolar transistor and method of making the same 失效
标题翻译：侧向双极晶体管及其制造方法
公开(公告)号：US5187109A
公开(公告)日：1993-02-16
申请号：US733090
申请日：1991-07-19
申请人： Robert K. Cook , Mario M. A. Pelella
发明人： Robert K. Cook , Mario M. A. Pelella
IPC分类号： H01L27/06 , H01L21/331 , H01L21/8249 , H01L29/73 , H01L29/735
CPC分类号： H01L29/6625 , H01L21/8249 , H01L29/735 , Y10S148/096
摘要： A lateral bipolar transistor and method of making the transistor which is compatible with a method of making MOS transistors to be used in making BICMOS circuits are disclosed. The method includes the following steps: Forming on the surface of a substrate of one conductivity type at least one layer of a semiconductor material of the opposite conductivity type. Forming a first region of the opposite conductivity type into one portion of the layer in one of the portions of the layer and a highly conductive contact region to the layer in another portion, forming a layer of an insulating material over the layer and providing an aperture therethrough to the first region. Depositing a layer of polycrystalline silicon over the insulating layer and in the aperture and defining the polycrystalline silicon layer so that it is in the aperture and extends a short distance beyond the aperture but not beyond the edge of the first region. Ion implanting a dopant of the opposite conductivity type into the defined portion of the polycrystalline silicon and into the portion of the first region which extends beyond the edge of the polycrystalline region to form a second region of the opposite conductivity type in the layer and around the first region. Annealing the substrate to drive the dopant from the conductive layer into the first region to form a third region of the opposite conductivity type in the first region and spaced from the third region.

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