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1. 发明授权

US5384277A Method for forming a DRAM trench cell capacitor having a strap connection 失效
标题翻译：用于形成具有带连接的DRAM沟槽电池电容器的方法
公开(公告)号：US5384277A
公开(公告)日：1995-01-24
申请号：US169875
申请日：1993-12-17
申请人： Louis L. Hsu , Toshio Mii , Joseph F. Shepard , Seiki Ogura
发明人： Louis L. Hsu , Toshio Mii , Joseph F. Shepard , Seiki Ogura
IPC分类号： H01L21/285 , H01L27/108 , H01L21/70 , H01L27/00
CPC分类号： H01L21/28525 , H01L27/10829
摘要： A method of forming a MOS DRAM cell having a trench capacitor in which the strap connection to the trench capacitor, the source, drain, and isolation are all raised above the surface of the single crystal silicon includes the steps of forming the trench capacitors, depositing a blanket gate stack including the gate oxide and a set of gate layers, and then depositing isolation members in apertures etched in the gate stack using the gate oxide as an etch stop. The same sidewalls that are used to form an LDD source and drain combine with nitride sidewalls on a gate contact aperture to separate a gate contact from source and drain contacts.
摘要翻译：一种形成具有沟槽电容器的MOS DRAM单元的方法，其中与沟槽电容器的带连接，源极，漏极和隔离都在单晶硅的表面上方升高，包括以下步骤：形成沟槽电容器，包括栅极氧化物和一组栅极层的覆盖栅极堆叠，然后使用栅极氧化物作为蚀刻停止层，在隔离栅堆叠中蚀刻的孔中沉积隔离元件。用于形成LDD源极和漏极的相同侧壁与栅极接触孔上的氮化物侧壁结合，以将栅极接触与源极和漏极接触分开。

2. 发明授权

US5389559A Method of forming integrated interconnect for very high density DRAMs 失效
标题翻译：形成非常高密度DRAM的集成互连的方法
公开(公告)号：US5389559A
公开(公告)日：1995-02-14
申请号：US161763
申请日：1993-12-02
申请人： Chang-Ming Hsieh , Louis L. Hsu , Toshio Mii , Seiki Ogura , Joseph F. Shepard
发明人： Chang-Ming Hsieh , Louis L. Hsu , Toshio Mii , Seiki Ogura , Joseph F. Shepard
IPC分类号： H01L21/8242 , H01L27/108 , H01L21/70 , H01L27/00
CPC分类号： H01L27/10861 , H01L27/10829
摘要： A trench capacitor DRAM cell with Shallow Trench Isolation (STI), a self-aligned buried strap and the method of making the cell. A trench capacitor is defined in a substrate. The trench capacitor's polysilicon (poly) plate is recessed below the surface of the substrate and the trench sidewalls are exposed above the poly. A doped poly layer is deposited over the surface contacting both the sidewall and the trench capacitor's poly plate. Horizontal portions of the poly layer are removed either through chemmech polishing or Reactive Ion Etching (RIE). A shallow trench is formed, removing one formerly exposed trench sidewall and a portion of the trench capacitor's poly plate in order to isolate the DRAM cell from adjacent cells. The remaining poly strap, along the trench sidewall contacting the poly plate, is self aligned to contact the source of the DRAM Pass gate Field Effect Transistor (FET). After the shallow trench is filled with oxide, FET's are formed on the substrate, completing the cell. In an alternate embodiment, instead of recessing the poly plate, a shallow trench is formed spanning the entire width of the trench capacitor. The deposited polysilicon is selectively removed, having straps that strap the poly plate to the shallow trench sidewall.
摘要翻译：具有浅沟槽隔离（STI）的沟槽电容器DRAM单元，自对准掩埋带和制造电池的方法。沟槽电容器限定在衬底中。沟槽电容器的多晶硅（poly）板在衬底的表面下方凹入，并且沟槽侧壁暴露在聚合物上方。在与侧壁和沟槽电容器的多晶硅板接触的表面上沉积掺杂的多晶硅层。通过化学抛光或反应离子蚀刻（RIE）去除多层的水平部分。形成浅沟槽，去除一个以前暴露的沟槽侧壁和沟槽电容器的多晶片的一部分，以便将DRAM单元与相邻单元隔离。沿着与多晶硅板接触的沟槽侧壁的剩余多晶带自对准以接触DRAM通过栅极场效应晶体管（FET）的源极。在浅沟槽充满氧化物之后，在衬底上形成FET，从而完成电池。在替代实施例中，代替凹陷多晶硅，形成跨越沟槽电容器的整个宽度的浅沟槽。选择性地去除沉积的多晶硅，具有将多晶板绑定到浅沟槽侧壁的带。

3. 发明授权

US5245206A Capacitors with roughened single crystal plates 失效
标题翻译：具有粗糙单晶板的电容器
公开(公告)号：US5245206A
公开(公告)日：1993-09-14
申请号：US881944
申请日：1992-05-12
申请人： Jack O. Chu , Louis L. Hsu , Toshio Mii , Joseph F. Shepard , Scott R. Stiffler , Manu J. Tejwani , Edward J. Vishnesky
发明人： Jack O. Chu , Louis L. Hsu , Toshio Mii , Joseph F. Shepard , Scott R. Stiffler , Manu J. Tejwani , Edward J. Vishnesky
IPC分类号： H01L27/04 , H01L21/02 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108 , H01L29/94
CPC分类号： H01L28/84 , H01L29/94 , Y10S438/964
摘要： A capacitor is provided having a substrate and a first capacitor plate including a lattice mismatched crystalline material is formed over and supported by a surface of the substrate. A layer of insulating material is formed over and supported by the first capacitor plate. A second capacitor plate including a layer of conductive material is formed over and supported by the layer of insulating material.
摘要翻译：提供一种电容器，其具有衬底，并且包括晶格失配的晶体材料的第一电容器板形成在衬底的表面上并由衬底的表面支撑。一层绝缘材料形成在第一电容器板上并由其支撑。包括导电材料层的第二电容器板形成在绝缘材料层的上方并由其支撑。

4. 发明授权

US5384152A Method for forming capacitors with roughened single crystal plates 失效
标题翻译：用粗糙单晶板形成电容器的方法
公开(公告)号：US5384152A
公开(公告)日：1995-01-24
申请号：US69473
申请日：1993-06-01
申请人： Jack C. Chu , Louis Lu-Chen Hsu , Toshio Mii , Joseph F. Shepard , Scott R. Stiffler , Manu J. Tejwani , Edward J. Vishnesky
发明人： Jack C. Chu , Louis Lu-Chen Hsu , Toshio Mii , Joseph F. Shepard , Scott R. Stiffler , Manu J. Tejwani , Edward J. Vishnesky
IPC分类号： H01L27/04 , H01L21/02 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108 , H01L29/94 , H01L21/70 , B05D5/12
CPC分类号： H01L28/84 , H01L29/94 , Y10S438/964
摘要： A capacitor is provided having a substrate and a first capacitor plate including a lattice mismatched crystalline material is formed over and supported by a surface of the substrate. A layer of insulating material is formed over and supported by the first capacitor plate. A second capacitor plate including a layer of conductive material is formed over and supported by the layer of insulating material.
摘要翻译：提供一种电容器，其具有衬底，并且包括晶格失配的晶体材料的第一电容器板形成在衬底的表面上并由衬底的表面支撑。一层绝缘材料形成在第一电容器板上并由其支撑。包括导电材料层的第二电容器板形成在绝缘材料层的上方并由其支撑。

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