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1. 发明申请

WO2010080674A1 SENSING CIRCUIT AND METHOD WITH REDUCED SUSCEPTIBILITY TO SPATIAL AND TEMPERATURE VARIATIONS 审中-公开
标题翻译：传感电路和降低对空间和温度变化的可靠性的方法
公开(公告)号：WO2010080674A1
公开(公告)日：2010-07-15
申请号：PCT/US2009/069703
申请日：2009-12-29
申请人： SANDISK CORPORATION , DUNGA, Mohan, Vamsi , MUI, Man , HIGASHITANI, Masaaki
发明人： DUNGA, Mohan, Vamsi , MUI, Man , HIGASHITANI, Masaaki
IPC分类号： G11C11/56 , G11C16/26
CPC分类号： G11C11/5642 , G11C16/26
摘要： A sense amplifier is disclosed. One embodiment is a sensing circuit (106) that includes a sensing device (104) and a sense transistor (287) coupled to the sensing device. A first switch (288) that is coupled to the sense transistor and to the sensing device causes the sensing device to be charged to a first voltage that is a function of the threshold voltage of the sense transistor. One or more second switches (282, 293, 291, 289) that are coupled to the sensing device and to a target element (10). The second switches couple the sensing device to the target element to modify the first voltage on the sensing device and decouple the target element from the sensing device during a sense phase in which the modified first voltage is applied to the sense transistor. A condition of the target element is determined based on whether or not the sense transistor turns on in response to applying the modified first voltage to the sense transistor.
摘要翻译：公开了一种读出放大器。一个实施例是感测电路（106），其包括耦合到感测装置的感测装置（104）和感测晶体管（287）。耦合到感测晶体管和感测装置的第一开关（288）使得感测装置被充电到作为感测晶体管的阈值电压的函数的第一电压。耦合到感测装置和目标元件（10）的一个或多个第二开关（282,293,291,289）。第二开关将感测装置耦合到目标元件以修改感测装置上的第一电压，并且在将修改的第一电压施加到感测晶体管的感测阶段期间将目标元件与感测装置分离。目标元件的条件基于响应于将修改的第一电压施加到感测晶体管是否导通感测晶体管来确定。

2. 发明申请

WO2014004095A1 SYSTEM TO REDUCE STRESS ON WORD LINE SELECT TRANSISTOR DURING ERASE OPERATION 审中-公开
标题翻译：在擦除操作期间减少字线选择晶体管的压力的系统
公开(公告)号：WO2014004095A1
公开(公告)日：2014-01-03
申请号：PCT/US2013/045585
申请日：2013-06-13
申请人： SANDISK TECHNOLOGIES, INC. , DUNGA, Mohan, Vamsi , MUI, Man , HIGASHITANI, Masaaki , TOYAMA, Fumiaki
发明人： DUNGA, Mohan, Vamsi , MUI, Man , HIGASHITANI, Masaaki , TOYAMA, Fumiaki
IPC分类号： G11C8/08 , G11C16/08 , G11C16/16 , G11C11/56
CPC分类号： G11C16/16 , G11C8/08 , G11C11/5635 , G11C16/08 , G11C16/14
摘要： A system for erasing a non-volatile storage system that reduces the voltage across the word line select transistors which interface between the word lines and global control lines. The use of the lower voltage across the word line select transistors allows for the word line select transistors to be made smaller. The use of smaller components allows the non-volatile storage system to include more memory cells, thereby providing the ability to store more data.
摘要翻译：一种用于擦除非易失性存储系统的系统，其降低了在字线和全局控制线之间接合的字线选择晶体管两端的电压。在字线选择晶体管两端使用较低的电压允许使字线选择晶体管更小。使用更小的组件允许非易失性存储系统包括更多的存储器单元，从而提供存储更多数据的能力。

3. 发明申请

WO2011025731A1 PARTIAL SPEED AND FULL SPEED PROGRAMMING FOR NON-VOLATILE MEMORY USING FLOATING BIT LINES 审中-公开
标题翻译：使用浮动位线的非易失性存储器的部分速度和全速编程
公开(公告)号：WO2011025731A1
公开(公告)日：2011-03-03
申请号：PCT/US2010/046312
申请日：2010-08-23
申请人： SANDISK CORPORATION , MUI, Man , DONG, Yingda , LE, Binh , DUTTA, Deepanshu
发明人： MUI, Man , DONG, Yingda , LE, Binh , DUTTA, Deepanshu
IPC分类号： G11C11/56 , G11C16/10 , G11C16/34
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/3418 , G11C16/3427
摘要： Partial speed (fine) and full speed (coarse) programming are achieved for a non-volatile memory system. During a program operation, in a first time period (tl-t3), bit lines of storage elements to be inhibited are pre-charged, while bit line of storage elements to be programmed at a partial speed (fine programming) and bit lines of storage elements to be programmed at a full speed (coarse programming) are fixed at ground potential. In a second time period (t4-t5), the bit lines of storage elements to be programmed at the partial speed are driven higher, while the bit lines of storage elements to be inhibited are floated and the bit line of storage elements to be programmed remain grounded. In a third time period (t5-t8), the bit lines of storage elements to be inhibited are driven higher while the bit lines of the storage elements to be programmed at the partial speed or the full speed are floated so that they couple higher.
摘要翻译：对于非易失性存储器系统，实现了部分速度（精细）和全速（粗略）编程。在编程操作期间，在第一时间段（t1-t3）中，要禁止的存储元件的位线被预充电，而要以部分速度（精细编程）编程的存储元件的位线和位线以全速编程的存储元件（粗略编程）固定在地电位。在第二时间段（t4-t5）中，以部分速度编程的存储元件的位线被驱动得较高，而要被禁止的存储元件的位线被浮置，并且存储元件的位线被编程保持接地。在第三时间段（t5-t8）中，待被禁止的存储元件的位线被驱动得较高，而以部分速度或全速编程的存储元件的位线被浮动，使得它们耦合得更高。

4. 发明申请

WO2008036609A2 IMPLEMENTATION OF OUTPUT FLOATING SCHEME FOR HV CHARGE PUMPS 审中-公开
标题翻译：高压充电泵输出浮动方案的实现
公开(公告)号：WO2008036609A2
公开(公告)日：2008-03-27
申请号：PCT/US2007/078667
申请日：2007-09-17
申请人： SANDISK CORPORATION , GOVINDU, Prashanti , PAN, Feng , MUI, Man , KWON, Gyuwan , PHAM, Trung , WANG, Chi-Ming
发明人： GOVINDU, Prashanti , PAN, Feng , MUI, Man , KWON, Gyuwan , PHAM, Trung , WANG, Chi-Ming
CPC分类号： G11C16/30 , G11C5/145
摘要： According to different embodiments of the present invention, various methods, devices and systems are described for managing power in charge pumps in a non-volatile memory system having a high voltage charge pump and associated regulator. A method includes the following operations, receiving an operation command corresponding to an operation, pumping up a charge pump output voltage to a desired output voltage, turning off the regulator and the charge pump when the output voltage is approximately the desired output voltage compensating for charge sharing by turning on the charge pump and setting a pump clock rate to a slow clock rate in order to avoid overshooting the desired output voltage by the charge pump while the operation is being carried out, and compensating for junction leakage by turning on the regulator and the charge pump until the charge pump output voltage is the desired output voltage.
摘要翻译：根据本发明的不同实施例，描述了用于管理具有高电压电荷泵和相关联的调节器的非易失性存储器系统中的电荷泵中的功率的各种方法，设备和系统。一种方法包括以下操作：接收对应于操作的操作命令，将电荷泵输出电压上升到期望的输出电压，当输出电压近似为补偿电荷的期望输出电压时关闭调节器和电荷泵通过打开电荷泵并将泵时钟速率设置为较慢的时钟速率来共享，以避免在执行操作时通过电荷泵超出期望的输出电压，并且通过接通调节器来补偿结泄漏并且电荷泵，直到电荷泵输出电压是所需的输出电压。

5. 发明申请

WO2013074516A1 IMPROVED READ OPERATION FOR NON-VOLATILE STORAGE SYSTEM WITH NAND STRINGS SHARING BIT LINE AND WORD LINES 审中-公开
标题翻译：改进非易失存储系统的读取操作，具有共享字线和字线的NAND条
公开(公告)号：WO2013074516A1
公开(公告)日：2013-05-23
申请号：PCT/US2012/064818
申请日：2012-11-13
申请人： SANDISK TECHNOLOGIES, INC. , MOKHLESI, Nima , DUNGA, Mohan, V. , MUI, Man
发明人： MOKHLESI, Nima , DUNGA, Mohan, V. , MUI, Man
IPC分类号： G11C11/56 , G11C16/04 , G11C16/26 , G11C16/34 , H01L27/115
CPC分类号： G11C16/26 , G11C11/5642 , G11C16/0483 , G11C16/24 , G11C16/3427 , H01L27/11524
摘要： A non-volatile storage system is disclosed that includes pairs of NAND strings (or other groupings of memory cells) in the same block being connected to and sharing a common bit line. To operate the system, two selection lines are used so that the NAND strings (or other groupings of memory cells) sharing a bit line can be selected at the block level. Both selection lines are connected to a selection gate for each of the NAND strings (or other groupings of memory cells) sharing the bit line. One set of embodiments avoid unwanted boosting during read operations by keeping the channels of the memory cells connected to word lines on the drain side of the selected word line biased at a fixed potential.
摘要翻译：公开了一种非易失性存储系统，其包括连接到共享位线的同一块中的NAND串（或存储器单元的其它组）对。为了操作该系统，使用两条选择线，使得可以在块级选择共享位线的NAND串（或存储器单元的其它分组）。两个选择线连接到共享位线的每个NAND串（或存储器单元的其它组）的选择门。一组实施例通过将存储器单元的通道与所选择的字线的漏极侧的字线连接以偏置固定电位来避免读取操作期间的不希望的升压。

6. 发明公开

EP2374133A1 SENSING CIRCUIT AND METHOD WITH REDUCED SUSCEPTIBILITY TO SPATIAL AND TEMPERATURE VARIATIONS 有权
标题翻译：测量电路和方法在降低灵敏度的空间和温度波动
公开(公告)号：EP2374133A1
公开(公告)日：2011-10-12
申请号：EP09801895.5
申请日：2009-12-29
申请人： Sandisk Corporation
发明人： DUNGA, Mohan, Vamsi , MUI, Man , HIGASHITANI, Masaaki
IPC分类号： G11C11/56 , G11C16/26
CPC分类号： G11C11/5642 , G11C16/26
摘要： A sense amplifier is disclosed. One embodiment is a sensing circuit (106) that includes a sensing device (104) and a sense transistor (287) coupled to the sensing device. A first switch (288) that is coupled to the sense transistor and to the sensing device causes the sensing device to be charged to a first voltage that is a function of the threshold voltage of the sense transistor. One or more second switches (282, 293, 291, 289) that are coupled to the sensing device and to a target element (10). The second switches couple the sensing device to the target element to modify the first voltage on the sensing device and decouple the target element from the sensing device during a sense phase in which the modified first voltage is applied to the sense transistor. A condition of the target element is determined based on whether or not the sense transistor turns on in response to applying the modified first voltage to the sense transistor.

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