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1. 发明授权

US06819190B2 Robust fractional clock-based pulse generator for digital pulse width modulator 有权
$Robust fractional clock-based pulse generator for digital pulse width modulator$
公开(公告)号：US06819190B2
公开(公告)日：2004-11-16
申请号：US10315836
申请日：2002-12-10
申请人： Lawrence G. Pearce , William David Bartlett
发明人： Lawrence G. Pearce , William David Bartlett
IPC分类号： H03B2700
CPC分类号： H03L7/0805 , H03K5/06 , H03K7/08 , H03L7/0812
摘要： A tapped delay line generates a fractional clock pulse signal for controlling a PWM pulse generator, such as used in a DC-DC converter. Operational parameters of the tapped delay are adjusted to maintain a desired fractional precision of the duty-cycle of the PWM clock pulse signal. In a first, phase locked loop (PLL) based embodiment, the tapped delay line-based digital PWM pulse generator includes a compensating phase locked-loop formed around an auxiliary tapped delay line that implements the voltage controlled oscillator of the PLL. In a second embodiment, the PWM pulse generator is configured as an ‘open-loop’ tapped delay line phase detector architecture, which avoids having to correlate parameters of the PLL delay line with those of the PWM delay line.

2. 发明授权

US07612465B2 Power supply circuit containing multiple DC-DC converters having programmable output current capabilities 失效
标题翻译：电源电路包含具有可编程输出电流能力的多个DC-DC转换器
公开(公告)号：US07612465B2
公开(公告)日：2009-11-03
申请号：US12041503
申请日：2008-03-03
申请人： Lawrence G. Pearce
发明人： Lawrence G. Pearce
IPC分类号： H02B1/24 , H01H9/54 , H02J1/00
CPC分类号： H02M3/1584 , H02M2001/008 , Y10T307/305 , Y10T307/352 , Y10T307/391 , Y10T307/406 , Y10T307/414 , Y10T307/747 , Y10T307/76 , Y10T307/865 , Y10T307/944
摘要： A apparatus and method of operating a power converter circuit is provided. The method selectively couples control signals to at least one output driver stage of a plurality of output driver stages of the power converter circuit to obtain a desired output at a select output port of the plurality of output ports. Wherein each output driver stage has a defined current drive capacity that is output to the select output port in response to the control signals.
摘要翻译：提供了一种操作电源转换器电路的装置和方法。该方法将控制信号选择性地耦合到功率转换器电路的多个输出驱动级的至少一个输出驱动级，以在多个输出端口的选择输出端口处获得期望的输出。其中每个输出驱动级具有定义的当前驱动能力，其响应于控制信号被输出到选择输出端口。

3. 发明授权

US07206343B2 High resolution digital pulse width modulator for DC-DC voltage converter 有权
标题翻译：用于DC-DC电压转换器的高分辨率数字脉宽调制器
公开(公告)号：US07206343B2
公开(公告)日：2007-04-17
申请号：US10350599
申请日：2003-01-24
申请人： Lawrence G. Pearce
发明人： Lawrence G. Pearce
IPC分类号： H03H7/30 , H03K5/159
CPC分类号： H03K5/133 , H02M3/157 , H03K7/08 , H03K2005/00058 , H03L7/00
摘要： A digitally-implemented pulse width modulation (PWM) signal generator forms the PWM pulse width as a rational number based on full cycles of a PWM reference clock, and offers a very high effective resolution of the PWM pulse signal that is compatible with multiphase DC-DC converters. Being totally digital allows digital error accumulation and correction to occur at the point of origin of the PWM signal, well upstream of the relatively slow voltage control feedback loop. Quantization errors are corrected before they can accumulate in the converter's DC output voltage.
摘要翻译：数字实现的脉冲宽度调制（PWM）信号发生器基于PWM参考时钟的全周期形成PWM脉冲宽度作为有理数，并提供与多相DC-DC相兼容的PWM脉冲信号的非常高的有效分辨率， DC转换器。完全数字化允许数字错误累积和校正发生在PWM信号的原点，在相对较慢的电压控制反馈回路的上游。量化误差在它们可以在转换器的直流输出电压中积累之前被校正。

4. 发明授权

US07076070B2 Monolithic class D amplifier 失效
标题翻译：单片D类放大器
公开(公告)号：US07076070B2
公开(公告)日：2006-07-11
申请号：US10738590
申请日：2003-12-15
申请人： Lawrence G. Pearce , Donald F. Hemmenway
发明人： Lawrence G. Pearce , Donald F. Hemmenway
IPC分类号： H03F21/00 , H03F3/38 , H03F3/217 , H04R3/00 , H01L29/76
CPC分类号： H01L21/8234 , H01L21/8249 , H01L27/0207 , H01L27/0623 , H01L27/0922 , H01L29/0615 , H01L29/0696 , H01L29/1095 , H01L29/4238 , H01L29/456 , H01L29/665 , H01L29/66719 , H01L29/7809 , H01L29/7811 , H01L29/7815 , H03F1/523 , H03F3/187 , H03F3/217 , H03F3/2171 , H03F3/2173 , H03F3/72
摘要： A monolithic 1.75 is mounted in a speaker cabinet 1.71 to drive the voice coil 1.74 of the speaker 1.70. The monolithic integrated circuit may be a class D amplifier 1.10, and is at least a half-bridge or full bridge power MOSFET device. Structures and process for forming the mos switching devices 2.20 of the bridge driver circuits are disclosed. Also disclosed is the N+ buried layer 4.14 of the QVDMOS transistors 4.43 of the bridge circuits.
摘要翻译：单体1.75安装在扬声器箱1.71中以驱动扬声器1.70的音圈1.74。单片集成电路可以是D类放大器1.10，并且是至少一个半桥或全桥功率MOSFET器件。公开了用于形成桥式驱动器电路的mos开关器件2.20的结构和工艺。还公开了桥接电路的QVDMOS晶体管4.43的N +掩埋层4.14。

5. 发明授权

US5837553A Method of making high voltage, junction isolation semiconductor device having dual conductivity type buried regions 失效
标题翻译：制造具有双重导电型掩埋区域的高电压，结隔离半导体器件的方法
公开(公告)号：US5837553A
公开(公告)日：1998-11-17
申请号：US683599
申请日：1996-07-15
申请人： Lawrence G. Pearce
发明人： Lawrence G. Pearce
IPC分类号： H01L21/331 , H01L21/74 , H01L21/761 , H01L21/265
CPC分类号： H01L29/66272 , H01L21/74 , H01L21/761 , Y10S148/01 , Y10S148/011
摘要： A two masking level process for a dual buried region epitaxial architecture forms a first masking layer on a surface of a P type substrate. The first masking layer exposes first and second surface portions of the substrate for N+ and P+ buried regions. N type impurities are introduced into the substrate through the first masking layer, so as to form N+ doped regions. A second masking layer is then selectively formed on the first masking layer, such that the second masking layer masks the first aperture, but exposes a second portion of the first masking layer that both includes and surrounds the second aperture. Boron impurities are then introduced through the exposed second aperture of the first masking layer, to a P+ doping concentration. That portion of the first masking layer surrounding the second aperture is removed, and boron impurities are then introduced into exposed second and third surface portions of the substrate, thereby forming a third buried region of the second conductivity type that is adjacent to the second doped region. The composite mask is removed from the substrate, and an N type layer is grown. Due to differences in diffusion coefficients, the P dopant (boron) in the second and third buried regions outruns the N dopant in the second buried region, resulting in the formation of an N+ buried region that is encapsulated in a P+ buried region. The P+ buried region is, in turn, laterally surrounded by a P-type buried region, so as to provide the desired compensation of N ions that are autodoped from the first N+ buried region in the epitaxial layer.
摘要翻译：用于双掩埋区域外延结构的两个掩模级处理在P型衬底的表面上形成第一掩模层。第一掩蔽层暴露衬底的第一和第二表面部分用于N +和P +掩埋区域。通过第一掩模层将N型杂质引入衬底中，以形成N +掺杂区域。然后在第一掩蔽层上选择性地形成第二掩模层，使得第二掩蔽层掩蔽第一孔，但暴露第一掩蔽层的第二部分，其包括并包围第二孔。然后将硼杂质通过第一掩模层的暴露的第二孔引入P +掺杂浓度。去除围绕第二孔的第一掩蔽层的那部分，然后将硼杂质引入衬底的暴露的第二和第三表面部分中，从而形成与第二掺杂区相邻的第二导电类型的第三掩埋区。从衬底上去除复合掩模，并生长N型层。由于扩散系数的差异，第二和第三掩埋区域中的P掺杂剂（硼）超出第二掩埋区域中的N掺杂剂，导致形成封装在P +掩埋区域中的N +掩埋区域。 P +掩埋区又被P型掩埋区横向围绕，从而提供从外延层中的第一N +掩埋区自动掺杂的N离子的期望补偿。

6. 发明授权

US5648678A Programmable element in barrier metal device 失效
标题翻译：阻挡金属器件中的可编程元件
公开(公告)号：US5648678A
公开(公告)日：1997-07-15
申请号：US310280
申请日：1994-09-21
申请人： Patrick A. Begley , John T. Gasner , Lawrence G. Pearce , Choong S. Rhee , Jeanne M. McNamara , John J. Hackenberg , Donald F. Hemmenway
发明人： Patrick A. Begley , John T. Gasner , Lawrence G. Pearce , Choong S. Rhee , Jeanne M. McNamara , John J. Hackenberg , Donald F. Hemmenway
IPC分类号： H01L23/525 , H01L27/102 , H01L29/00
CPC分类号： H01L27/1021 , H01L23/5252 , H01L2924/0002 , Y10S257/926
摘要： An integrated circuit 10 has a programmable Zener diode with diffusion regions 18 and 16 and metal contacts 34 and 32. A barrier metal 30 is disposed between one contact 32 and the substrate 12; another contact region 18 has no barrier metal on its surface. A polysilicon layer 22 is self-aligned with surface regions 18 and diffusion region 18. A silicide layer 128 may be used on the polysilicon layer 22 and on surface region 18.
摘要翻译：集成电路10具有可扩展区域18和16以及金属触点34和32的可编程齐纳二极管。阻挡金属30设置在一个触点32和基板12之间; 另一个接触区域18在其表面上没有阻挡金属。多晶硅层22与表面区域18和扩散区域18自对准。硅化物层128可以用在多晶硅层22上和表面区域18上。

7. 发明授权

US4818725A Technique for forming planarized gate structure 失效
标题翻译：形成平面化栅极结构的技术
公开(公告)号：US4818725A
公开(公告)日：1989-04-04
申请号：US224320
申请日：1988-07-26
申请人： Richard L. Lichtel, Jr. , Lawrence G. Pearce , Dryer A. Matlock
发明人： Richard L. Lichtel, Jr. , Lawrence G. Pearce , Dryer A. Matlock
IPC分类号： H01L21/033 , H01L21/28 , H01L21/336 , H01L21/22 , H01L21/265
CPC分类号： H01L29/66583 , H01L21/033 , H01L21/28123 , Y10S148/05 , Y10S148/086 , Y10S148/122 , Y10S148/131
摘要： A direct moat wafer processing for maximizing the functional continuity of a field oxide layer employs a processing sequence through which respective differently sized apertures are successively formed in the oxide layer. A first of these apertures prescribes the size of the polysilicon gate, while a second aperture is formed around the completed gate structure and prescribes the geometry of source/drain regions to be introduced into exposed surface areas of the substrate on either side of the gate. The sidewalls of the first and subsequently formed, second aperture are effectively perpendicular to the substrate surface, thereby maintaining the functional continuity of the field oxide layer across the entirety thereof. Thereafter, a separate gate interconnect layer is selectively formed atop the field oxide layer to provide a conductive path to the gate.
摘要翻译：用于最大化场氧化物层的功能连续性的直接护环晶片处理采用处理顺序，通过该处理顺序在氧化物层中连续地形成各自不同尺寸的孔。这些孔中的第一个规定了多晶硅栅极的尺寸，而在完成的栅极结构周围形成第二孔径，并且规定了将源极/漏极区域的几何形状引入栅极两侧的衬底的暴露表面区域中。第一和随后形成的第二孔的侧壁有效地垂直于衬底表面，由此保持场氧化物层在其整体上的功能连续性。此后，单独的栅极互连层选择性地形成在场氧化物层的顶部，以提供到栅极的导电路径。

8. 发明授权

US06946897B2 Technique for measuring temperature and current via a MOSFET of a synchronous buck voltage converter 失效
公开(公告)号：US06946897B2
公开(公告)日：2005-09-20
申请号：US10691370
申请日：2003-10-22
申请人： Lawrence G. Pearce
发明人： Lawrence G. Pearce
IPC分类号： G01K7/01 , H02M3/158 , H03K3/42
CPC分类号： G01K7/01 , H02M3/1588 , H02M2001/0009 , Y02B70/1466
摘要： In order to derive a precise measurement of temperature and current in a synchronous buck DC-DC converter a synchronous conduction cycle measurement of the value of reverse conduction voltage (VON), and an asynchronous conduction cycle measurement of the value of body diode conduction voltage (VDF) of the low side power MOSFET are performed. These two measured values are then used as dual inputs to a two-dimensional to two-dimensional transform function (e.g., look-up table) that is effective to map the measured voltage values into output values for current (I) and temperature (T).

9. 发明授权

US06791304B2 Electronic device including multiphase switching regulator and related methods 失效
标题翻译：电子器件包括多相开关调节器及相关方法
公开(公告)号：US06791304B2
公开(公告)日：2004-09-14
申请号：US10350755
申请日：2003-01-24
申请人： Lawrence G. Pearce , Nicolaas W. Van Vonno
发明人： Lawrence G. Pearce , Nicolaas W. Van Vonno
IPC分类号： G05F1618
CPC分类号： H02J1/102 , H02M3/1584
摘要： An electronic device may include a circuit board, at least one load circuit carried by the circuit board, and a power distribution conductor carried by the circuit board and connected to the at least one load circuit. The electronic device may also include a multiphase switching regulator including a plurality of output stages connected to the power distribution conductor, and a controller for controlling the output stages based upon respective phase currents. The respective phase currents may be derived from corresponding voltage drops across the power distribution conductor and a matrix of resistivity values.
摘要翻译：电子设备可以包括电路板，由电路板承载的至少一个负载电路和由电路板承载并连接到至少一个负载电路的配电导体。电子设备还可以包括多相开关调节器，其包括连接到配电导体的多个输出级，以及用于基于各自的相电流来控制输出级的控制器。相应的相电流可以从功率分布导体上的相应电压降和电阻率值矩阵导出。

10. 发明授权

US5973368A Monolithic class D amplifier 失效
标题翻译：单片D类放大器
公开(公告)号：US5973368A
公开(公告)日：1999-10-26
申请号：US973769
申请日：1997-12-11
申请人： Lawrence G. Pearce , Donald F. Hemmenway
发明人： Lawrence G. Pearce , Donald F. Hemmenway
IPC分类号： H03F99/00 , H01L21/8249 , H01L27/02 , H01L27/06 , H03F1/52 , H03F3/217 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113
CPC分类号： H01L21/8234 , H01L21/8249 , H01L27/0207 , H01L27/0623 , H01L27/0922 , H01L29/0696 , H01L29/4238 , H01L29/66719 , H01L29/7809 , H01L29/7811 , H01L29/7815 , H03F1/523 , H03F3/187 , H03F3/217 , H03F3/2171 , H03F3/2173 , H03F3/72 , H01L29/0615 , H01L29/1095 , H01L29/456 , H01L29/665
摘要： A monolithic integrated circuit is mounted in a speaker cabinet to drive the voice coil of the speaker. The monolithic integrated circuit may be a class D amplifier and is at least a half bridge or full bridge power MOSFET device. Structures comprise MOS switching devices of the bridge driver and N+ buried layer of the QVDMOS transistors of the bridge circuits.
摘要翻译： PCT No.PCT / US96 / 08826 Sec。 371日期：1998年7月27日 102（e）1998年7月27日PCT PCT 1996年6月5日PCT公布。公开号WO96 / 41412 PCT 日期1996年12月19日将单片集成电路安装在扬声器箱中以驱动扬声器的音圈。单片集成电路可以是D类放大器，并且是至少一个半桥或全桥功率MOSFET器件。结构包括桥式驱动器的MOS开关器件和桥式电路的QVDMOS晶体管的N +掩埋层。

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