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1. 发明授权

US08826195B2 Layout modification method and system 有权
标题翻译：布局修改方法和系统
公开(公告)号：US08826195B2
公开(公告)日：2014-09-02
申请号：US13530164
申请日：2012-06-22
申请人： Meng-Xiang Lee , Li-Chung Hsu , Shih-Hsien Yang , Ho Che Yu , King-Ho Tam , Chung-Hsing Wang
发明人： Meng-Xiang Lee , Li-Chung Hsu , Shih-Hsien Yang , Ho Che Yu , King-Ho Tam , Chung-Hsing Wang
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5031 , G06F2217/02 , G06F2217/78 , G06F2217/84
摘要： A method comprises providing a non-transitory, machine-readable storage medium storing a partial netlist of at least a portion of a previously taped-out integrated circuit (IC) layout, representing a set of photomasks for fabricating an IC having the IC layout such that the IC meets a first specification value. A computer identifies a proper subset of a plurality of first devices in the IC layout, such that replacement of the proper subset of the first devices by second devices in a revised IC layout satisfies a second specification value different from the first specification value. At least one layout mask is generated and stored in at least one non-transitory machine readable storage medium, accessible by a tool for forming at least one additional photomask, such that the set of photomasks and the at least one additional photomask are usable to fabricate an IC according to the revised IC layout.
摘要翻译：一种方法包括提供一种非暂时的机器可读存储介质，其存储至少部分先前采集的集成电路（IC）布局的部分网表，其表示用于制造具有IC布局的IC的一组光掩模，该IC满足第一规格值。计算机识别IC布局中的多个第一设备的正确子集，使得经修订的IC布局中的第二设备对第一设备的正确子集的替换满足与第一规范值不同的第二规范值。至少一个布局掩模被生成并存储在至少一个非暂时机器可读存储介质中，可由用于形成至少一个附加光掩模的工具访问，使得该组光掩模和至少一个附加光掩模可用于制造一个IC根据修订的IC布局。

2. 发明授权

US09311440B2 System and method of electromigration avoidance for automatic place-and-route 有权
标题翻译：自动放置路由的电迁移避免系统和方法
公开(公告)号：US09311440B2
公开(公告)日：2016-04-12
申请号：US13468055
申请日：2012-05-10
申请人： Jerry Kao , King-Ho Tam , Meng-Xiang Lee , Li-Chung Hsu , Chi-Yeh Yu , Chung-Min Fu , Chung-Hsing Wang
发明人： Jerry Kao , King-Ho Tam , Meng-Xiang Lee , Li-Chung Hsu , Chi-Yeh Yu , Chung-Min Fu , Chung-Hsing Wang
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F17/5077 , G06F2217/76
摘要： A method includes identifying at least one local power segment of a circuit, estimating at least one performance parameter of the at least one power segment based on a computer-based simulation of the circuit, and changing a design of the circuit based on at least one electromigration avoidance strategy if the at least one parameter is greater than or equal to a threshold value. A data file representing the circuit is stored if the at least one parameter is less than the threshold value.
摘要翻译：一种方法包括识别电路的至少一个局部电力部分，基于电路的基于计算机的仿真来估计所述至少一个电力部分的至少一个性能参数，以及基于至少一个电路来改变所述电路的设计如果至少一个参数大于或等于阈值，则电迁移避免策略。如果至少一个参数小于阈值，则存储表示电路的数据文件。

3. 发明授权

US08694945B2 Automatic place and route method for electromigration tolerant power distribution 有权
标题翻译：用于电迁移容量配电的自动放置和布线方法
公开(公告)号：US08694945B2
公开(公告)日：2014-04-08
申请号：US13331329
申请日：2011-12-20
申请人： Chung-Hsing Wang , King-Ho Tam , Huang-Yu Chen
发明人： Chung-Hsing Wang , King-Ho Tam , Huang-Yu Chen
IPC分类号： G06F17/50 , H01L23/498
CPC分类号： H01L23/5286 , G06F17/5072 , G06F17/5077 , G06F2217/78 , H01L2027/11881 , H01L2924/0002 , H01L2924/00
摘要： The present disclosure relates to an electromigration tolerant power distribution network generated by an automatic place and route (APR) methodology. In some embodiments, an automatic place and route tool constructs a local power network having multi-level power rails. The multi-level power rails have interleaved segments of vertically adjacent metal layers, wherein each interleaved segment is shorter than a predetermined characteristic length corresponding to a Blech length. By limiting the length of the interleaved metallization segments, electromigration within the multi-level power rails is alleviated, allowing for the maximum current density requirement (Jmax) for mean time to failures (MTTF) to be increased.
摘要翻译：本公开涉及通过自动位置和路由（APR）方法产生的电迁移容限配电网络。在一些实施例中，自动放置和路由工具构建具有多级电源轨的本地电力网络。多级电源轨具有交错的垂直相邻金属层的段，其中每个交错段短于对应于Blech长度的预定特征长度。通过限制交错金属化段的长度，多级电力轨道内的电迁移得到缓解，允许增加平均故障时间（MTTF）的最大电流密度要求（Jmax）。

4. 发明授权

US08543954B1 Concurrent noise and delay modeling of circuit stages for static timing analysis of integrated circuit designs 有权
标题翻译：用于集成电路设计的静态时序分析的电路级并发噪声和延迟建模
公开(公告)号：US08543954B1
公开(公告)日：2013-09-24
申请号：US12203115
申请日：2008-09-02
申请人： Igor Keller , Vinod Kariat , King Ho Tam
发明人： Igor Keller , Vinod Kariat , King Ho Tam
IPC分类号： G06F17/50 , G06F17/10
CPC分类号： G06F17/5036 , G06F17/5031 , G06F2217/82 , G06F2217/84
摘要： Systems, apparatus, and methods of static timing analysis for an integrated circuit design in the presence of noise are disclosed. The integrated circuit design undergoing analysis may be partitioned into a plurality of subcircuit stages. Each subcircuit stage in the integrated circuit design may be modeled to include a model of at least one victim driver, at least one aggressor driver, at least one receiver, and an interconnect network. Associated with each subcircuit stage is a set of related edges of a design graph to compute signal propagation delay. For each subcircuit stage, full timing delays of each edge can be concurrently computed. This includes concurrently computing base timing delays for a nominal response to the at least one victim driver and the interconnect network and noise related timing delays in response to the at least one aggressor driver and the interconnect network.
摘要翻译：公开了在存在噪声的情况下用于集成电路设计的静态时序分析的系统，装置和方法。经历分析的集成电路设计可以被划分成多个子电路级。集成电路设计中的每个子电路阶段可以被建模为包括至少一个受害者驱动器，至少一个攻击者驱动器，至少一个接收器和互连网络的模型。与每个子电路阶段相关联的是设计图的一组相关边缘，用于计算信号传播延迟。对于每个子电路阶段，可以同时计算每个边缘的完整定时延迟。这包括响应于至少一个攻击者驱动器和互连网络同时计算对至少一个受害者驱动器和互连网络的标称响应的基本时序延迟和噪声相关的定时延迟。

5. 发明申请

US20130154128A1 Automatic Place and Route Method for Electromigration Tolerant Power Distribution 有权
标题翻译：自动放置和路由方法的电迁移容错配电
公开(公告)号：US20130154128A1
公开(公告)日：2013-06-20
申请号：US13331329
申请日：2011-12-20
申请人： Chung-Hsing Wang , King-Ho Tam , Huang-Yu Chen
发明人： Chung-Hsing Wang , King-Ho Tam , Huang-Yu Chen
IPC分类号： H01L23/498 , G06F17/50
CPC分类号： H01L23/5286 , G06F17/5072 , G06F17/5077 , G06F2217/78 , H01L2027/11881 , H01L2924/0002 , H01L2924/00
摘要： The present disclosure relates to an electromigration tolerant power distribution network generated by an automatic place and route (APR) methodology. In some embodiments, an automatic place and route tool constructs a local power network having multi-level power rails. The multi-level power rails have interleaved segments of vertically adjacent metal layers, wherein each interleaved segment is shorter than a predetermined characteristic length corresponding to a Blech length. By limiting the length of the interleaved metallization segments, electromigration within the multi-level power rails is alleviated, allowing for the maximum current density requirement (Jmax) for mean time to failures (MTTF) to be increased.
摘要翻译：本公开涉及通过自动位置和路由（APR）方法产生的电迁移容限配电网络。在一些实施例中，自动放置和路由工具构建具有多级电源轨的本地电力网络。多级电源轨具有交错的垂直相邻金属层的段，其中每个交错段短于对应于Blech长度的预定特征长度。通过限制交错金属化段的长度，多级电力轨道内的电迁移得到缓解，允许增加平均故障时间（MTTF）的最大电流密度要求（Jmax）。

6. 发明申请

US20130326438A1 LAYOUT MODIFICATION METHOD AND SYSTEM 有权
标题翻译：布局修改方法和系统
公开(公告)号：US20130326438A1
公开(公告)日：2013-12-05
申请号：US13530164
申请日：2012-06-22
申请人： Meng-Xiang LEE , Li-Chung HSU , Shih-Hsien YANG , Ho Che YU , King-Ho TAM , Chung-Hsing WANG
发明人： Meng-Xiang LEE , Li-Chung HSU , Shih-Hsien YANG , Ho Che YU , King-Ho TAM , Chung-Hsing WANG
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5031 , G06F2217/02 , G06F2217/78 , G06F2217/84
摘要： A method comprises providing a non-transitory, machine-readable storage medium storing a partial netlist of at least a portion of a previously taped-out integrated circuit (IC) layout, representing a set of photomasks for fabricating an IC having the IC layout such that the IC meets a first specification value. A computer identifies a proper subset of a plurality of first devices in the IC layout, such that replacement of the proper subset of the first devices by second devices in a revised IC layout satisfies a second specification value different from the first specification value. At least one layout mask is generated and stored in at least one non-transitory machine readable storage medium, accessible by a tool for forming at least one additional photomask, such that the set of photomasks and the at least one additional photomask are usable to fabricate an IC according to the revised IC layout.
摘要翻译：一种方法包括提供一种非暂时的机器可读存储介质，其存储至少部分先前采集的集成电路（IC）布局的部分网表，其表示用于制造具有IC布局的IC的一组光掩模，该IC满足第一规格值。计算机识别IC布局中的多个第一设备的正确子集，使得经修订的IC布局中的第二设备对第一设备的正确子集的替换满足与第一规范值不同的第二规范值。至少一个布局掩模被生成并存储在至少一个非暂时机器可读存储介质中，可由用于形成至少一个附加光掩模的工具访问，使得该组光掩模和至少一个附加光掩模可用于制造一个IC根据修订的IC布局。

7. 发明授权

US08499274B2 Computer implemented system and method for leakage calculation 有权
标题翻译：计算机实现系统和泄漏计算方法
公开(公告)号：US08499274B2
公开(公告)日：2013-07-30
申请号：US13403289
申请日：2012-02-23
申请人： Chien-Ju Chao , Jerry Chang-Jui Kao , King-Ho Tam , Chung-Hsing Wang , Huan Chi Tseng
发明人： Chien-Ju Chao , Jerry Chang-Jui Kao , King-Ho Tam , Chung-Hsing Wang , Huan Chi Tseng
IPC分类号： G06F17/50 , G06F9/455 , G06G7/48
CPC分类号： G06F17/5022
摘要： A tool includes one or more machine readable storage mediums encoded with data. The data include a list of standard cells included in an integrated circuit (IC) design The data include a nominal leakage value approximating a respective median leakage value for each of the plurality of standard cells at a predetermined temperature and voltage. The data include at least one table including adjustment factors for calculating leakage based on voltage, temperature and process variations. The table includes a respective statistical scaling factor, for computing a mean leakage corresponding to a given median leakage. A processor is programmed to calculate and output a total IC leakage for the IC design at an input voltage and input temperature, based on the list, the nominal leakage values, the input voltage, the input temperature and at least one of the adjustment factors.
摘要翻译：工具包括用数据编码的一个或多个机器可读存储介质。数据包括集成电路（IC）设计中包括的标准单元的列表。数据包括在预定温度和电压下接近多个标准单元中的每一个的相应中值泄漏值的标称泄漏值。数据包括至少一个表，其中包括基于电压，温度和过程变化来计算泄漏的调整因子。该表包括相应的统计缩放因子，用于计算对应于给定中位泄漏的平均泄漏。处理器被编程为基于列表，标称泄漏值，输入电压，输入温度和至少一个调整因子来计算并输出IC设计中的IC设计的总IC泄漏，输入电压和输入温度。

8. 发明申请

US20130139120A1 COMPUTER IMPLEMENTED SYSTEM AND METHOD FOR LEAKAGE CALCULATION 有权
标题翻译：计算机实现系统和泄漏计算方法
公开(公告)号：US20130139120A1
公开(公告)日：2013-05-30
申请号：US13403289
申请日：2012-02-23
申请人： Chien-Ju Chao , Jerry Chang-Jui Kao , King-Ho Tam , Chung-Hsing Wang , Huan Chi Tseng
发明人： Chien-Ju Chao , Jerry Chang-Jui Kao , King-Ho Tam , Chung-Hsing Wang , Huan Chi Tseng
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： A tool includes one or more machine readable storage mediums encoded with data. The data include a list of standard cells included in an integrated circuit (IC) design The data include a nominal leakage value approximating a respective median leakage value for each of the plurality of standard cells at a predetermined temperature and voltage. The data include at least one table including adjustment factors for calculating leakage based on voltage, temperature and process variations. The table includes a respective statistical scaling factor, for computing a mean leakage corresponding to a given median leakage. A processor is programmed to calculate and output a total IC leakage for the IC design at an input voltage and input temperature, based on the list, the nominal leakage values, the input voltage, the input temperature and at least one of the adjustment factors.
摘要翻译：工具包括用数据编码的一个或多个机器可读存储介质。数据包括集成电路（IC）设计中包括的标准单元的列表。数据包括在预定温度和电压下接近多个标准单元中的每一个的相应中值泄漏值的标称泄漏值。数据包括至少一个表，其中包括基于电压，温度和过程变化来计算泄漏的调整因子。该表包括相应的统计缩放因子，用于计算对应于给定中位泄漏的平均泄漏。处理器被编程为基于列表，标称泄漏值，输入电压，输入温度和至少一个调整因子来计算并输出IC设计中的IC设计的总IC泄漏，输入电压和输入温度。

9. 发明申请

US20130304449A1 SYSTEM AND METHOD OF ELECTROMIGRATION AVOIDANCE FOR AUTOMATIC PLACE-AND- ROUTE 有权
标题翻译：用于自动布置和路由的电气避雷系统和方法
公开(公告)号：US20130304449A1
公开(公告)日：2013-11-14
申请号：US13468055
申请日：2012-05-10
申请人： Jerry KAO , King-Ho TAM , Meng-Xiang LEE , Li-Chung HSU , Chi-Yeh YU , Chung-Min FU , Chung-Hsing WANG
发明人： Jerry KAO , King-Ho TAM , Meng-Xiang LEE , Li-Chung HSU , Chi-Yeh YU , Chung-Min FU , Chung-Hsing WANG
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F17/5077 , G06F2217/76
摘要： A method includes identifying at least one local power segment of a circuit, estimating at least one performance parameter of the at least one power segment based on a computer-based simulation of the circuit, and changing a design of the circuit based on at least one electromigration avoidance strategy if the at least one parameter is greater than or equal to a threshold value. A data file representing the circuit is stored if the at least one parameter is less than the threshold value.
摘要翻译：一种方法包括识别电路的至少一个局部电力部分，基于电路的基于计算机的仿真来估计所述至少一个电力部分的至少一个性能参数，以及基于至少一个电路来改变所述电路的设计如果至少一个参数大于或等于阈值，则电迁移避免策略。如果至少一个参数小于阈值，则存储表示电路的数据文件。

10. 发明授权

US08533644B1 Multi-CCC current source models and static timing analysis methods for integrated circuit designs 有权
标题翻译：多CCC电流源模型和集成电路设计的静态时序分析方法
公开(公告)号：US08533644B1
公开(公告)日：2013-09-10
申请号：US12965886
申请日：2010-12-12
申请人： Vinod Kariat , Igor Keller , Joel R. Phillips , King Ho Tam
发明人： Vinod Kariat , Igor Keller , Joel R. Phillips , King Ho Tam
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5036 , G06F2217/84
摘要： In one embodiment of the invention, a multi-CCC current source model is disclosed to perform statistical timing analysis of an integrated circuit design. The multi-CCC current source model includes a voltage waveform transfer function, a voltage dependent current source, and an output capacitor. The voltage waveform transfer function receives an input voltage waveform and transforms it into an intermediate voltage waveform. The voltage dependent current source generates an output current in response to the intermediate voltage waveform. The output capacitor is coupled in parallel to the voltage dependent current source to generate an output voltage waveform for computation of a timing delay.
摘要翻译：在本发明的一个实施例中，公开了一种多CCC电流源模型来执行集成电路设计的统计时序分析。多CCC电流源模型包括电压波形传递函数，电压相关电流源和输出电容器。电压波形传递函数接收输入电压波形并将其转换为中间电压波形。电压相关电流源响应于中间电压波形产生输出电流。输出电容器并联到与电压相关的电流源，以产生用于计算定时延迟的输出电压波形。

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