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1. 发明授权

US08533644B1 Multi-CCC current source models and static timing analysis methods for integrated circuit designs 有权
标题翻译：多CCC电流源模型和集成电路设计的静态时序分析方法
公开(公告)号：US08533644B1
公开(公告)日：2013-09-10
申请号：US12965886
申请日：2010-12-12
申请人： Vinod Kariat , Igor Keller , Joel R. Phillips , King Ho Tam
发明人： Vinod Kariat , Igor Keller , Joel R. Phillips , King Ho Tam
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5036 , G06F2217/84
摘要： In one embodiment of the invention, a multi-CCC current source model is disclosed to perform statistical timing analysis of an integrated circuit design. The multi-CCC current source model includes a voltage waveform transfer function, a voltage dependent current source, and an output capacitor. The voltage waveform transfer function receives an input voltage waveform and transforms it into an intermediate voltage waveform. The voltage dependent current source generates an output current in response to the intermediate voltage waveform. The output capacitor is coupled in parallel to the voltage dependent current source to generate an output voltage waveform for computation of a timing delay.
摘要翻译：在本发明的一个实施例中，公开了一种多CCC电流源模型来执行集成电路设计的统计时序分析。多CCC电流源模型包括电压波形传递函数，电压相关电流源和输出电容器。电压波形传递函数接收输入电压波形并将其转换为中间电压波形。电压相关电流源响应于中间电压波形产生输出电流。输出电容器并联到与电压相关的电流源，以产生用于计算定时延迟的输出电压波形。

2. 发明授权

US08516420B1 Sensitivity and static timing analysis for integrated circuit designs using a multi-CCC current source model 有权
标题翻译：使用多CCC电流源模型的集成电路设计的灵敏度和静态时序分析
公开(公告)号：US08516420B1
公开(公告)日：2013-08-20
申请号：US11849254
申请日：2007-08-31
申请人： Vinod Kariat , Igor Keller , Joel R. Phillips , King Ho Tam
发明人： Vinod Kariat , Igor Keller , Joel R. Phillips , King Ho Tam
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5036 , G06F2217/84
摘要： In one embodiment of the invention, a multi-CCC current source model is disclosed to perform statistical timing analysis of an integrated circuit design. The multi-CCC current source model includes a voltage waveform transfer function, a voltage dependent current source, and an output capacitor. The voltage waveform transfer function receives an input voltage waveform and transforms it into an intermediate voltage waveform. The voltage dependent current source generates an output current in response to the intermediate voltage waveform. The output capacitor is coupled in parallel to the voltage dependent current source to generate an output voltage waveform for computation of a timing delay.
摘要翻译：在本发明的一个实施例中，公开了一种多CCC电流源模型来执行集成电路设计的统计时序分析。多CCC电流源模型包括电压波形传递函数，电压相关电流源和输出电容器。电压波形传递函数接收输入电压波形并将其转换为中间电压波形。电压相关电流源响应于中间电压波形产生输出电流。输出电容器并联到与电压相关的电流源，以产生用于计算定时延迟的输出电压波形。

3. 发明授权

US08595669B1 Flexible noise and delay modeling of circuit stages for static timing analysis of integrated circuit designs 有权
标题翻译：集成电路设计的静态时序分析的电路级灵活噪声和延迟建模
公开(公告)号：US08595669B1
公开(公告)日：2013-11-26
申请号：US12203128
申请日：2008-09-02
申请人： Igor Keller , Vinod Kariat , King Ho Tam
发明人： Igor Keller , Vinod Kariat , King Ho Tam
IPC分类号： G06F17/50 , G06F17/10
CPC分类号： G06F17/5031 , G06F17/5036 , G06F17/5068 , G06F17/5072 , G06F2217/82 , G06F2217/84
摘要： Systems, apparatus, and methods of static timing analysis for an integrated circuit design in the presence of noise are disclosed. The integrated circuit design may be partitioned into a plurality of circuit stages. A timing graph including timing arcs is constructed to represent the timing delays in circuit stages of the integrated circuit design. A model of each circuit stage may be formed including a model of a victim driver, an aggressor driver, a victim receiver, and a victim net and an aggressor net coupled together. For each timing arc in the timing graph, full timing delays may be computed for the timing arcs in each circuit stage.
摘要翻译：公开了在存在噪声的情况下用于集成电路设计的静态时序分析的系统，装置和方法。集成电路设计可以被划分成多个电路级。包括定时弧的定时图被构造成表示集成电路设计的电路阶段中的时序延迟。可以形成每个电路级的模型，其包括耦合在一起的受害者驱动器，攻击者驱动器，受害者接收器以及受害者网络和侵略者网络的模型。对于定时图中的每个定时电弧，可以为每个电路级中的定时弧计算全定时延迟。

4. 发明授权

US08543954B1 Concurrent noise and delay modeling of circuit stages for static timing analysis of integrated circuit designs 有权
标题翻译：用于集成电路设计的静态时序分析的电路级并发噪声和延迟建模
公开(公告)号：US08543954B1
公开(公告)日：2013-09-24
申请号：US12203115
申请日：2008-09-02
申请人： Igor Keller , Vinod Kariat , King Ho Tam
发明人： Igor Keller , Vinod Kariat , King Ho Tam
IPC分类号： G06F17/50 , G06F17/10
CPC分类号： G06F17/5036 , G06F17/5031 , G06F2217/82 , G06F2217/84
摘要： Systems, apparatus, and methods of static timing analysis for an integrated circuit design in the presence of noise are disclosed. The integrated circuit design undergoing analysis may be partitioned into a plurality of subcircuit stages. Each subcircuit stage in the integrated circuit design may be modeled to include a model of at least one victim driver, at least one aggressor driver, at least one receiver, and an interconnect network. Associated with each subcircuit stage is a set of related edges of a design graph to compute signal propagation delay. For each subcircuit stage, full timing delays of each edge can be concurrently computed. This includes concurrently computing base timing delays for a nominal response to the at least one victim driver and the interconnect network and noise related timing delays in response to the at least one aggressor driver and the interconnect network.
摘要翻译：公开了在存在噪声的情况下用于集成电路设计的静态时序分析的系统，装置和方法。经历分析的集成电路设计可以被划分成多个子电路级。集成电路设计中的每个子电路阶段可以被建模为包括至少一个受害者驱动器，至少一个攻击者驱动器，至少一个接收器和互连网络的模型。与每个子电路阶段相关联的是设计图的一组相关边缘，用于计算信号传播延迟。对于每个子电路阶段，可以同时计算每个边缘的完整定时延迟。这包括响应于至少一个攻击者驱动器和互连网络同时计算对至少一个受害者驱动器和互连网络的标称响应的基本时序延迟和噪声相关的定时延迟。

5. 发明授权

US08104006B2 Method and apparatus for thermal analysis 有权
标题翻译：热分析方法和装置
公开(公告)号：US08104006B2
公开(公告)日：2012-01-24
申请号：US12024002
申请日：2008-01-31
申请人： Vinod Kariat , Igor Keller , Eddy Pramono
发明人： Vinod Kariat , Igor Keller , Eddy Pramono
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F2217/78
摘要： Some embodiments of the invention provide a method for performing thermal analysis of an integrated circuit (“IC”) layout that includes numerous circuit modules. In some embodiments, the method initially defines several power dissipation equations that express the temperature dependence of the power dissipation for several circuit modules. In some embodiments, the power dissipation equations express a non-linear relationship between power dissipation and temperature. The method defines a heat flow equation based on the specified power dissipation equations. The method then solves the heat flow equation to identify a temperature distribution for the design layout.
摘要翻译：本发明的一些实施例提供了一种用于执行包括许多电路模块的集成电路（“IC”）布局的热分析的方法。在一些实施例中，该方法最初定义了几个功率耗散方程，其表示几个电路模块的功率耗散的温度依赖性。在一些实施例中，功耗方程表示功率耗散和温度之间的非线性关系。该方法基于指定的功率耗散方程定义热流方程。该方法然后解决了热流方程，以确定设计布局的温度分布。

6. 发明授权

US08631369B1 Methods, systems, and apparatus for timing and signal integrity analysis of integrated circuits with semiconductor process variations 有权
标题翻译：具有半导体工艺变化的集成电路的定时和信号完整性分析的方法，系统和装置
公开(公告)号：US08631369B1
公开(公告)日：2014-01-14
申请号：US12981504
申请日：2010-12-30
申请人： Vinod Kariat , Joel R. Phillips , Igor Keller
发明人： Vinod Kariat , Joel R. Phillips , Igor Keller
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： In one embodiment of the invention, a method of statically analyzing an integrated circuit with process and environment variations is provided. The method includes characterizing each circuit cell of a cell library for a sensitivity to process parameter variations within a predetermined range; creating a timing graph corresponding to a netlist representing an integrated circuit design; along nodes of the timing graph, computing delay values including sensitivities to process variations; for each selected output node of the netlist, propagating a full timing value function with the sensitivities to the selected output nodes; and generating a parameterized timing report including the sensitivities to the process variations.
摘要翻译：在本发明的一个实施例中，提供了一种静态分析具有过程和环境变化的集成电路的方法。该方法包括表征单元库的每个电路单元以便在预定范围内处理参数变化的灵敏度; 创建对应于表示集成电路设计的网表的时序图; 沿着定时图的节点计算包括对过程变化的敏感度的延迟值; 对于网表的每个选择的输出节点，传播具有对所选输出节点的灵敏度的完整定时值函数; 以及生成包括对所述过程变化的灵敏度的参数化定时报告。

7. 发明申请

US20090199140A1 METHOD AND APPARATUS FOR THERMAL ANALYSIS 有权
标题翻译：用于热分析的方法和装置
公开(公告)号：US20090199140A1
公开(公告)日：2009-08-06
申请号：US12024002
申请日：2008-01-31
申请人： Vinod Kariat , Igor Keller , Eddy Pramono
发明人： Vinod Kariat , Igor Keller , Eddy Pramono
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F2217/78
摘要： Some embodiments of the invention provide a method for performing thermal analysis of an integrated circuit (“IC”) layout that includes numerous circuit modules. In some embodiments, the method initially defines several power dissipation equations that express the temperature dependence of the power dissipation for several circuit modules. In some embodiments, the power dissipation equations express a non-linear relationship between power dissipation and temperature. The method defines a heat flow equation based on the specified power dissipation equations. The method then solves the heat flow equation to identify a temperature distribution for the design layout.
摘要翻译：本发明的一些实施例提供了一种用于执行包括许多电路模块的集成电路（“IC”）布局的热分析的方法。在一些实施例中，该方法最初定义了几个功率耗散方程，其表示几个电路模块的功率耗散的温度依赖性。在一些实施例中，功耗方程表示功率耗散和温度之间的非线性关系。该方法基于指定的功率耗散方程定义热流方程。该方法然后解决了热流方程，以确定设计布局的温度分布。

8. 发明授权

US07882471B1 Timing and signal integrity analysis of integrated circuits with semiconductor process variations 有权
标题翻译：具有半导体工艺变化的集成电路的时序和信号完整性分析
公开(公告)号：US07882471B1
公开(公告)日：2011-02-01
申请号：US11560261
申请日：2006-11-15
申请人： Vinod Kariat , Joel R. Phillips , Igor Keller
发明人： Vinod Kariat , Joel R. Phillips , Igor Keller
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： In one embodiment of the invention, a method of statically analyzing an integrated circuit with process and environment variations is provided. The method includes characterizing each circuit cell of a cell library for a sensitivity to process parameter variations within a predetermined range; creating a timing graph corresponding to a netlist representing an integrated circuit design; along nodes of the timing graph, computing delay values including sensitivities to process variations; for each selected output node of the netlist, propagating a full timing value function with the sensitivities to the selected output nodes; and generating a parameterized timing report including the sensitivities to the process variations.
摘要翻译：在本发明的一个实施例中，提供了一种静态分析具有过程和环境变化的集成电路的方法。该方法包括表征单元库的每个电路单元以便在预定范围内处理参数变化的灵敏度; 创建对应于表示集成电路设计的网表的时序图; 沿着定时图的节点计算包括对过程变化的敏感度的延迟值; 对于网表的每个选择的输出节点，传播具有对所选输出节点的灵敏度的完整定时值函数; 以及生成包括对所述过程变化的灵敏度的参数化定时报告。

9. 发明申请

US20120297357A1 METHOD AND APPARATUS FOR MULTI-DIE THERMAL ANALYSIS 有权
公开(公告)号：US20120297357A1
公开(公告)日：2012-11-22
申请号：US13477006
申请日：2012-05-21
申请人： Eddy Pramono , Yong Zhan , Vinod Kariat
发明人： Eddy Pramono , Yong Zhan , Vinod Kariat
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： Some embodiments of the invention provide a method for performing thermal analysis of a multi-die integrated circuit (IC) design layout. The thermal analysis produces a temperature distribution for analyzing internal properties of each die within the multi-die design and for analyzing thermal interactions between two or more dies of the design based on an internal configuration of the two or more dies. Therefore, in some embodiments, the temperature distribution shows a temperature distribution for each die and the individual temperature distributions show varying temperature across each of the dies. Some embodiments reduce the number of iteration required to perform the thermal analysis by constructing a high quality preconditioner based on thermal conducting segments introduced to model thermal effects at the boundaries between two dies.

10. 发明授权

US08104007B2 Method and apparatus for thermal analysis 有权
标题翻译：热分析方法和装置
公开(公告)号：US08104007B2
公开(公告)日：2012-01-24
申请号：US12144651
申请日：2008-06-24
申请人： Vinod Kariat , Eddy Pramono , Yong Zhan
发明人： Vinod Kariat , Eddy Pramono , Yong Zhan
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F2217/16
摘要： Some embodiments of the invention provide a method for performing thermal analysis of an integrated circuit (“IC”) design layout that includes numerous circuit modules. The method divides the IC design layout into a set of elements, where at least one element includes several wires. The method computes a set of conductivity groups of values for the set of elements. The method identifies a temperature distribution for the IC design layout based on the set of conductivity groups of values. In some embodiments, each of these elements corresponds to a particular portion of a particular layer of the IC design layout. Each element includes several nodes. Each conductivity group of values is defined by entry values. Each entry value describes how heat flow at a particular node of the element is affected by a temperature change at another particular node of the element.
摘要翻译：本发明的一些实施例提供了一种用于执行包括许多电路模块的集成电路（“IC”）设计布局的热分析的方法。该方法将IC设计布局分为一组元素，其中至少一个元素包含多个线。该方法计算一组元素的一组电导率值。该方法基于一组导电率值来识别IC设计布局的温度分布。在一些实施例中，这些元件中的每一个对应于IC设计布局的特定层的特定部分。每个元素包括几个节点。每个电导率值的值由入口值定义。每个入口值描述了元件的特定节点处的热流如何受到该元件的另一特定节点处的温度变化的影响。

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