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1. 发明授权

US09311440B2 System and method of electromigration avoidance for automatic place-and-route 有权
标题翻译：自动放置路由的电迁移避免系统和方法
公开(公告)号：US09311440B2
公开(公告)日：2016-04-12
申请号：US13468055
申请日：2012-05-10
申请人： Jerry Kao , King-Ho Tam , Meng-Xiang Lee , Li-Chung Hsu , Chi-Yeh Yu , Chung-Min Fu , Chung-Hsing Wang
发明人： Jerry Kao , King-Ho Tam , Meng-Xiang Lee , Li-Chung Hsu , Chi-Yeh Yu , Chung-Min Fu , Chung-Hsing Wang
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F17/5077 , G06F2217/76
摘要： A method includes identifying at least one local power segment of a circuit, estimating at least one performance parameter of the at least one power segment based on a computer-based simulation of the circuit, and changing a design of the circuit based on at least one electromigration avoidance strategy if the at least one parameter is greater than or equal to a threshold value. A data file representing the circuit is stored if the at least one parameter is less than the threshold value.
摘要翻译：一种方法包括识别电路的至少一个局部电力部分，基于电路的基于计算机的仿真来估计所述至少一个电力部分的至少一个性能参数，以及基于至少一个电路来改变所述电路的设计如果至少一个参数大于或等于阈值，则电迁移避免策略。如果至少一个参数小于阈值，则存储表示电路的数据文件。

2. 发明授权

US08826195B2 Layout modification method and system 有权
标题翻译：布局修改方法和系统
公开(公告)号：US08826195B2
公开(公告)日：2014-09-02
申请号：US13530164
申请日：2012-06-22
申请人： Meng-Xiang Lee , Li-Chung Hsu , Shih-Hsien Yang , Ho Che Yu , King-Ho Tam , Chung-Hsing Wang
发明人： Meng-Xiang Lee , Li-Chung Hsu , Shih-Hsien Yang , Ho Che Yu , King-Ho Tam , Chung-Hsing Wang
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5031 , G06F2217/02 , G06F2217/78 , G06F2217/84
摘要： A method comprises providing a non-transitory, machine-readable storage medium storing a partial netlist of at least a portion of a previously taped-out integrated circuit (IC) layout, representing a set of photomasks for fabricating an IC having the IC layout such that the IC meets a first specification value. A computer identifies a proper subset of a plurality of first devices in the IC layout, such that replacement of the proper subset of the first devices by second devices in a revised IC layout satisfies a second specification value different from the first specification value. At least one layout mask is generated and stored in at least one non-transitory machine readable storage medium, accessible by a tool for forming at least one additional photomask, such that the set of photomasks and the at least one additional photomask are usable to fabricate an IC according to the revised IC layout.
摘要翻译：一种方法包括提供一种非暂时的机器可读存储介质，其存储至少部分先前采集的集成电路（IC）布局的部分网表，其表示用于制造具有IC布局的IC的一组光掩模，该IC满足第一规格值。计算机识别IC布局中的多个第一设备的正确子集，使得经修订的IC布局中的第二设备对第一设备的正确子集的替换满足与第一规范值不同的第二规范值。至少一个布局掩模被生成并存储在至少一个非暂时机器可读存储介质中，可由用于形成至少一个附加光掩模的工具访问，使得该组光掩模和至少一个附加光掩模可用于制造一个IC根据修订的IC布局。

3. 发明授权

US08694945B2 Automatic place and route method for electromigration tolerant power distribution 有权
标题翻译：用于电迁移容量配电的自动放置和布线方法
公开(公告)号：US08694945B2
公开(公告)日：2014-04-08
申请号：US13331329
申请日：2011-12-20
申请人： Chung-Hsing Wang , King-Ho Tam , Huang-Yu Chen
发明人： Chung-Hsing Wang , King-Ho Tam , Huang-Yu Chen
IPC分类号： G06F17/50 , H01L23/498
CPC分类号： H01L23/5286 , G06F17/5072 , G06F17/5077 , G06F2217/78 , H01L2027/11881 , H01L2924/0002 , H01L2924/00
摘要： The present disclosure relates to an electromigration tolerant power distribution network generated by an automatic place and route (APR) methodology. In some embodiments, an automatic place and route tool constructs a local power network having multi-level power rails. The multi-level power rails have interleaved segments of vertically adjacent metal layers, wherein each interleaved segment is shorter than a predetermined characteristic length corresponding to a Blech length. By limiting the length of the interleaved metallization segments, electromigration within the multi-level power rails is alleviated, allowing for the maximum current density requirement (Jmax) for mean time to failures (MTTF) to be increased.
摘要翻译：本公开涉及通过自动位置和路由（APR）方法产生的电迁移容限配电网络。在一些实施例中，自动放置和路由工具构建具有多级电源轨的本地电力网络。多级电源轨具有交错的垂直相邻金属层的段，其中每个交错段短于对应于Blech长度的预定特征长度。通过限制交错金属化段的长度，多级电力轨道内的电迁移得到缓解，允许增加平均故障时间（MTTF）的最大电流密度要求（Jmax）。

4. 发明申请

US20130154128A1 Automatic Place and Route Method for Electromigration Tolerant Power Distribution 有权
标题翻译：自动放置和路由方法的电迁移容错配电
公开(公告)号：US20130154128A1
公开(公告)日：2013-06-20
申请号：US13331329
申请日：2011-12-20
申请人： Chung-Hsing Wang , King-Ho Tam , Huang-Yu Chen
发明人： Chung-Hsing Wang , King-Ho Tam , Huang-Yu Chen
IPC分类号： H01L23/498 , G06F17/50
CPC分类号： H01L23/5286 , G06F17/5072 , G06F17/5077 , G06F2217/78 , H01L2027/11881 , H01L2924/0002 , H01L2924/00
摘要： The present disclosure relates to an electromigration tolerant power distribution network generated by an automatic place and route (APR) methodology. In some embodiments, an automatic place and route tool constructs a local power network having multi-level power rails. The multi-level power rails have interleaved segments of vertically adjacent metal layers, wherein each interleaved segment is shorter than a predetermined characteristic length corresponding to a Blech length. By limiting the length of the interleaved metallization segments, electromigration within the multi-level power rails is alleviated, allowing for the maximum current density requirement (Jmax) for mean time to failures (MTTF) to be increased.
摘要翻译：本公开涉及通过自动位置和路由（APR）方法产生的电迁移容限配电网络。在一些实施例中，自动放置和路由工具构建具有多级电源轨的本地电力网络。多级电源轨具有交错的垂直相邻金属层的段，其中每个交错段短于对应于Blech长度的预定特征长度。通过限制交错金属化段的长度，多级电力轨道内的电迁移得到缓解，允许增加平均故障时间（MTTF）的最大电流密度要求（Jmax）。

5. 发明授权

US08499274B2 Computer implemented system and method for leakage calculation 有权
标题翻译：计算机实现系统和泄漏计算方法
公开(公告)号：US08499274B2
公开(公告)日：2013-07-30
申请号：US13403289
申请日：2012-02-23
申请人： Chien-Ju Chao , Jerry Chang-Jui Kao , King-Ho Tam , Chung-Hsing Wang , Huan Chi Tseng
发明人： Chien-Ju Chao , Jerry Chang-Jui Kao , King-Ho Tam , Chung-Hsing Wang , Huan Chi Tseng
IPC分类号： G06F17/50 , G06F9/455 , G06G7/48
CPC分类号： G06F17/5022
摘要： A tool includes one or more machine readable storage mediums encoded with data. The data include a list of standard cells included in an integrated circuit (IC) design The data include a nominal leakage value approximating a respective median leakage value for each of the plurality of standard cells at a predetermined temperature and voltage. The data include at least one table including adjustment factors for calculating leakage based on voltage, temperature and process variations. The table includes a respective statistical scaling factor, for computing a mean leakage corresponding to a given median leakage. A processor is programmed to calculate and output a total IC leakage for the IC design at an input voltage and input temperature, based on the list, the nominal leakage values, the input voltage, the input temperature and at least one of the adjustment factors.
摘要翻译：工具包括用数据编码的一个或多个机器可读存储介质。数据包括集成电路（IC）设计中包括的标准单元的列表。数据包括在预定温度和电压下接近多个标准单元中的每一个的相应中值泄漏值的标称泄漏值。数据包括至少一个表，其中包括基于电压，温度和过程变化来计算泄漏的调整因子。该表包括相应的统计缩放因子，用于计算对应于给定中位泄漏的平均泄漏。处理器被编程为基于列表，标称泄漏值，输入电压，输入温度和至少一个调整因子来计算并输出IC设计中的IC设计的总IC泄漏，输入电压和输入温度。

6. 发明申请

US20130139120A1 COMPUTER IMPLEMENTED SYSTEM AND METHOD FOR LEAKAGE CALCULATION 有权
标题翻译：计算机实现系统和泄漏计算方法
公开(公告)号：US20130139120A1
公开(公告)日：2013-05-30
申请号：US13403289
申请日：2012-02-23
申请人： Chien-Ju Chao , Jerry Chang-Jui Kao , King-Ho Tam , Chung-Hsing Wang , Huan Chi Tseng
发明人： Chien-Ju Chao , Jerry Chang-Jui Kao , King-Ho Tam , Chung-Hsing Wang , Huan Chi Tseng
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： A tool includes one or more machine readable storage mediums encoded with data. The data include a list of standard cells included in an integrated circuit (IC) design The data include a nominal leakage value approximating a respective median leakage value for each of the plurality of standard cells at a predetermined temperature and voltage. The data include at least one table including adjustment factors for calculating leakage based on voltage, temperature and process variations. The table includes a respective statistical scaling factor, for computing a mean leakage corresponding to a given median leakage. A processor is programmed to calculate and output a total IC leakage for the IC design at an input voltage and input temperature, based on the list, the nominal leakage values, the input voltage, the input temperature and at least one of the adjustment factors.
摘要翻译：工具包括用数据编码的一个或多个机器可读存储介质。数据包括集成电路（IC）设计中包括的标准单元的列表。数据包括在预定温度和电压下接近多个标准单元中的每一个的相应中值泄漏值的标称泄漏值。数据包括至少一个表，其中包括基于电压，温度和过程变化来计算泄漏的调整因子。该表包括相应的统计缩放因子，用于计算对应于给定中位泄漏的平均泄漏。处理器被编程为基于列表，标称泄漏值，输入电压，输入温度和至少一个调整因子来计算并输出IC设计中的IC设计的总IC泄漏，输入电压和输入温度。

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