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1. 发明授权

US08601420B1 Equivalent waveform model for static timing analysis of integrated circuit designs 有权
标题翻译：集成电路设计静态时序分析的等效波形模型
公开(公告)号：US08601420B1
公开(公告)日：2013-12-03
申请号：US12960387
申请日：2010-12-03
申请人： Igor Keller , Joel R. Phillips , Jijun Chen
发明人： Igor Keller , Joel R. Phillips , Jijun Chen
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/50 , G06F17/5036 , G06F2217/84
摘要： In one embodiment, a method of constructing an equivalent waveform model for static timing analysis of integrated circuit designs is disclosed. The method includes fitting time point coefficients (qk) and known time delay values from a delay and slew model of a receiving gate from a timing library; determining waveform values (Ikj) for input waveforms from the timing library; determining timing values (dj) from a timing table in the timing library in response to the input waveforms of the timing library; and determining coefficients (qk) by minimizing a residual of a delay equation.
摘要翻译：在一个实施例中，公开了一种构建用于集成电路设计的静态时序分析的等效波形模型的方法。该方法包括从定时库中接收来自延迟和转换模型的时间点系数（qk）和已知的时间延迟值; 从定时库确定输入波形的波形值（Ikj）; 响应于定时库的输入波形从定时库中的定时表确定定时值（dj）; 以及通过使延迟方程的残差最小化来确定系数（qk）。

2. 发明授权

US08375343B1 Methods and apparatus for waveform based variational static timing analysis 有权
标题翻译：基于波形变分静态时序分析的方法和装置
公开(公告)号：US08375343B1
公开(公告)日：2013-02-12
申请号：US12331172
申请日：2008-12-09
申请人： Saurabh K. Tiwary , Joel R. Phillips , Igor Keller
发明人： Saurabh K. Tiwary , Joel R. Phillips , Igor Keller
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A system and method are disclosed for waveform based variational static timing analysis. A circuit is divided into its linear circuit parts and non-linear circuit parts and modeled together, by a combination of linear modeling techniques, into linear equations that may be represented by matrices. The linear equations in matrix form may be readily solved by a computer such that an input waveform to an input pin of the circuit can be sequentially “pushed” through the various interconnects and logic networks of the circuit to an output pin. Output voltage waveforms are obtained at each stage of the waveform pushing and may be used to perform static timing analysis.
摘要翻译：公开了一种基于波形变分静态时序分析的系统和方法。电路分为线性电路部分和非线性电路部分，并通过线性建模技术的组合建模在一起，形成可以由矩阵表示的线性方程组。矩阵形式的线性方程式可以由计算机容易地解决，使得可以将电路的输入引脚的输入波形顺序推送到电路的各种互连和逻辑网络到输出引脚。在波形推送的每个阶段获得输出电压波形，可用于执行静态时序分析。

3. 发明授权

US07761826B1 Method and system for crosstalk analysis 失效
标题翻译：串扰分析方法和系统
公开(公告)号：US07761826B1
公开(公告)日：2010-07-20
申请号：US11782619
申请日：2007-07-24
申请人： Venkat Thanvantri , Shiva Raja , Igor Keller , Lizheng Zhang
发明人： Venkat Thanvantri , Shiva Raja , Igor Keller , Lizheng Zhang
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： Method and system for crosstalk analysis relating to a statistical crosstalk path delay model that fits into existing static timing framework with little overhead in performance and capacity. More realistic models or assumptions are utilized rather than the more aggressive and less likely deterministic model.
摘要翻译：与统计串扰路径延迟模型相关的串扰分析方法和系统，适用于现有的静态时序框架，性能和容量的开销很小。使用更逼真的模型或假设，而不是更积极和不太可能的确定性模型。

4. 发明授权

US07562323B1 System, method and computer program product for handling small aggressors in signal integrity analysis 有权
标题翻译：用于处理信号完整性分析中的小侵略者的系统，方法和计算机程序产品
公开(公告)号：US07562323B1
公开(公告)日：2009-07-14
申请号：US11417862
申请日：2006-05-04
申请人： Xiaoliang Bai , Igor Keller
发明人： Xiaoliang Bai , Igor Keller
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/5036
摘要： A method, system and computer program product for determining aggressor-induced crosstalk in a victim net of a stage of an integrated circuit design is provided. The methodology can include combining a plurality of aggressor nets to construct a virtual aggressor net, determining a current waveform induced on the victim net by the plurality of small aggressor nets, and modeling a current waveform induced by the virtual aggressor on the victim net based on the contribution of the current waveforms determined for the plurality of small aggressor nets. In a further embodiment, the methodology can also comprise evaluating an effect of an aggressor net on a victim net; and including that aggressor net in the virtual aggressor net if its effect is below a predetermined threshold. The effect evaluated by the methodology can, for example, be the height of a glitch induced on the victim net by a transition in the aggressor net. Additionally, the aggressor net can be included in the virtual aggressor net if the height of the glitch it induces on the victim net is less than a predetermined factor of the supply voltage. Switching probability can be used to compute a 3-sigma capacitance value, and this value can be used to limit the number of small aggressors included in the virtual aggressor net. The combined currents of the aggressor in the virtual aggressor net can be modeled using a piece-wise linear analysis.
摘要翻译：提供了一种用于确定集成电路设计阶段的受害者网络中的侵扰者诱导的串扰的方法，系统和计算机程序产品。该方法可以包括组合多个攻击者网以构建虚拟攻击者网络，通过多个小攻击者网络确定在受害者网络上引起的当前波形，以及基于受害者网络上的虚拟攻击者引起的当前波形建模，基于确定多个小侵略网络的电流波形的贡献。在进一步的实施例中，该方法还可以包括评估侵略者网对受害网的影响; 并且如果其影响低于预定阈值，则将该侵入者网络包括在虚拟攻击者网络中。通过该方法评估的效果可以是通过侵略者网络过渡在受害者网络上引起的故障的高度。此外，如果在受害网上引起的故障高度小于电源电压的预定因子，则侵入者网络可以被包括在虚拟攻击者网络中。可以使用切换概率来计算3-sigma电容值，该值可用于限制虚拟攻击者网络中包含的小攻击者的数量。可以使用分段线性分析来建模虚拟攻击者网络中的攻击者的组合电流。

5. 发明授权

US08245165B1 Methods and apparatus for waveform based variational static timing analysis 有权
标题翻译：基于波形变分静态时序分析的方法和装置
公开(公告)号：US08245165B1
公开(公告)日：2012-08-14
申请号：US12331072
申请日：2008-12-09
申请人： Saurabh K. Tiwary , Joel R. Phillips , Igor Keller
发明人： Saurabh K. Tiwary , Joel R. Phillips , Igor Keller
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A system and method are disclosed for waveform based variational static timing analysis. A circuit is divided into its linear circuit parts and non-linear circuit parts and modeled together, by a combination of linear modeling techniques, into linear equations that may be represented by matrices. The linear equations in matrix form may be readily solved by a computer such that an input waveform to an input pin of the circuit can be sequentially “pushed” through the various interconnects and logic networks of the circuit to an output pin. Output voltage waveforms are obtained at each stage of the waveform pushing and may be used to perform static timing analysis.
摘要翻译：公开了一种基于波形变分静态时序分析的系统和方法。电路分为线性电路部分和非线性电路部分，并通过线性建模技术的组合建模在一起，形成可以由矩阵表示的线性方程组。矩阵形式的线性方程可以由计算机容易地解决，使得到电路的输入引脚的输入波形可以顺序地“推动”到电路的各种互连和逻辑网络到输出引脚。在波形推送的每个阶段获得输出电压波形，可用于执行静态时序分析。

6. 发明授权

US08104006B2 Method and apparatus for thermal analysis 有权
标题翻译：热分析方法和装置
公开(公告)号：US08104006B2
公开(公告)日：2012-01-24
申请号：US12024002
申请日：2008-01-31
申请人： Vinod Kariat , Igor Keller , Eddy Pramono
发明人： Vinod Kariat , Igor Keller , Eddy Pramono
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F2217/78
摘要： Some embodiments of the invention provide a method for performing thermal analysis of an integrated circuit (“IC”) layout that includes numerous circuit modules. In some embodiments, the method initially defines several power dissipation equations that express the temperature dependence of the power dissipation for several circuit modules. In some embodiments, the power dissipation equations express a non-linear relationship between power dissipation and temperature. The method defines a heat flow equation based on the specified power dissipation equations. The method then solves the heat flow equation to identify a temperature distribution for the design layout.
摘要翻译：本发明的一些实施例提供了一种用于执行包括许多电路模块的集成电路（“IC”）布局的热分析的方法。在一些实施例中，该方法最初定义了几个功率耗散方程，其表示几个电路模块的功率耗散的温度依赖性。在一些实施例中，功耗方程表示功率耗散和温度之间的非线性关系。该方法基于指定的功率耗散方程定义热流方程。该方法然后解决了热流方程，以确定设计布局的温度分布。

7. 发明授权

US08533644B1 Multi-CCC current source models and static timing analysis methods for integrated circuit designs 有权
标题翻译：多CCC电流源模型和集成电路设计的静态时序分析方法
公开(公告)号：US08533644B1
公开(公告)日：2013-09-10
申请号：US12965886
申请日：2010-12-12
申请人： Vinod Kariat , Igor Keller , Joel R. Phillips , King Ho Tam
发明人： Vinod Kariat , Igor Keller , Joel R. Phillips , King Ho Tam
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5036 , G06F2217/84
摘要： In one embodiment of the invention, a multi-CCC current source model is disclosed to perform statistical timing analysis of an integrated circuit design. The multi-CCC current source model includes a voltage waveform transfer function, a voltage dependent current source, and an output capacitor. The voltage waveform transfer function receives an input voltage waveform and transforms it into an intermediate voltage waveform. The voltage dependent current source generates an output current in response to the intermediate voltage waveform. The output capacitor is coupled in parallel to the voltage dependent current source to generate an output voltage waveform for computation of a timing delay.
摘要翻译：在本发明的一个实施例中，公开了一种多CCC电流源模型来执行集成电路设计的统计时序分析。多CCC电流源模型包括电压波形传递函数，电压相关电流源和输出电容器。电压波形传递函数接收输入电压波形并将其转换为中间电压波形。电压相关电流源响应于中间电压波形产生输出电流。输出电容器并联到与电压相关的电流源，以产生用于计算定时延迟的输出电压波形。

8. 发明授权

US08516420B1 Sensitivity and static timing analysis for integrated circuit designs using a multi-CCC current source model 有权
标题翻译：使用多CCC电流源模型的集成电路设计的灵敏度和静态时序分析
公开(公告)号：US08516420B1
公开(公告)日：2013-08-20
申请号：US11849254
申请日：2007-08-31
申请人： Vinod Kariat , Igor Keller , Joel R. Phillips , King Ho Tam
发明人： Vinod Kariat , Igor Keller , Joel R. Phillips , King Ho Tam
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5036 , G06F2217/84
摘要： In one embodiment of the invention, a multi-CCC current source model is disclosed to perform statistical timing analysis of an integrated circuit design. The multi-CCC current source model includes a voltage waveform transfer function, a voltage dependent current source, and an output capacitor. The voltage waveform transfer function receives an input voltage waveform and transforms it into an intermediate voltage waveform. The voltage dependent current source generates an output current in response to the intermediate voltage waveform. The output capacitor is coupled in parallel to the voltage dependent current source to generate an output voltage waveform for computation of a timing delay.
摘要翻译：在本发明的一个实施例中，公开了一种多CCC电流源模型来执行集成电路设计的统计时序分析。多CCC电流源模型包括电压波形传递函数，电压相关电流源和输出电容器。电压波形传递函数接收输入电压波形并将其转换为中间电压波形。电压相关电流源响应于中间电压波形产生输出电流。输出电容器并联到与电压相关的电流源，以产生用于计算定时延迟的输出电压波形。

9. 发明授权

US08341572B1 Methods and apparatus for waveform based variational static timing analysis 有权
标题翻译：基于波形变分静态时序分析的方法和装置
公开(公告)号：US08341572B1
公开(公告)日：2012-12-25
申请号：US12331130
申请日：2008-12-09
申请人： Saurabh K. Tiwary , Joel R. Phillips , Igor Keller
发明人： Saurabh K. Tiwary , Joel R. Phillips , Igor Keller
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/5031
摘要： A system and method are disclosed for waveform based variational static timing analysis. A circuit is divided into its linear circuit parts and non-linear circuit parts and modeled together, by a combination of linear modeling techniques, into linear equations that may be represented by matrices. The linear equations in matrix form may be readily solved by a computer such that an input waveform to an input pin of the circuit can be sequentially “pushed” through the various interconnects and logic networks of the circuit to an output pin. Output voltage waveforms are obtained at each stage of the waveform pushing and may be used to perform static timing analysis.
摘要翻译：公开了一种基于波形变分静态时序分析的系统和方法。电路分为线性电路部分和非线性电路部分，并通过线性建模技术的组合建模在一起，形成可以由矩阵表示的线性方程组。矩阵形式的线性方程式可以由计算机容易地解决，使得可以将电路的输入引脚的输入波形顺序推送到电路的各种互连和逻辑网络到输出引脚。在波形推送的每个阶段获得输出电压波形，可用于执行静态时序分析。

10. 发明授权

US08302046B1 Compact modeling of circuit stages for static timing analysis of integrated circuit designs 有权
标题翻译：用于集成电路设计的静态时序分析的电路级的紧凑建模
公开(公告)号：US08302046B1
公开(公告)日：2012-10-30
申请号：US12269037
申请日：2008-11-11
申请人： Igor Keller , King Ho Tam
发明人： Igor Keller , King Ho Tam
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： Systems, apparatus, and methods of timing analysis with a multi-operating region gate model are disclosed, including modeling a logic gate with a constant direct current (DC) voltage source during a steady state region of operation; in response to a transition from the steady state region of operation, modeling the logic gate with a time-varying voltage dependent current source during a varying current region of operation; and, in response to a transition from the variable current region of operation, modeling the logic gate with a time-invariant voltage dependent current source during an asymptotic region of operation. Instantaneous output current provided by the time varying voltage dependent current source in the VCR region is responsive to time and the instantaneous output voltage of the logic gate. Instantaneous output current provided by the time-invariant voltage dependent current source in the AR region is responsive to the instantaneous output voltage of the logic gate.
摘要翻译：公开了具有多操作区域门模型的定时分析的系统，装置和方法，包括在稳定状态区域中用恒定直流（DC）电压源对逻辑门进行建模; 响应于从稳态操作区域的转变，在变化的当前操作区域期间用随时间变化的电压依赖电流源对逻辑门进行建模; 并且响应于来自可变电流操作区域的转变，在渐近的操作区域期间用不变的电压依赖电流源对逻辑门进行建模。由VCR区域中随时间变化的电压源提供的瞬时输出电流响应逻辑门的时间和瞬时输出电压。由AR区域中的不变电压依赖电流源提供的瞬时输出电流响应逻辑门的瞬时输出电压。

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