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1. 发明申请

US20130304449A1 SYSTEM AND METHOD OF ELECTROMIGRATION AVOIDANCE FOR AUTOMATIC PLACE-AND- ROUTE 有权
标题翻译：用于自动布置和路由的电气避雷系统和方法
公开(公告)号：US20130304449A1
公开(公告)日：2013-11-14
申请号：US13468055
申请日：2012-05-10
申请人： Jerry KAO , King-Ho TAM , Meng-Xiang LEE , Li-Chung HSU , Chi-Yeh YU , Chung-Min FU , Chung-Hsing WANG
发明人： Jerry KAO , King-Ho TAM , Meng-Xiang LEE , Li-Chung HSU , Chi-Yeh YU , Chung-Min FU , Chung-Hsing WANG
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F17/5077 , G06F2217/76
摘要： A method includes identifying at least one local power segment of a circuit, estimating at least one performance parameter of the at least one power segment based on a computer-based simulation of the circuit, and changing a design of the circuit based on at least one electromigration avoidance strategy if the at least one parameter is greater than or equal to a threshold value. A data file representing the circuit is stored if the at least one parameter is less than the threshold value.
摘要翻译：一种方法包括识别电路的至少一个局部电力部分，基于电路的基于计算机的仿真来估计所述至少一个电力部分的至少一个性能参数，以及基于至少一个电路来改变所述电路的设计如果至少一个参数大于或等于阈值，则电迁移避免策略。如果至少一个参数小于阈值，则存储表示电路的数据文件。

2. 发明申请

US20130326438A1 LAYOUT MODIFICATION METHOD AND SYSTEM 有权
标题翻译：布局修改方法和系统
公开(公告)号：US20130326438A1
公开(公告)日：2013-12-05
申请号：US13530164
申请日：2012-06-22
申请人： Meng-Xiang LEE , Li-Chung HSU , Shih-Hsien YANG , Ho Che YU , King-Ho TAM , Chung-Hsing WANG
发明人： Meng-Xiang LEE , Li-Chung HSU , Shih-Hsien YANG , Ho Che YU , King-Ho TAM , Chung-Hsing WANG
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5031 , G06F2217/02 , G06F2217/78 , G06F2217/84
摘要： A method comprises providing a non-transitory, machine-readable storage medium storing a partial netlist of at least a portion of a previously taped-out integrated circuit (IC) layout, representing a set of photomasks for fabricating an IC having the IC layout such that the IC meets a first specification value. A computer identifies a proper subset of a plurality of first devices in the IC layout, such that replacement of the proper subset of the first devices by second devices in a revised IC layout satisfies a second specification value different from the first specification value. At least one layout mask is generated and stored in at least one non-transitory machine readable storage medium, accessible by a tool for forming at least one additional photomask, such that the set of photomasks and the at least one additional photomask are usable to fabricate an IC according to the revised IC layout.
摘要翻译：一种方法包括提供一种非暂时的机器可读存储介质，其存储至少部分先前采集的集成电路（IC）布局的部分网表，其表示用于制造具有IC布局的IC的一组光掩模，该IC满足第一规格值。计算机识别IC布局中的多个第一设备的正确子集，使得经修订的IC布局中的第二设备对第一设备的正确子集的替换满足与第一规范值不同的第二规范值。至少一个布局掩模被生成并存储在至少一个非暂时机器可读存储介质中，可由用于形成至少一个附加光掩模的工具访问，使得该组光掩模和至少一个附加光掩模可用于制造一个IC根据修订的IC布局。

3. 发明申请

US20130091476A1 METHOD AND SYSTEM FOR REPLACING A PATTERN IN A LAYOUT 有权
标题翻译：用于在布局中替换图案的方法和系统
公开(公告)号：US20130091476A1
公开(公告)日：2013-04-11
申请号：US13269757
申请日：2011-10-10
申请人： Huang-Yu CHEN , Yuan-Te HOU , Chung-Min FU , Chung-Hsing WANG , Wen-Hao CHEN , Yi-Kan CHENG
发明人： Huang-Yu CHEN , Yuan-Te HOU , Chung-Min FU , Chung-Hsing WANG , Wen-Hao CHEN , Yi-Kan CHENG
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： A received layout identifies a plurality of circuit components to be included in an integrated circuit (IC) layer for double patterning the layer using two photomasks, the layout including a plurality of first patterns to be included in the first photomask and at least one second pattern to be included in the second photomask. A selected one of the first patterns has first and second endpoints, to be replaced by a replacement pattern connecting the first endpoint to a third endpoint. At least one respective keep-out region is provided adjacent to each respective remaining first pattern except for the selected first pattern. Data are generated representing the replacement pattern, such that no part of the replacement pattern is formed in any of the keep-out regions. Data representing the remaining first patterns and the replacement pattern are output.
摘要翻译：接收到的布局标识要包括在集成电路（IC）层中的多个电路组件，用于使用两个光掩模对层进行双重图案化，所述布局包括要包括在第一光掩模中的多个第一图案和至少一个第二图案被包括在第二个光掩模中。所选择的第一模式中的一个具有第一和第二端点，被替换为将第一端点连接到第三端点的替换模式。除了所选择的第一图案之外，至少一个相应的保留区域被设置为与每个相应的剩余第一图案相邻。生成表示替换图案的数据，使得在任何保留区域中不形成替换图案的一部分。输出表示剩余的第一图案和替换图案的数据。

4. 发明申请

US20130174106A1 STITCH AND TRIM METHODS FOR DOUBLE PATTERNING COMPLIANT STANDARD CELL DESIGN 有权
公开(公告)号：US20130174106A1
公开(公告)日：2013-07-04
申请号：US13415997
申请日：2012-03-09
申请人： Chin-Hsiung HSU , Huang-Yu CHEN , Chung-Hsing WANG
发明人： Chin-Hsiung HSU , Huang-Yu CHEN , Chung-Hsing WANG
IPC分类号： G06F17/50
CPC分类号： G06F17/50 , G06F17/5072 , G06F2217/78
摘要： A method for creating double patterning compliant integrated circuit layouts is disclosed. The method allows patterns to be assigned to different masks and stitched together during lithography. The method also allows portions of the pattern to be removed after the process.

5. 发明申请

US20140019930A1 SEMICONDUCTOR DEVICE DESIGN METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT 有权
标题翻译：半导体器件设计方法，系统和计算机程序产品
公开(公告)号：US20140019930A1
公开(公告)日：2014-01-16
申请号：US13547251
申请日：2012-07-12
申请人： Ping-Hung YUH , Cheng-I HUANG , Chung-Hsing WANG
发明人： Ping-Hung YUH , Cheng-I HUANG , Chung-Hsing WANG
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/5081
摘要： In a semiconductor device design method performed by at least one processor, at least one first parasitic parameter between electrical components inside a region of a layout of a semiconductor device and at least one second parasitic parameter between electrical components outside the region of the layout are extracted by different tools. The extracted parasitic parameters are incorporated into the layout.
摘要翻译：在由至少一个处理器执行的半导体器件设计方法中，提取在半导体器件的布局的区域内的电气元件之间的至少一个第一寄生参数和在布局区域之外的电气元件之间的至少一个第二寄生参数通过不同的工具。提取的寄生参数被并入到布局中。

6. 发明申请

US20110083115A1 ROBUST METHOD FOR INTEGRATION OF BUMP CELLS IN SEMICONDUCTOR DEVICE DESIGN 有权
标题翻译：用于在半导体器件设计中整合保护电池的稳健方法
公开(公告)号：US20110083115A1
公开(公告)日：2011-04-07
申请号：US12575147
申请日：2009-10-07
申请人： Hung-Yi LIU , Chung-Hsing WANG , Agrawal Aditya BINODKUMAR
发明人： Hung-Yi LIU , Chung-Hsing WANG , Agrawal Aditya BINODKUMAR
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/12 , Y02P90/265
摘要： A system and method for computer-aided design of semiconductor integrated circuit devices provides for having dummy vias beneath UBM of bump cells to prevent delamination at the bump cell sites during bonding. The dummy vias are inserted into the design and bump cell placement occurs during the floorplanning stage and prior to placement and routing of the active integrated circuit components. In this manner, a sufficiently high via density is achieved and design information on the bump cells including the dummy vias is provided to a computer-aided design, CAD, system along with program instructions for carrying out the indicated sequence of design operations.
摘要翻译：用于半导体集成电路器件的计算机辅助设计的系统和方法提供了在凸块电池的UBM下面具有虚拟通孔，以防止在接合期间在凸块电池位置处的分层。虚设通孔插入到设计中，并且在铺设阶段期间以及在有源集成电路部件的放置和布线之前发生凸起电池放置。以这种方式，实现足够高的通孔密度，并且将包括虚拟通路的凸起单元的设计信息与用于执行所指示的设计操作序列的程序指令一起提供给计算机辅助设计CAD系统。

7. 发明申请

US20100242008A1 METHOD FOR DUMMY METAL AND DUMMY VIA INSERTION 有权
标题翻译：用于金属和DUMMY通过插入的方法
公开(公告)号：US20100242008A1
公开(公告)日：2010-09-23
申请号：US12728728
申请日：2010-03-22
申请人： Hung-Yi LIU , Chung-Hsing WANG , Chih-Chieh CHEN , Jian-Yi LI
发明人： Hung-Yi LIU , Chung-Hsing WANG , Chih-Chieh CHEN , Jian-Yi LI
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F17/5045 , G06F17/5068 , G06F17/5072 , G06F17/5081
摘要： A method for dummy metal and dummy via insertion is provided. In one embodiment, dummy metals are inserted using a place and route tool, where the place and route tool has timing-awareness. Then, dummy vias arrays are inserted inside an overlap area of dummy metals using a design-rule-checking utility. Fine-grained dummy vias arrays are inserted in available space far away from main patterns. The dummy-patterns resulting from the inserted dummy vias are compressed using the design-rule-checking utility to reduce the size of a graphic data system file generated from the integrated circuit design. The dummy vias can be inserted with relaxed via spacing rules. The dummy metals are inserted with a constant line-end spacing between them for better process control and the maximum length of the dummy metal can be limited for smaller coupling effects. The dummy vias can have various sizes and a square or rectangular shape.
摘要翻译：提供了一种用于虚拟金属和虚拟通孔插入的方法。在一个实施例中，使用地点和路线工具插入虚拟金属，其中地点和路线工具具有时间意识。然后，使用设计规则检查实用程序将虚拟过孔阵列插入到虚拟金属的重叠区域内。细粒度的虚拟通孔阵列插入到远离主图案的可用空间中。使用设计规则检查实用程序对插入的虚拟通孔产生的虚拟模式进行压缩，以减小从集成电路设计生成的图形数据系统文件的大小。虚拟通孔可以放松通过间隔规则插入。虚拟金属以它们之间的恒定的线端间隔插入，以获得更好的工艺控制，并且可以限制虚拟金属的最大长度以减小耦合效应。虚拟通孔可以具有各种尺寸和正方形或矩形形状。

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