专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20130058062A1 METHOD FOR MANUFACTURING BASE MATERIAL HAVING GOLD-PLATED METAL FINE PATTERN, BASE MATERIAL HAVING GOLD-PLATED METAL FINE PATTERN, PRINTED WIRING BOARD, INTERPOSER, AND SEMICONDUCTOR DEVICE 审中-公开
标题翻译：用于制造具有金属镀金属图案的基材的方法，具有金属镀金属图案的基底材料，印刷线路板，插入器和半导体器件
公开(公告)号：US20130058062A1
公开(公告)日：2013-03-07
申请号：US13697720
申请日：2011-05-26
申请人： Kenya Tachibana , Teppei Ito , Yasuaki Mitsui
发明人： Kenya Tachibana , Teppei Ito , Yasuaki Mitsui
IPC分类号： H05K3/10 , H05K7/06 , H05K1/09
CPC分类号： H05K3/108 , C23C18/1651 , C23C18/1653 , C23C18/1689 , C23C18/1844 , C23C18/2006 , C23C18/2086 , C23C18/22 , C23C18/30 , C23C18/34 , C23C18/36 , C23C18/44 , C25D5/022 , H01L23/49816 , H01L23/49827 , H01L24/45 , H01L24/48 , H01L24/73 , H01L2224/05571 , H01L2224/05573 , H01L2224/16225 , H01L2224/16227 , H01L2224/32225 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/48228 , H01L2224/48465 , H01L2224/73204 , H01L2224/73265 , H01L2924/00014 , H01L2924/15174 , H01L2924/15311 , H01L2924/181 , H05K3/244 , H05K3/387 , H05K2201/0761 , H01L2924/00012 , H01L2924/00 , H01L2224/05599
摘要： A method for manufacturing a base material having a gold-plated metal fine pattern is disclosed, comprising the steps of preparing a base material having a supporting surface made of a resin; forming a primer resin layer having surface roughness of 0.5 μm or less on the supporting surface, and forming a metal fine pattern thereon by an SAP process to obtain a base material having a metal fine pattern; and applying a gold-plating treatment to at least one part of a surface of the metal fine pattern; wherein the base material having a metal fine pattern is subjected to a palladium removal treatment in an optional stage before carrying out the gold-plating treatment.
摘要翻译：公开了一种具有镀金属精细图案的基材的制造方法，包括制备具有由树脂制成的支撑面的基材的工序; 在支撑面上形成表面粗糙度为0.5μm以下的底漆树脂层，通过SAP工序在其上形成金属微细图案，得到具有金属微细图案的基材; 对所述金属精细图案的表面的至少一部分进行镀金处理; 其中，在进行镀金处理之前，在任意阶段对具有金属精细图案的基材进行脱钯处理。

2. 发明申请

US20110051387A1 METHOD FOR ELECTROLESS NICKEL-PALLADIUM-GOLD PLATING, PLATED PRODUCT, PRINTED WIRING BOARD, INTERPOSER AND SEMICONDUCTOR APPARATUS 审中-公开
标题翻译：电镀镍 - 镀金镀层，印制产品，印刷线路板，插销器和半导体装置的方法
公开(公告)号：US20110051387A1
公开(公告)日：2011-03-03
申请号：US12852522
申请日：2010-08-09
申请人： Kenya TACHIBANA , Teppei ITO , Yasuaki MITSUI
发明人： Kenya TACHIBANA , Teppei ITO , Yasuaki MITSUI
IPC分类号： H05K1/09 , H05K7/00 , H05H1/00
CPC分类号： C23C18/1607 , C23C18/1844 , C23C18/50 , H01L24/73 , H01L2224/16225 , H01L2224/32225 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H01L2224/73265 , H01L2924/15311 , H01L2924/181 , H05K3/244 , H05K3/26 , H05K2201/0761 , H05K2201/10378 , H05K2203/0716 , H05K2203/072 , H05K2203/0793 , H05K2203/0796 , H05K2203/095 , H01L2924/00012 , H01L2924/00 , H01L2924/00014
摘要： An object of the present invention is to provide an electroless nickel-palladium-gold plating method which is able, when performed on a plating target surface such as terminals of a printed wiring board, terminals of other electronic components, and other resin substrates with a fine metal pattern, to prevent abnormal metal deposition on a resin surface which is an undercoat and to provide a high-quality plated surface. Another object of the present invention is to provide a plated product with a high-quality plated surface, particularly such as an interposer and motherboard, and a semiconductor apparatus using the same. These objects were achieved by the electroless nickel-palladium-gold plating method of the present invention, which is a method for plating target objects such as terminals of a printed wiring board and in which at least one surface treatment selected from a treatment with a solution of pH 10 to 14 and a plasma treatment is performed at an optional step after the step of providing a palladium catalyst and before the step of performing electroless palladium plating.
摘要翻译：本发明的目的在于提供一种无电解镍 - 钯 - 金电镀方法，其能够在电镀目标表面上进行印刷电路板的端子，其他电子部件的端子和其它树脂基板精细的金属图案，以防止在作为底涂层的树脂表面上异常金属沉积并提供高质量的电镀表面。本发明的另一个目的是提供一种具有高质量电镀表面的电镀产品，特别是内插器和母板，以及使用该电镀产品的半导体装置。这些目的是通过本发明的化学镀镍 - 钯 - 金镀覆方法来实现的，该方法是用于对印刷电路板的端子等目标物体进行电镀的方法，其中至少一种选自溶液处理的表面处理的pH为10〜14，并且在提供钯催化剂的步骤之后和进行无电镀钯的步骤之前的任选步骤进行等离子体处理。

3. 发明申请

US20110180208A1 METHOD FOR LAMINATING PREPREG, METHOD FOR PRODUCING PRINTED WIRING BOARD AND PREPREG ROLL 审中-公开
标题翻译：用于层压PREPREG的方法，用于生产印刷线路板和PREPREG辊的方法
公开(公告)号：US20110180208A1
公开(公告)日：2011-07-28
申请号：US13010425
申请日：2011-01-20
申请人： Kenya TACHIBANA , Kuniharu UMENO , Kenichi KANEDA
发明人： Kenya TACHIBANA , Kuniharu UMENO , Kenichi KANEDA
IPC分类号： H05K3/00 , B32B37/02 , B32B37/06 , B32B37/10 , B32B37/14 , C09J7/02
CPC分类号： B32B37/16 , B32B2038/0064 , B32B2038/0076 , B32B2305/076 , B32B2309/02 , B32B2309/12 , B32B2309/68 , B32B2457/08 , H05K3/4673 , H05K2203/1545 , Y10T428/14
摘要： A method for laminating a prepreg contributing to decrease in layer thickness and having high productivity, a method for producing a printed wiring board by the method for laminating the prepreg, and a prepreg roll used for the method for laminating the prepreg are provided. The method involves: 1) preparing a prepreg roll comprising a prepreg comprising at least a core layer, a first resin layer, a second resin layer, being thicker than the first resin layer, and a supporting base film which covers the first resin layer, wherein the prepreg with the supporting base film is rolled up into a roll; 2) unreeling the prepreg with the supporting base film from the prepreg roll, peeling off the peelable film if the second resin layer is covered with the peelable film, and layering the prepreg with the supporting base film on a circuit board so that the second resin layer side of the prepreg with the supporting base film faces a circuit of the circuit board; 3) vacuum laminating the prepreg; and 4) smoothing a surface of the first resin layer contacting the supporting base film by hot press.
摘要翻译：提供了有助于降低层厚度并且具有高生产率的预浸料的层压方法，通过层压预浸料坯的方法制造印刷线路板的方法和用于层压预浸料的方法的预浸料辊。该方法包括：1）制备预浸料辊，该预浸料辊包括至少包含比第一树脂层厚的芯层，第一树脂层，第二树脂层的预浸料和覆盖第一树脂层的支撑基膜，其中将具有支撑基膜的预浸料卷起成卷; 2）如果第二树脂层被可剥离膜覆盖，则用预浸料辊将支撑基膜从预浸料坯上退卷，剥离可剥离膜，并将预浸料与支撑基膜分层在电路板上，使得第二树脂具有支撑基底膜的预浸料的层侧面对电路板的电路; 3）真空层压预浸料; 以及4）通过热压使所述第一树脂层的与所述支撑基膜接触的表面平滑化。

4. 发明授权

US08008767B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US08008767B2
公开(公告)日：2011-08-30
申请号：US12094775
申请日：2007-09-05
申请人： Masahiro Wada , Hiroyuki Tanaka , Hiroshi Hirose , Teppei Itoh , Kenya Tachibana
发明人： Masahiro Wada , Hiroyuki Tanaka , Hiroshi Hirose , Teppei Itoh , Kenya Tachibana
IPC分类号： H01L23/18 , H01L23/498
CPC分类号： H01L21/563 , H01L23/145 , H01L23/498 , H01L23/49894 , H01L2224/131 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/00011 , H01L2924/00014 , H01L2924/01004 , H01L2924/01019 , H01L2924/0102 , H01L2924/01057 , H01L2924/01078 , H01L2924/01079 , H01L2924/10253 , H01L2924/3011 , H05K1/0271 , H05K3/305 , H05K3/4602 , H01L2924/00 , H01L2924/014 , H01L2224/0401
摘要： The invention offers technology for suppressing damage to semiconductor devices due to temperature changes. When flip-chip mounting a silicon chip on a buildup type multilayer substrate having a structure with a thinned core, a core having a small coefficient of thermal expansion is used in the multilayer substrate, and the coefficient of thermal expansion and glass transition point of the underfill are appropriately designed in accordance with the thickness and coefficient of thermal expansion of the core. By doing so, it is possible to relieve stresses inside the semiconductor package caused by deformation of the multilayer substrate due to temperature changes, and thereby to suppress damage to the semiconductor package due to temperature changes.
摘要翻译：本发明提供了用于抑制由于温度变化引起的半导体器件损坏的技术。当将硅芯片倒装安装在具有减薄芯的结构的积层型多层基板上时，在多层基板中使用具有小的热膨胀系数的芯，并且热膨胀系数和玻璃化转变点底部填充物根据芯的厚度和热膨胀系数进行适当设计。通过这样做，可以减轻由于温度变化而导致的多层基板的变形引起的半导体封装内的应力，从而抑制由于温度变化导致的半导体封装的损坏。

5. 发明授权

US07893542B2 Connecting structure for flip-chip semiconductor package, build-up layer material, sealing resin composition, and circuit board 失效
标题翻译：倒装芯片半导体封装，堆积层材料，密封树脂组合物和电路板的连接结构
公开(公告)号：US07893542B2
公开(公告)日：2011-02-22
申请号：US12309110
申请日：2008-03-28
申请人： Kenya Tachibana , Masahiro Wada , Takuya Hatao
发明人： Kenya Tachibana , Masahiro Wada , Takuya Hatao
IPC分类号： H01L23/29
CPC分类号： H05K1/0271 , H01L21/563 , H01L23/293 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L24/16 , H01L24/81 , H01L2224/16 , H01L2224/73203 , H01L2224/81801 , H01L2924/01004 , H01L2924/01012 , H01L2924/01019 , H01L2924/0102 , H01L2924/01078 , H01L2924/01079 , H01L2924/10253 , H05K3/305 , H05K3/4602 , H05K2201/068 , H05K2201/10674 , H05K2201/10977 , H01L2924/00
摘要： The invention provides a connecting structure for a flip-chip semiconductor package in which cracking and delamination are inhibited or reduced to improve reliability, and in which the potential range of designs is expanded for the inner circuitry of circuit boards and the inductance is reduced. The invention is a connecting structure for a flip-chip semiconductor package, including: a circuit board having a core layer and at least one build-up layer; a semiconductor element connected via metal bumps to the circuit board; and a sealing resin composition with which gaps between the semiconductor element and circuit board are filled, wherein a cured product of the sealing resin composition has a glass transition temperature between 60° C. and 150° C. and a coefficient of linear expansion from room temperature to the glass transition temperature being between 15 ppm/° C. and 35 ppm/° C., a cured product of the build-up layer has a the glass transition temperature of at least 170° C. and a coefficient of linear expansion in the in-plane direction up to the glass transition temperature being not more than 40 ppm/° C., and stacked vias are provided in the build-up layer on at least one side of the core layer.
摘要翻译：本发明提供了一种用于倒装芯片半导体封装的连接结构，其中抑制或减少裂纹和分层以提高可靠性，并且其中电路板的内部电路扩展了设计的电位范围并且电感被减小。本发明是用于倒装芯片半导体封装的连接结构，包括：具有芯层和至少一个堆积层的电路板; 通过金属凸块连接到电路板的半导体元件; 以及密封树脂组合物，其中填充有半导体元件和电路板之间的间隙，其中密封树脂组合物的固化产物的玻璃化转变温度为60℃至150℃，并且室内线性膨胀系数温度至玻璃化转变温度在15ppm /℃至35ppm /℃之间，积聚层的固化产物的玻璃化转变温度至少为170℃，线膨胀系数在面内方向直到玻璃化转变温度为40ppm /℃以下，堆积通孔设置在芯层的至少一侧上的堆积层中。

6. 发明申请

US20090267212A1 Semiconductor Device 失效
标题翻译：半导体器件
公开(公告)号：US20090267212A1
公开(公告)日：2009-10-29
申请号：US12094775
申请日：2007-09-05
申请人： Masahiro Wada , Hiroyuki Tanaka , Hiroshi Hirose , Teppei Itoh , Kenya Tachibana
发明人： Masahiro Wada , Hiroyuki Tanaka , Hiroshi Hirose , Teppei Itoh , Kenya Tachibana
IPC分类号： H01L23/18 , H01L23/498
CPC分类号： H01L21/563 , H01L23/145 , H01L23/498 , H01L23/49894 , H01L2224/131 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/00011 , H01L2924/00014 , H01L2924/01004 , H01L2924/01019 , H01L2924/0102 , H01L2924/01057 , H01L2924/01078 , H01L2924/01079 , H01L2924/10253 , H01L2924/3011 , H05K1/0271 , H05K3/305 , H05K3/4602 , H01L2924/00 , H01L2924/014 , H01L2224/0401
摘要： The invention offers technology for suppressing damage to semiconductor devices due to temperature changes. When flip-chip mounting a silicon chip on a buildup type multilayer substrate having a structure with a thinned core, a core having a small coefficient of thermal expansion is used in the multilayer substrate, and the coefficient of thermal expansion and glass transition point of the underfill are appropriately designed in accordance with the thickness and coefficient of thermal expansion of the core. By doing so, it is possible to relieve stresses inside the semiconductor package caused by deformation of the multilayer substrate due to temperature changes, and thereby to suppress damage to the semiconductor package due to temperature changes.
摘要翻译：本发明提供了用于抑制由于温度变化引起的半导体器件损坏的技术。当将硅芯片倒装安装在具有减薄芯的结构的积层型多层基板上时，在多层基板中使用具有小的热膨胀系数的芯，并且热膨胀系数和玻璃化转变点底部填充物根据芯的厚度和热膨胀系数进行适当设计。通过这样做，可以减轻由于温度变化而导致的多层基板的变形引起的半导体封装内的应力，从而抑制由于温度变化导致的半导体封装的损坏。

7. 发明授权

US08592994B2 Semiconductor package, core layer material, buildup layer material, and sealing resin composition 有权
标题翻译：半导体封装，芯层材料，堆积层材料和密封树脂组合物
公开(公告)号：US08592994B2
公开(公告)日：2013-11-26
申请号：US12517551
申请日：2007-12-05
申请人： Kenya Tachibana , Masahiro Wada , Hitoshi Kawaguchi , Kensuke Nakamura
发明人： Kenya Tachibana , Masahiro Wada , Hitoshi Kawaguchi , Kensuke Nakamura
IPC分类号： H01L23/48
CPC分类号： H01L21/563 , C08L63/00 , H01L23/293 , H01L23/3735 , H01L23/3737 , H01L23/49822 , H01L2224/16 , H01L2224/16225 , H01L2224/16227 , H01L2224/32225 , H01L2224/73203 , H01L2224/73204 , H01L2924/00014 , H01L2924/01019 , H01L2924/0102 , H01L2924/01078 , H01L2924/01079 , H01L2924/10253 , H05K1/0271 , H05K3/305 , H05K3/4602 , H05K2201/068 , H05K2201/10674 , H05K2201/10977 , H01L2924/00 , H01L2224/0401
摘要： A flip-chip semiconductor package includes a circuit board having a core layer and at least one buildup layer, a semiconductor device connected to the circuit board through a metal bump, and a cured member that is made of a sealing resin composition and enclosed between the semiconductor device and the circuit board. The coefficient of linear expansion at 25 to 75° C. of the cured member is 15 to 35 ppm/° C., the glass transition temperature of at least one buildup layer is 170° C. or more, and the coefficient of linear expansion of at 25 to 75° C. of the at least one buildup layer in the planar direction is 25 ppm or less. A highly reliable flip-chip semiconductor package, buildup layer material, core layer material, and sealing resin composition can be provided by preventing cracks and inhibiting delamination.
摘要翻译：倒装芯片半导体封装包括具有芯层和至少一个堆积层的电路板，通过金属凸块连接到电路板的半导体器件，以及由密封树脂组合物制成的封装在其间的固化构件半导体器件和电路板。固化部件的25〜75℃的线膨胀系数为15〜35ppm /℃，至少一层积层的玻璃化转变温度为170℃以上，线膨胀系数在平面方向上的至少一个堆积层的25〜75℃为25ppm以下。可以通过防止裂纹和抑制分层而提供高度可靠的倒装芯片半导体封装，堆积层材料，芯层材料和密封树脂组合物。

8. 发明申请

US20100032826A1 SEMICONDUCTOR PACKAGE, CORE LAYER MATERIAL, BUILDUP LAYER MATERIAL, AND SEALING RESIN COMPOSITION 有权
标题翻译：半导体包装，核心层材料，建筑材料和密封树脂组合物
公开(公告)号：US20100032826A1
公开(公告)日：2010-02-11
申请号：US12517551
申请日：2007-12-05
申请人： Kenya Tachibana , Masahiro Wada , Hitoshi Kawaguchi , Kensuke Nakamura
发明人： Kenya Tachibana , Masahiro Wada , Hitoshi Kawaguchi , Kensuke Nakamura
IPC分类号： H01L23/48 , C08G18/77
CPC分类号： H01L21/563 , C08L63/00 , H01L23/293 , H01L23/3735 , H01L23/3737 , H01L23/49822 , H01L2224/16 , H01L2224/16225 , H01L2224/16227 , H01L2224/32225 , H01L2224/73203 , H01L2224/73204 , H01L2924/00014 , H01L2924/01019 , H01L2924/0102 , H01L2924/01078 , H01L2924/01079 , H01L2924/10253 , H05K1/0271 , H05K3/305 , H05K3/4602 , H05K2201/068 , H05K2201/10674 , H05K2201/10977 , H01L2924/00 , H01L2224/0401
摘要： A flip-chip semiconductor package includes a circuit board having a core layer and at least one buildup layer, a semiconductor device connected to the circuit board through a metal bump, and a cured member that is made of a sealing resin composition and enclosed between the semiconductor device and the circuit board. The coefficient of linear expansion at 25 to 75° C. of the cured member is 15 to 35 ppm/° C., the glass transition temperature of at least one buildup layer is 170° C. or more, and the coefficient of linear expansion of at 25 to 75° C. of the at least one buildup layer in the planar direction is 25 ppm or less. A highly reliable flip-chip semiconductor package, buildup layer material, core layer material, and sealing resin composition can be provided by preventing cracks and inhibiting delamination.
摘要翻译：倒装芯片半导体封装包括具有芯层和至少一个堆积层的电路板，通过金属凸块连接到电路板的半导体器件，以及由密封树脂组合物制成的封装在其间的固化构件半导体器件和电路板。固化部件的25〜75℃的线膨胀系数为15〜35ppm /℃，至少一层积层的玻璃化转变温度为170℃以上，线膨胀系数在平面方向上的至少一个堆积层的25〜75℃为25ppm以下。可以通过防止裂纹和抑制分层而提供高度可靠的倒装芯片半导体封装，堆积层材料，芯层材料和密封树脂组合物。

9. 发明申请

US20090273073A1 CONNECTING STRUCTURE FOR FLIP-CHIP SEMICONDUCTOR PACKAGE, BUILD-UP LAYER MATERIAL, SEALING RESIN COMPOSITION, AND CIRCUIT BOARD 失效
标题翻译：贴片半导体封装，建筑材料，密封树脂组合物和电路板的连接结构
公开(公告)号：US20090273073A1
公开(公告)日：2009-11-05
申请号：US12309110
申请日：2008-03-28
申请人： Kenya Tachibana , Masahiro Wada , Takuya Hatao
发明人： Kenya Tachibana , Masahiro Wada , Takuya Hatao
IPC分类号： H01L23/498 , H05K1/16 , C08G65/04 , C08G65/38 , C08G18/00 , C08G73/06 , C08G73/10 , C08G61/08 , C08G73/14
CPC分类号： H05K1/0271 , H01L21/563 , H01L23/293 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L24/16 , H01L24/81 , H01L2224/16 , H01L2224/73203 , H01L2224/81801 , H01L2924/01004 , H01L2924/01012 , H01L2924/01019 , H01L2924/0102 , H01L2924/01078 , H01L2924/01079 , H01L2924/10253 , H05K3/305 , H05K3/4602 , H05K2201/068 , H05K2201/10674 , H05K2201/10977 , H01L2924/00
摘要： The invention provides a connecting structure for a flip-chip semiconductor package in which cracking and delamination are inhibited or reduced to improve reliability, and in which the potential range of designs is expanded for the inner circuitry of circuit boards and the inductance is reduced. The invention is a connecting structure for a flip-chip semiconductor package, including: a circuit board having a core layer and at least one build-up layer; a semiconductor element connected via metal bumps to the circuit board; and a sealing resin composition with which gaps between the semiconductor element and circuit board are filled, wherein a cured product of the sealing resin composition has a glass transition temperature between 60° C. and 150° C. and a coefficient of linear expansion from room temperature to the glass transition temperature being between 15 ppm/° C. and 35 ppm/° C., a cured product of the build-up layer has a the glass transition temperature of at least 170° C. and a coefficient of linear expansion in the in-plane direction up to the glass transition temperature being not more than 40 ppm/° C., and stacked vias are provided in the build-up layer on at least one side of the core layer.
摘要翻译：本发明提供了一种用于倒装芯片半导体封装的连接结构，其中抑制或减少裂纹和分层以提高可靠性，并且其中电路板的内部电路扩展了设计的电位范围并且减小了电感。本发明是用于倒装芯片半导体封装的连接结构，包括：具有芯层和至少一个堆积层的电路板; 通过金属凸块连接到电路板的半导体元件; 以及密封树脂组合物，其中填充有半导体元件和电路板之间的间隙，其中密封树脂组合物的固化产物的玻璃化转变温度为60℃至150℃，并且室内线性膨胀系数温度至玻璃化转变温度在15ppm /℃至35ppm /℃之间，积聚层的固化产物的玻璃化转变温度至少为170℃，线膨胀系数在面内方向直到玻璃化转变温度为40ppm /℃以下，堆积通孔设置在芯层的至少一侧上的堆积层中。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式