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1. 发明申请

US20080094405A1 SCALABLE SHADER ARCHITECTURE 有权
标题翻译：可分级阴影架构
公开(公告)号：US20080094405A1
公开(公告)日：2008-04-24
申请号：US11957358
申请日：2007-12-14
申请人： Rui BASTOS , Karim Abdalla , Christian Rouet , Michael Toksvig , Johnny Rhoades , Roger Allen , John Tynefield , Emmett Kilgariff , Gary Tarolli , Brian Cabral , Craig Wittenbrink , Sean Treichler
发明人： Rui BASTOS , Karim Abdalla , Christian Rouet , Michael Toksvig , Johnny Rhoades , Roger Allen , John Tynefield , Emmett Kilgariff , Gary Tarolli , Brian Cabral , Craig Wittenbrink , Sean Treichler
IPC分类号： G06F15/80
CPC分类号： G06T15/005
摘要： A scalable shader architecture is disclosed. In accord with that architecture, a shader includes multiple shader pipelines, each of which can perform processing operations on rasterized pixel data. Shader pipelines can be functionally removed as required, thus preventing a defective shader pipeline from causing a chip rejection. The shader includes a shader distributor that processes rasterized pixel data and then selectively distributes the processed rasterized pixel data to the various shader pipelines, beneficially in a manner that balances workloads. A shader collector formats the outputs of the various shader pipelines into proper order to form shaded pixel data. A shader instruction processor (scheduler) programs the individual shader pipelines to perform their intended tasks. Each shader pipeline has a shader gatekeeper that interacts with the shader distributor and with the shader instruction processor such that pixel data that passes through the shader pipelines is controlled and processed as required.
摘要翻译：公开了可扩展着色器架构。根据该架构，着色器包括多个着色器管线，每个着色器管线可以对光栅化像素数据执行处理操作。着色器管线可以根据需要进行功能删除，从而防止着色器流水线造成芯片排斥。着色器包括着色器分配器，用于处理光栅化的像素数据，然后有选择地将经处理的光栅化像素数据分配到各种着色器管线，有利于平衡工作负载。着色器收集器将各种着色器管线的输出格式化为正确的顺序，以形成阴影像素数据。着色器指令处理器（调度器）对各个着色器管线进行编程，以执行其预期任务。每个着色器管道具有与着色器分配器和着色器指令处理器交互的着色器网守，使得通过着色器管线的像素数据被根据需要被控制和处理。

2. 发明申请

US20050225554A1 Scalable shader architecture 有权
标题翻译：可扩展着色器架构
公开(公告)号：US20050225554A1
公开(公告)日：2005-10-13
申请号：US10938042
申请日：2004-09-10
申请人： Rui Bastos , Karim Abdalla , Christian Rouet , Michael Toksvig , Johnny Rhoades , Roger Allen , John Tynefield , Emmett Kilgariff , Gary Tarolli , Brian Cabral , Craig Wittenbrink , Sean Treichler
发明人： Rui Bastos , Karim Abdalla , Christian Rouet , Michael Toksvig , Johnny Rhoades , Roger Allen , John Tynefield , Emmett Kilgariff , Gary Tarolli , Brian Cabral , Craig Wittenbrink , Sean Treichler
IPC分类号： G06T15/00 , G06F15/80 , G06T1/20
CPC分类号： G06T15/005
摘要： A scalable shader architecture is disclosed. In accord with that architecture, a shader includes multiple shader pipelines, each of which can perform processing operations on rasterized pixel data. Shader pipelines can be functionally removed as required, thus preventing a defective shader pipeline from causing a chip rejection. The shader includes a shader distributor that processes rasterized pixel data and then selectively distributes the processed rasterized pixel data to the various shader pipelines, beneficially in a manner that balances workloads. A shader collector formats the outputs of the various shader pipelines into proper order to form shaded pixel data. A shader instruction processor (scheduler) programs the individual shader pipelines to perform their intended tasks. Each shader pipeline has a shader gatekeeper that interacts with the shader distributor and with the shader instruction processor such that pixel data that passes through the shader pipelines is controlled and processed as required.
摘要翻译：公开了可扩展着色器架构。根据该架构，着色器包括多个着色器管线，每个着色器管线可以对光栅化像素数据执行处理操作。着色器管线可以根据需要进行功能删除，从而防止着色器流水线造成芯片排斥。着色器包括一个着色器分配器，用于处理光栅化的像素数据，然后有选择地将经处理的光栅化像素数据分配到各种着色器管道，有利于平衡工作负载。着色器收集器将各种着色器管线的输出格式化为正确的顺序，以形成阴影像素数据。着色器指令处理器（调度器）对各个着色器管线进行编程，以执行其预期任务。每个着色器管道具有与着色器分配器和着色器指令处理器交互的着色器网守，使得通过着色器管线的像素数据被根据需要被控制和处理。

3. 发明授权

US07765500B2 Automated generation of theoretical performance analysis based upon workload and design configuration 有权
标题翻译：基于工作负载和设计配置自动生成理论性能分析
公开(公告)号：US07765500B2
公开(公告)日：2010-07-27
申请号：US11983657
申请日：2007-11-08
申请人： Ziyad Hakura , John Tynefield , Thomas Green
发明人： Ziyad Hakura , John Tynefield , Thomas Green
IPC分类号： G06F17/50
CPC分类号： G06F11/3447 , G06F11/3414 , G06F11/3457 , G06F11/3485
摘要： A method of more efficiently, easily and cost-effectively analyzing the performance of a device model is disclosed. Embodiments enable automated generation of theoretical performance analysis for a device model based upon a workload associated with rendering graphical data and a configuration of the device model. The workload may be independent of design configuration, thereby enabling determination of the workload without simulating the device model. Additionally, the design configuration may be updated or changed without re-determining the workload. Accordingly, the graphical data may comprise a general or random test which is relatively large in size and covers a relatively large operational scope of the design. Additionally, the workload may comprise graphical information determined based upon the graphical data. Further, the theoretical performance analysis may indicate a graphics pipeline unit of the device model causing a bottleneck in a graphics pipeline of the device model.
摘要翻译：公开了一种更有效，容易和经济有效地分析设备模型性能的方法。实施例能够基于与渲染图形数据和设备模型的配置相关联的工作负载来自动生成针对设备模型的理论性能分析。工作负载可以独立于设计配置，从而能够在不模拟设备模型的情况下确定工作负载。此外，可以更新或更改设计配置，而无需重新确定工作负载。因此，图形数据可以包括尺寸相对较大并且涵盖设计的较大操作范围的一般或随机测试。另外，工作负载可以包括基于图形数据确定的图形信息。此外，理论性能分析可以指示设备模型的图形流水线单元导致设备模型的图形流水线中的瓶颈。

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