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1. 发明授权

US08891324B2 Memory device from which dummy edge memory block is removed 有权
标题翻译：去除虚拟边缘存储器块的存储器件
公开(公告)号：US08891324B2
公开(公告)日：2014-11-18
申请号：US13915338
申请日：2013-06-11
申请人： Chul-woo Yi , Seong-jin Jang , Jin-seok Kwak , Tai-young Ko , Joung-yeal Kim , Sang-yun Kim , Sang-kyun Park , Jung-bae Lee
发明人： Chul-woo Yi , Seong-jin Jang , Jin-seok Kwak , Tai-young Ko , Joung-yeal Kim , Sang-yun Kim , Sang-kyun Park , Jung-bae Lee
IPC分类号： G11C7/00 , G11C5/06 , G11C7/06 , H01L27/02 , H01L27/105 , G11C7/18 , G11C11/4091 , H01L27/108
CPC分类号： G11C5/063 , G11C7/062 , G11C7/065 , G11C7/18 , G11C11/4091 , G11C11/4097 , H01L27/0207 , H01L27/105 , H01L27/10885 , H01L27/10897 , Y10T29/41
摘要： A semiconductor memory device having an open bitline memory structure from which an edge dummy memory block is removed, the semiconductor memory device includes a memory block, an edge sense amplification block including a first sense amplifier having a first bitline, a first complementary bitline, and a first amplification circuit comprising a first transistor having a first size, a central sense amplification block including a second sense amplifier having a second bitline, a second complementary bitline, and a second amplification circuit comprising a second transistor having a second size different from the first size, a capacitor block electrically connected to the edge sense amplification block.
摘要翻译：一种具有开放位线存储器结构的半导体存储器件，其中除去边缘伪存储器块，所述半导体存储器件包括存储器块，边沿读出放大块，其包括第一读出放大器，所述第一读出放大器具有第一位线，第一互补位线和第一放大电路，包括具有第一尺寸的第一晶体管，中央读出放大块，包括具有第二位线的第二读出放大器，第二互补位线和第二放大电路，所述第二放大电路包括第二晶体管，电容器块电连接到边缘检测放大块。

2. 发明申请

US20130272047A1 MEMORY DEVICE FROM WHICH DUMMY EDGE MEMORY BLOCK IS REMOVED 有权
标题翻译：删除了DUMMY边缘存储块的存储器件
公开(公告)号：US20130272047A1
公开(公告)日：2013-10-17
申请号：US13915338
申请日：2013-06-11
申请人： Chul-woo YI , Seong-jin JANG , Jin-seok KWAK , Tai-young KO , Joung-yeal KIM , Sang-yun KIM , Sang-kyun PARK , Jung-bae LEE
发明人： Chul-woo YI , Seong-jin JANG , Jin-seok KWAK , Tai-young KO , Joung-yeal KIM , Sang-yun KIM , Sang-kyun PARK , Jung-bae LEE
IPC分类号： G11C5/06
CPC分类号： G11C5/063 , G11C7/062 , G11C7/065 , G11C7/18 , G11C11/4091 , G11C11/4097 , H01L27/0207 , H01L27/105 , H01L27/10885 , H01L27/10897 , Y10T29/41
摘要： A semiconductor memory device having an open bitline memory structure from which an edge dummy memory block is removed, the semiconductor memory device includes a memory block, an edge sense amplification block including a first sense amplifier having a first bitline, a first complementary bitline, and a first amplification circuit comprising a first transistor having a first size, a central sense amplification block including a second sense amplifier having a second bitline, a second complementary bitline, and a second amplification circuit comprising a second transistor having a second size different from the first size, a capacitor block electrically connected to the edge sense amplification block.
摘要翻译：一种具有开放位线存储器结构的半导体存储器件，其中除去边缘伪存储器块，所述半导体存储器件包括存储器块，边沿读出放大块，其包括第一读出放大器，所述第一读出放大器具有第一位线，第一互补位线和第一放大电路，包括具有第一尺寸的第一晶体管，中央读出放大块，包括具有第二位线的第二读出放大器，第二互补位线和第二放大电路，所述第二放大电路包括第二晶体管，电容器块电连接到边缘检测放大块。

3. 发明申请

US20110044121A1 SEMICONDUCTOR MEMORY DEVICE HAVING DEVICE FOR CONTROLLING BIT LINE LOADING AND IMPROVING SENSING EFFICIENCY OF BIT LINE SENSE AMPLIFIER 审中-公开
标题翻译：具有用于控制位线负载的设备的半导体存储器件和提高位线感测放大器的感测效率
公开(公告)号：US20110044121A1
公开(公告)日：2011-02-24
申请号：US12860484
申请日：2010-08-20
申请人： Joung-Yeal Kim , Soo-Bong Chang , Seong-Jin Jang , Jin-Seok Kwak , Dong-Hak Shin
发明人： Joung-Yeal Kim , Soo-Bong Chang , Seong-Jin Jang , Jin-Seok Kwak , Dong-Hak Shin
IPC分类号： G11C7/06
CPC分类号： G11C11/4094 , G11C11/4091 , G11C2207/005
摘要： A semiconductor memory device includes a memory cell array block including a plurality of memory cells each connected to one of a plurality of bit lines and one of a plurality of word lines, a sense amplifier connected to a half of the plurality of bit lines, the sense amplifier for sensing and amplifying a voltage between each of the half of the bit lines and a corresponding complementary bit line; and a dummy block connected to the half of the plurality of bit lines of the memory cell array block, the dummy block for controlling a load on the memory cell array block to be different from a load on the dummy block according to a dummy load signal.
摘要翻译：半导体存储器件包括存储单元阵列块，该存储单元阵列块包括多个存储单元，每个存储单元分别连接到多个位线中的一个位线和多个字线中的一个，连接到多个位线的一半的读出放大器，读出放大器，用于感测和放大位线的每一个之间的电压和相应的互补位线; 以及连接到存储单元阵列块的多个位线的一半的虚拟块，用于根据虚拟负载信号控制存储单元阵列块上的负载与虚拟块上的负载不同的虚拟块。

4. 发明申请

US20100026373A1 Semiconductor device for charge pumping 有权
标题翻译：用于电荷泵浦的半导体器件
公开(公告)号：US20100026373A1
公开(公告)日：2010-02-04
申请号：US12458533
申请日：2009-07-15
申请人： Joung-Yeal Kim , Young-hyun Jun , Bai-sun Kong
发明人： Joung-Yeal Kim , Young-hyun Jun , Bai-sun Kong
IPC分类号： G05F1/10
CPC分类号： H02M3/07
摘要： Provided is a semiconductor device for performing charge pumping. The semiconductor device may include a first pumping unit, a second pumping unit, and a controller. The first pumping unit may be configured to output a boosted voltage via an output node by using a first input signal and the initial voltage, where the boosted voltage is greater than an initial voltage. The second pumping unit may be configured to output the boosted voltage via the output node by using a second input signal and the initial voltage. The controller may be configured to control the first and second pumping units. Each of the first and second pumping units may include an initialization unit, a boosting unit, and a transmission unit. The initialization unit may be configured to control a voltage of a boosting node to be equal to the initial voltage during an initialization operation. The boosting unit may be configured to boost the voltage of the boosting node based on the first and second input signals. Also, the transmission unit may be configured to control output of the boosted voltage.
摘要翻译：提供一种用于进行电荷泵送的半导体器件。半导体器件可以包括第一泵送单元，第二泵送单元和控制器。第一泵单元可以被配置为通过使用第一输入信号和初始电压经由输出节点输出升压电压，其中升压电压大于初始电压。第二泵送单元可以被配置为通过使用第二输入信号和初始电压经由输出节点输出升压电压。控制器可以被配置为控制第一和第二泵送单元。第一和第二泵送单元中的每一个可以包括初始化单元，升压单元和传输单元。初始化单元可以被配置为在初始化操作期间将升压节点的电压控制为等于初始电压。升压单元可以被配置为基于第一和第二输入信号来升压升压节点的电压。此外，传输单元可以被配置为控制升压电压的输出。

5. 发明申请

US20070043921A1 Wave pipelined output circuit of synchronous memory device 有权
标题翻译：同步存储设备的波形流水线输出电路
公开(公告)号：US20070043921A1
公开(公告)日：2007-02-22
申请号：US11504897
申请日：2006-08-16
申请人： Joung-yeal Kim , Seong-jin Jang
发明人： Joung-yeal Kim , Seong-jin Jang
IPC分类号： G06F13/00
CPC分类号： G11C7/1039 , G11C7/1051 , G11C7/106 , G11C7/1066 , G11C7/1069 , G11C7/1072
摘要： Provided is a wave pipelined output circuit of a synchronous memory device. In the wave pipelined output circuit, paths for transferring data in a high frequency mode of the synchronous memory device are separated from paths for transferring the data in a low frequency mode of the synchronous memory device. The number of registers included in data output paths in the high frequency mode is reduced and the number of control signals used for data input/output of the registers is also reduced. Consequently, loads of the data output paths in the high frequency mode are decreased to improve a high frequency operation and reduce the chip area of the output circuit.
摘要翻译：提供了同步存储器件的波形流水线输出电路。在波长流水线输出电路中，同步存储装置的高频模式传送数据的路径与同步存储装置的低频模式下的数据传送路径分离。包括在高频模式的数据输出路径中的寄存器数量减少，并且用于寄存器的数据输入/输出的控制信号的数量也减少。因此，降低高频模式下的数据输出路径的负载，以改善高频操作并减小输出电路的芯片面积。

6. 发明申请

US20060077748A1 Address buffer circuit and method for controlling the same 失效
公开(公告)号：US20060077748A1
公开(公告)日：2006-04-13
申请号：US11232175
申请日：2005-09-21
申请人： Sung-Hoon Kim , Joung-Yeal Kim
发明人： Sung-Hoon Kim , Joung-Yeal Kim
IPC分类号： G11C8/00
CPC分类号： G11C8/06
摘要： An address buffer circuit for a semiconductor memory device wherein an address buffer is enabled (to output an internal address signal) in response to a first level of a control signal and, but is disabled in response to a second level of the control signal. An address buffer control unit generates the control signal at the second level in ‘no operation’ state (NOP command) in which the semiconductor memory device does not perform data accessing operations and generates the control signal at the first level while the semiconductor memory device performs data accessing operations, thereby reducing or minimizing the output of an internal address buffered and output by the address buffer at and thus reducing power consumption during no-operation states of the semiconductor memory device.

7. 发明授权

US07002852B2 Data output circuits for synchronous integrated circuit memory devices 失效
标题翻译：同步集成电路存储器件的数据输出电路
公开(公告)号：US07002852B2
公开(公告)日：2006-02-21
申请号：US10632439
申请日：2003-07-31
申请人： Chang-Man Khang , Joung-Yeal Kim
发明人： Chang-Man Khang , Joung-Yeal Kim
IPC分类号： G11C16/04
CPC分类号： G11C7/1066 , G11C7/1012 , G11C7/1039 , G11C7/1051 , G11C7/1072
摘要： A data output circuit includes a plurality of registers and a plurality of register output selection switches that are respectively connected to the plurality of registers. Pairs of the plurality of register output selection switches are connected by respective common active regions. A first data group selection switch is connected to the common active regions of a first set of the plurality of register output selection switches. A second data group selection switch is connected to the common active regions of a second subset of the plurality of register output selection switches. An output driver is connected to the first and second data group selection switches.
摘要翻译：数据输出电路包括分别连接到多个寄存器的多个寄存器和多个寄存器输出选择开关。多个寄存器输出选择开关的对通过相应的公共有效区域连接。第一数据组选择开关连接到多个寄存器输出选择开关的第一组的公共有效区。第二数据组选择开关连接到多个寄存器输出选择开关的第二子集的公共有效区域。输出驱动器连接到第一和第二数据组选择开关。

8. 发明授权

US09966317B2 Semiconductor device and semiconductor package comprising the same 有权
公开(公告)号：US09966317B2
公开(公告)日：2018-05-08
申请号：US15298919
申请日：2016-10-20
申请人： Joung-Yeal Kim , Dae-Hyun Kwon , Mi-Young Woo , Joon-Sun Yoon , Jong-Hyun Choi
发明人： Joung-Yeal Kim , Dae-Hyun Kwon , Mi-Young Woo , Joon-Sun Yoon , Jong-Hyun Choi
IPC分类号： H01L21/66 , H01L23/498 , H01L49/02 , H01L27/08
CPC分类号： H01L22/32 , H01L23/49811 , H01L23/49838 , H01L27/0802 , H01L28/20
摘要： A semiconductor device may include a first terminal electrically connected to a first semiconductor chip, a second terminal electrically connected to a second semiconductor chip, which is different from the first semiconductor chip, a first signal line electrically connecting the first terminal and the second terminal and including a first node, a third terminal connected to a tester monitoring a signal transmitted between the first semiconductor chip and the second semiconductor chip, a fourth terminal applied a reference voltage, a second signal line electrically connecting the third terminal and the fourth terminal and including a second node, a first resistor connected between the first node and the second node and a second resistor directly connected to the second node different from the first resistor.

9. 发明授权

US08872436B2 Power supply device for charge pumping 有权
标题翻译：电荷泵送电源
公开(公告)号：US08872436B2
公开(公告)日：2014-10-28
申请号：US13615843
申请日：2012-09-14
申请人： Joung Yeal Kim , Su Jin Park , Young Hyun Jun
发明人： Joung Yeal Kim , Su Jin Park , Young Hyun Jun
IPC分类号： G05F1/10 , H05B37/02
CPC分类号： H02M3/07
摘要： A power supply device includes; first/second boost circuits that boost voltages applied to a first/second boost nodes in response to a first/second main signals, and respectively operated first/second transmission unit that control provision of boosted voltages to an output node. The power supply device also includes a bulk voltage controller connected between the boosted nodes and controlling a connection between the output node and a bulk node in response to a bulk control signal. Voltages respectively applied to the first and second transmission units are determined in response to an output node voltage, as well as the first/second main signals.
摘要翻译：电源装置包括：第一/第二升压电路，其响应于第一/第二主信号升压施加到第一/第二升压节点的电压，以及分别操作的第一/第二传输单元，其控制向输出节点提供升压电压。电源装置还包括连接在升压节点之间的体电压控制器，并且响应于大容量控制信号来控制输出节点和体节点之间的连接。分别施加到第一和第二传输单元的电压响应于输出节点电压以及第一/第二主信号而被确定。

10. 发明申请

US20130162159A1 POWER SUPPLY DEVICE FOR CHARGE PUMPING 有权
标题翻译：充电泵的电源装置
公开(公告)号：US20130162159A1
公开(公告)日：2013-06-27
申请号：US13615843
申请日：2012-09-14
申请人： JOUNG YEAL KIM , SU JIN PARK , YOUNG HYUN JUN
发明人： JOUNG YEAL KIM , SU JIN PARK , YOUNG HYUN JUN
IPC分类号： G05F1/10 , H05B37/02
CPC分类号： H02M3/07
摘要： A power supply device includes; first/second boost circuits that boost voltages applied to a first/second boost nodes in response to a first/second main signals, and respectively operated first/second transmission unit that control provision of boosted voltages to an output node. The power supply device also includes a bulk voltage controller connected between the boosted nodes and controlling a connection between the output node and a bulk node in response to a bulk control signal. Voltages respectively applied to the first and second transmission units are determined in response to an output node voltage, as well as the first/second main signals.
摘要翻译：电源装置包括：第一/第二升压电路，其响应于第一/第二主信号升压施加到第一/第二升压节点的电压，以及分别操作的第一/第二传输单元，其控制向输出节点提供升压电压。电源装置还包括连接在升压节点之间的体电压控制器，并且响应于大容量控制信号来控制输出节点和体节点之间的连接。分别施加到第一和第二传输单元的电压响应于输出节点电压以及第一/第二主信号而被确定。

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