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1. 发明申请

US20050024947A1 Data output circuits for synchronous integrated circuit memory devices 失效
标题翻译：同步集成电路存储器件的数据输出电路
公开(公告)号：US20050024947A1
公开(公告)日：2005-02-03
申请号：US10632439
申请日：2003-07-31
申请人： Chang-Man Khang , Joung-Yeal Kim
发明人： Chang-Man Khang , Joung-Yeal Kim
IPC分类号： G11C11/40 , G11C5/00 , G11C7/10 , G11C11/4093
CPC分类号： G11C7/1066 , G11C7/1012 , G11C7/1039 , G11C7/1051 , G11C7/1072
摘要： A data output circuit includes a plurality of registers and a plurality of register output selection switches that are respectively connected to the plurality of registers. Pairs of the plurality of register output selection switches are connected by respective common active regions. A first data group selection switch is connected to the common active regions of a first set of the plurality of register output selection switches. A second data group selection switch is connected to the common active regions of a second subset of the plurality of register output selection switches. An output driver is connected to the first and second data group selection switches.
摘要翻译：数据输出电路包括分别连接到多个寄存器的多个寄存器和多个寄存器输出选择开关。多个寄存器输出选择开关的对通过相应的公共有效区域连接。第一数据组选择开关连接到多个寄存器输出选择开关的第一组的公共有效区。第二数据组选择开关连接到多个寄存器输出选择开关的第二子集的公共有效区域。输出驱动器连接到第一和第二数据组选择开关。

2. 发明授权

US07002852B2 Data output circuits for synchronous integrated circuit memory devices 失效
标题翻译：同步集成电路存储器件的数据输出电路
公开(公告)号：US07002852B2
公开(公告)日：2006-02-21
申请号：US10632439
申请日：2003-07-31
申请人： Chang-Man Khang , Joung-Yeal Kim
发明人： Chang-Man Khang , Joung-Yeal Kim
IPC分类号： G11C16/04
CPC分类号： G11C7/1066 , G11C7/1012 , G11C7/1039 , G11C7/1051 , G11C7/1072
摘要： A data output circuit includes a plurality of registers and a plurality of register output selection switches that are respectively connected to the plurality of registers. Pairs of the plurality of register output selection switches are connected by respective common active regions. A first data group selection switch is connected to the common active regions of a first set of the plurality of register output selection switches. A second data group selection switch is connected to the common active regions of a second subset of the plurality of register output selection switches. An output driver is connected to the first and second data group selection switches.
摘要翻译：数据输出电路包括分别连接到多个寄存器的多个寄存器和多个寄存器输出选择开关。多个寄存器输出选择开关的对通过相应的公共有效区域连接。第一数据组选择开关连接到多个寄存器输出选择开关的第一组的公共有效区。第二数据组选择开关连接到多个寄存器输出选择开关的第二子集的公共有效区域。输出驱动器连接到第一和第二数据组选择开关。

3. 发明授权

US5883845A Semiconductor memory having bitline precharge circuit 失效
公开(公告)号：US5883845A
公开(公告)日：1999-03-16
申请号：US126600
申请日：1998-07-31
申请人： Chang-Man Khang
发明人： Chang-Man Khang
IPC分类号： H01L27/10 , G11C7/12 , H01L27/108 , G11C13/00
CPC分类号： H01L27/10805 , G11C7/12
摘要： A semiconductor device is provided having a symmetric bitline precharge circuit. Sizes of a parasitic devices near transistors lying symmetrically in the bitline precharge circuit are symmetrical to each other. Further, a layout area occupied by the bitline precharge circuit or a chip is reduced or minimized by the symmetric layout. The device can include a memory having first and second bitline extending in parallel a first direction a bitline precharge voltage supplying line and a bitline equalizing signal line extending in parallel in a second direction perpendicular to the first direction. A gate has at least a first part extending in the first direction, a second part having a first predetermined length extending in the second direction coupled to the first part and a third part having a second predetermined length extending in the second direction coupled to the first part with contact areas at uncoupled ends. An active region is on portions of the first and second bitline, the bitline precharge voltage supplying line, the first part and the second part of the gate. A first contact located between the first and second bitline to electrically couples the bitline precharge voltage supplying line and the active region. Second and third contacts electrically couple the gate to the bitline equalizing signal line, and fourth and firth contacts electrically couple the first and the second bitlines to the active region.

4. 发明授权

US5889724A Word line driving circuit for semiconductor memory device and method 失效
标题翻译：半导体存储器件的字线驱动电路及方法
公开(公告)号：US5889724A
公开(公告)日：1999-03-30
申请号：US992572
申请日：1997-12-17
申请人： Chang-Man Khang , Chang-Jin Lee
发明人： Chang-Man Khang , Chang-Jin Lee
IPC分类号： G11C11/413 , G11C8/10 , G11C11/407 , G11C8/00 , G11C7/00
CPC分类号： G11C8/10
摘要： A word line driving circuit for a semiconductor memory is provided that drives a corresponding word line of a first number of word lines coupled to a plurality of memory cells based on a memory address signal generated from a more significant controller. The memory cells have a matrix form of rows and columns and the first number of word lines are divided into a second number of word line groups. The word line driving circuit includes a second number of word line group driving circuits each respectively coupled to one of the second number of word line groups to drive one of the word lines in the word line group selected by a control signal. A word line selecting circuit determines which of the second word line groups contain the corresponding word line to be driven using the memory address signal and generates the control signal for the corresponding word line group driving circuit.
摘要翻译：提供一种用于半导体存储器的字线驱动电路，其基于从更重要的控制器产生的存储器地址信号驱动耦合到多个存储器单元的第一数量字线的对应字线。存储单元具有行和列的矩阵形式，并且第一数量的字线被划分为第二数量的字线组。字线驱动电路包括第二数量的字线组驱动电路，每个字线组驱动电路分别耦合到第二数量的字线组中的一个，以驱动由控制信号选择的字线组中的一个字线。字线选择电路使用存储器地址信号确定哪个第二字线组包含要驱动的对应字线，并且产生对应的字线组驱动电路的控制信号。

5. 发明授权

US06856164B2 Semiconductor integrated circuit having on-chip termination 有权
标题翻译：具有片上终端的半导体集成电路
公开(公告)号：US06856164B2
公开(公告)日：2005-02-15
申请号：US10426687
申请日：2003-05-01
申请人： Youn-Sik Park , Chang-Man Khang
发明人： Youn-Sik Park , Chang-Man Khang
IPC分类号： G11C5/02 , H04L25/02 , H03K19/003
CPC分类号： H04L25/028 , H04L25/0278 , H04L25/0292
摘要： A semiconductor integrated circuit includes at least one pad coupled to a bus line, a transmitter for transmitting a signal from an internal circuit to the outside through the pad, and a termination circuit for terminating the bus line. The transmitter and the termination circuit are disposed to surround the pad, reducing a size of the semiconductor integrated circuit.
摘要翻译：半导体集成电路包括耦合到总线的至少一个焊盘，用于通过焊盘将信号从内部电路发送到外部的发射器，以及用于终止总线的终端电路。发射机和终端电路被设置成围绕焊盘，减小了半导体集成电路的尺寸。

6. 发明授权

US5963494A Semiconductor memory having bitline precharge circuit 有权
标题翻译：具有位线预充电电路的半导体存储器
公开(公告)号：US5963494A
公开(公告)日：1999-10-05
申请号：US258788
申请日：1999-03-01
申请人： Chang-Man Khang
发明人： Chang-Man Khang
IPC分类号： G11C7/12 , G11C11/4094 , H01L21/8242 , H01L27/108 , G11C13/00
CPC分类号： H01L27/10885 , G11C11/4094 , G11C7/12 , H01L27/10897
摘要： A semiconductor device is provided having a symmetric bitline precharge circuit. Sizes of a parasitic devices near transistors lying symmetrically in the bitline precharge circuit are symmetrical to each other. Further, a layout area occupied by the bitline precharge circuit or a chip is reduced or minimized by the symmetric layout. The device can include a memory having first and second bitline extending in parallel a first direction a bitline precharge voltage supplying line and a bitline equalizing signal line extending in parallel in a second direction perpendicular to the first direction. A gate has at least a first part extending in the first direction, a second part having a first predetermined length extending in the second direction coupled to the first part and a third part having a second predetermined length extending in the second direction coupled to the first part with contact areas at uncoupled ends. An active region is on portions of the first and second bitline, the bitline precharge voltage supplying line, the first part and the second part of the gate. A first contact located between the first and second bitline to electrically couples the bitline precharge voltage supplying line and the active region. Second and third contacts electrically couple the gate to the bitline equalizing signal line, and fourth and firth contacts electrically couple the first and the second bitlines to the active region.
摘要翻译：提供具有对称位线预充电电路的半导体器件。在位线预充电电路对称的晶体管附近的寄生器件的尺寸彼此对称。此外，由位线预充电电路或芯片占用的布局面积通过对称布局减小或最小化。该装置可以包括具有第一和第二位线的第一和第二位线的存储器，第一和第二位线在第一方向上平行延伸，位线预充电电压供应线和位于垂直于第一方向的第二方向上并行延伸的位线均衡信号线。门具有至少第一部分，其在第一方向上延伸，第二部分具有在耦合到第一部分的第二方向上延伸的第一预定长度，以及具有第二预定长度的第三部分，该第二预定长度在第二方向上延伸，部分与非耦合端的接触区域。有源区域位于第一和第二位线，位线预充电电压供给线，栅极的第一部分和第二部分的一部分上。位于第一和第二位线之间的第一触点，用于电耦合位线预充电电压线和有源区。第二和第三触点将栅极电耦合到位线均衡信号线，第四和第三触点将第一和第二位线电耦合到有源区。

7. 发明授权

US06667895B2 Integrated circuit device and module with integrated circuits 失效
公开(公告)号：US06667895B2
公开(公告)日：2003-12-23
申请号：US10192901
申请日：2002-07-10
申请人： Seong-Jin Jang , Young-Hyun Jun , Chang-Man Khang
发明人： Seong-Jin Jang , Young-Hyun Jun , Chang-Man Khang
IPC分类号： G11C506
CPC分类号： G11C5/063 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit comprises a substrate having circuitry integrated with the substrate. Switching circuitry is selectably operable to configure signal paths to alternative mirrored pads over the substrate. At least one of the first and second signal paths may comprise a buffer in series between the switching circuit and its respective pad.

8. 发明授权

US6075736A Semiconductor memory device with improved sense amplifier driver 有权
标题翻译：具有改善的读出放大器驱动器的半导体存储器件
公开(公告)号：US6075736A
公开(公告)日：2000-06-13
申请号：US179564
申请日：1998-10-27
申请人： Ha-Soo Kim , Jae-Goo Lee , Chang-Man Khang , Tae-Hyoung Kim
发明人： Ha-Soo Kim , Jae-Goo Lee , Chang-Man Khang , Tae-Hyoung Kim
IPC分类号： G11C11/41 , G06F9/34 , G11C7/06 , G11C11/401 , G11C11/407 , G11C11/409 , H01L21/8242 , H01L27/108 , G11C7/02
CPC分类号： G11C7/06
摘要： The semiconductor memory according to the present invention employs a plurality of sense amplifier drivers which individually control the sense amplifiers, or control groups of sense amplifiers, in the semiconductor memory. More specifically, the sense amplifier drivers control whether associated sense amplifiers are connected to sense amplifier array input/output lines. In this manner fewer sense amplifiers are connected to the sense amplifier array input/output lines, reducing overall current consumption.
摘要翻译：根据本发明的半导体存储器采用多个读出放大器驱动器，其分别控制半导体存储器中的读出放大器或读出放大器的控制组。更具体地，读出放大器驱动器控制相关读出放大器是否连接到读出放大器阵列输入/输出线。以这种方式，较少的读出放大器连接到读出放大器阵列输入/输出线，从而降低总体电流消耗。

9. 发明授权

US6011743A Charge pump circuit for memory device 有权
标题翻译：用于存储器件的电荷泵电路
公开(公告)号：US6011743A
公开(公告)日：2000-01-04
申请号：US131384
申请日：1998-08-07
申请人： Chang-Man Khang
发明人： Chang-Man Khang
IPC分类号： G11C5/14 , G11C7/12 , G11C11/4074 , G11C11/4094 , G11C7/00
CPC分类号： G11C7/12 , G11C11/4074 , G11C11/4094 , G11C5/145
摘要： The present invention relates to a charge pump circuit for memory device, more particularly to a circuit charging cell capacitors or bitlines up to a full level of power supply voltage by means of compensating for the loss caused by the threshold voltages of memory transistors with the elevated potential higher than the power supply voltage.The present invention includes an elevated potential terminal connected to an output capacitor, a level monitor connected to said elevated potential terminal wherein a certain range of voltage is divided into a plurality of voltage level intervals, and the level monitor generates a plurality of pumping enable signals corresponding to a plurality of the voltage level intervals, and a plurality of the pumping enable signals have different activated time one another, and the level monitor activates the pumping enable signals corresponding to the voltage level intervals to which the elevated potential belongs among the voltage level intervals by means of detecting the elevated potential, a pulse generator connected to the level monitor wherein the pulse generator generates a pulse signal, and wherein at least one of the pumping enable signals is activated, and a plurality of charge pump modules connected to the pulse generator wherein the charge pump modules are enabled by the pumping enable signals, and wherein the charge pump modules supplies the output capacitor with electric charge with pumping operation by the pulse signals.
摘要翻译：本发明涉及一种用于存储器件的电荷泵电路，更具体地说，涉及通过补偿存储晶体管的阈值电压引起的损耗而使电池充电电池或位线达到全电平电压的电路，电位高于电源电压。本发明包括连接到输出电容器的升高的电位端子，连接到所述升高的电位端子的电平监视器，其中一定范围的电压被分成多个电压电平间隔，并且电平监视器产生多个泵浦使能信号对应于多个电压电平间隔，并且多个泵送使能信号彼此具有不同的激活时间，并且电平监视器激活对应于升高的电位属于电压电平的电压电平间隔的泵浦使能信号通过检测升高的电位的间隔;连接到电平监视器的脉冲发生器，其中所述脉冲发生器产生脉冲信号，并且其中至少一个所述泵浦使能信号被激活，并且多个电荷泵模块连接到所述脉冲发电机，其中电荷泵模块通过泵送启动使能并且其中电荷泵模块通过脉冲信号向输出电容器提供具有泵浦操作的电荷。

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