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1. 发明授权

US08189406B2 Device and method generating internal voltage in semiconductor memory device 有权
标题翻译：在半导体存储器件中产生内部电压的器件和方法
公开(公告)号：US08189406B2
公开(公告)日：2012-05-29
申请号：US12978677
申请日：2010-12-27
申请人： Soo-Bong Chang , Doo-Young Kim , Jung-Im Huh
发明人： Soo-Bong Chang , Doo-Young Kim , Jung-Im Huh
IPC分类号： G11C5/14
CPC分类号： G11C5/147
摘要： A semiconductor memory device and a method of generating an internal voltage in the semiconductor memory device are provided. The semiconductor memory device includes a controller configured to activate a sensing enable signal when an active command is applied from outside, inactivate the sensing enable signal when a precharge command is applied, and output the sensing enable signal, and an array internal voltage generator configured to output an active array power supply voltage as an array power supply voltage when the sensing enable signal is activated, output an external array power supply voltage and a standby array power supply voltage as the array power supply voltage when the sensing enable signal is inactivated, and output the standby array power supply voltage alone as the array power supply voltage when the sensing enable signal is inactivated for at least a specific period.
摘要翻译：提供半导体存储器件和在半导体存储器件中产生内部电压的方法。半导体存储器件包括：控制器，被配置为当从外部施加有效命令时激活感测使能信号，当施加预充电命令时使感测使能信号失效，并输出感测使能信号;以及阵列内部电压发生器，被配置为当感测使能信号被激活时，输出有源阵列电源电压作为阵列电源电压，当感测使能信号被去激活时，输出外部阵列电源电压和备用阵列电源电压作为阵列电源电压;以及当感测使能信号在至少特定的时间段内被去激活时，单独输出备用阵列电源电压作为阵列电源电压。

2. 发明申请

US20110044121A1 SEMICONDUCTOR MEMORY DEVICE HAVING DEVICE FOR CONTROLLING BIT LINE LOADING AND IMPROVING SENSING EFFICIENCY OF BIT LINE SENSE AMPLIFIER 审中-公开
标题翻译：具有用于控制位线负载的设备的半导体存储器件和提高位线感测放大器的感测效率
公开(公告)号：US20110044121A1
公开(公告)日：2011-02-24
申请号：US12860484
申请日：2010-08-20
申请人： Joung-Yeal Kim , Soo-Bong Chang , Seong-Jin Jang , Jin-Seok Kwak , Dong-Hak Shin
发明人： Joung-Yeal Kim , Soo-Bong Chang , Seong-Jin Jang , Jin-Seok Kwak , Dong-Hak Shin
IPC分类号： G11C7/06
CPC分类号： G11C11/4094 , G11C11/4091 , G11C2207/005
摘要： A semiconductor memory device includes a memory cell array block including a plurality of memory cells each connected to one of a plurality of bit lines and one of a plurality of word lines, a sense amplifier connected to a half of the plurality of bit lines, the sense amplifier for sensing and amplifying a voltage between each of the half of the bit lines and a corresponding complementary bit line; and a dummy block connected to the half of the plurality of bit lines of the memory cell array block, the dummy block for controlling a load on the memory cell array block to be different from a load on the dummy block according to a dummy load signal.
摘要翻译：半导体存储器件包括存储单元阵列块，该存储单元阵列块包括多个存储单元，每个存储单元分别连接到多个位线中的一个位线和多个字线中的一个，连接到多个位线的一半的读出放大器，读出放大器，用于感测和放大位线的每一个之间的电压和相应的互补位线; 以及连接到存储单元阵列块的多个位线的一半的虚拟块，用于根据虚拟负载信号控制存储单元阵列块上的负载与虚拟块上的负载不同的虚拟块。

3. 发明授权

US07660141B2 Layout structures and methods of fabricating layout structures 失效
标题翻译：制作布局结构的布局结构和方法
公开(公告)号：US07660141B2
公开(公告)日：2010-02-09
申请号：US11878066
申请日：2007-07-20
申请人： Soo-bong Chang
发明人： Soo-bong Chang
IPC分类号： G11C5/06
CPC分类号： G11C7/18 , G11C7/065 , G11C7/08 , G11C7/12 , G11C11/4091 , G11C11/4094 , G11C11/4097 , H01L27/0207 , H01L27/105 , H01L27/10885 , H01L27/10897
摘要： Example embodiments may provide a layout structure and layout method for a memory device that may reduce the area of the memory device. Example embodiment layout structures may include a first region and/or a second region. First and second sensing MOS transistors of a sense amplifier that senses data of a bit line and a complementary bit line may be arranged in the first region. First, second and third equalization MOS transistors of an equalizer that equalizes the bit line and the complementary bit line may be arranged In the second region located apart from the first region, Sensing NMOS transistors and equalization NMOS transistors may share an N-type active region in the layout structure of a memory device, and the area of a sense amplifier may be reduced.
摘要翻译：示例性实施例可以提供可以减小存储器件的面积的存储器件的布局结构和布局方法。示例性实施例布局结构可以包括第一区域和/或第二区域。可以在第一区域中布置感测位线和互补位线的数据的读出放大器的第一和第二感测MOS晶体管。首先，均衡器的均衡器的第二和第三均衡MOS晶体管可以被布置在与第一区域分开的第二区域中，感测NMOS晶体管和均衡NMOS晶体管可以共享N型有源区在存储器件的布局结构中，可以减小读出放大器的面积。

4. 发明授权

US07336518B2 Layout for equalizer and data line sense amplifier employed in a high speed memory device 有权
标题翻译：用于高速存储器件中的均衡器和数据线读出放大器的布局
公开(公告)号：US07336518B2
公开(公告)日：2008-02-26
申请号：US11383727
申请日：2006-05-16
申请人： Soo-Bong Chang , Chi-Wook Kim
发明人： Soo-Bong Chang , Chi-Wook Kim
IPC分类号： G11C5/02
CPC分类号： G11C7/1048 , G11C7/062 , G11C11/4091 , G11C11/4093
摘要： A memory device includes a memory cell array block including memory cells, a word line driver block adjacent the memory cell array block disposed in a direction in which word lines of the memory cells are arranged, a sense amplifier block adjacent the memory cell array block disposed in a direction in which bit lines of the memory cells are arranged, a conjunction block disposed at an intersection of the word line driver block and the sense amplifier block, an equalizer for equalizing a pair of local data lines, the equalizer disposed in the conjunction block, and a local data line sense amplifier configured to sense and amplify signals on a pair of local data lines, and having transistors of a first type disposed in the conjunction block and transistors of a second type disposed in the sense amplifier block.
摘要翻译：存储器件包括存储单元阵列块，存储单元阵列块，与沿着存储单元的字线排列的方向布置的存储单元阵列块相邻的字线驱动块，设置有存储单元阵列块的读出放大器块在布置存储单元的位线的方向上，设置在字线驱动块和读出放大器块的交叉点处的连接块，用于均衡一对本地数据线的均衡器，均衡器配置在一起块和本地数据线读出放大器，其被配置为感测和放大一对本地数据线上的信号，并且具有布置在连接块中的第一类型的晶体管和布置在读出放大器块中的第二类型的晶体管。

5. 发明申请

US20110090746A1 DEVICE AND METHOD GENERATING INTERNAL VOLTAGE IN SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：在半导体存储器件中产生内部电压的器件和方法
公开(公告)号：US20110090746A1
公开(公告)日：2011-04-21
申请号：US12978677
申请日：2010-12-27
申请人： Soo-Bong CHANG , Doo-Young KIM , Jung-Im HUH
发明人： Soo-Bong CHANG , Doo-Young KIM , Jung-Im HUH
IPC分类号： G11C5/14
CPC分类号： G11C5/147
摘要： A semiconductor memory device and a method of generating an internal voltage in the semiconductor memory device are provided. The semiconductor memory device includes a controller configured to activate a sensing enable signal when an active command is applied from outside, inactivate the sensing enable signal when a precharge command is applied, and output the sensing enable signal, and an array internal voltage generator configured to output an active array power supply voltage as an array power supply voltage when the sensing enable signal is activated, output an external array power supply voltage and a standby array power supply voltage as the array power supply voltage when the sensing enable signal is inactivated, and output the standby array power supply voltage alone as the array power supply voltage when the sensing enable signal is inactivated for at least a specific period.
摘要翻译：提供半导体存储器件和在半导体存储器件中产生内部电压的方法。半导体存储器件包括：控制器，被配置为当从外部施加有效命令时激活感测使能信号，当施加预充电命令时使感测使能信号失效，并输出感测使能信号;以及阵列内部电压发生器，被配置为当感测使能信号被激活时，输出有源阵列电源电压作为阵列电源电压，当感测使能信号被去激活时，输出外部阵列电源电压和备用阵列电源电压作为阵列电源电压;以及当感测使能信号在至少特定的时间段内被去激活时，单独输出备用阵列电源电压作为阵列电源电压。

6. 发明申请

US20090207674A1 DEVICE AND METHOD GENERATING INTERNAL VOLTAGE IN SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：在半导体存储器件中产生内部电压的器件和方法
公开(公告)号：US20090207674A1
公开(公告)日：2009-08-20
申请号：US12372290
申请日：2009-02-17
申请人： Soo-Bong Chang , Doo-Young Kim , Jung-Im Huh
发明人： Soo-Bong Chang , Doo-Young Kim , Jung-Im Huh
IPC分类号： G11C7/00 , G11C5/14
CPC分类号： G11C5/147
摘要： A semiconductor memory device and a method of generating an internal voltage in the semiconductor memory device are provided. The semiconductor memory device includes a controller configured to activate a sensing enable signal when an active command is applied from outside, inactivate the sensing enable signal when a precharge command is applied, and output the sensing enable signal, and an array internal voltage generator configured to output an active array power supply voltage as an array power supply voltage when the sensing enable signal is activated, output an external array power supply voltage and a standby array power supply voltage as the array power supply voltage when the sensing enable signal is inactivated, and output the standby array power supply voltage alone as the array power supply voltage when the sensing enable signal is inactivated for at least a specific period.
摘要翻译：提供半导体存储器件和在半导体存储器件中产生内部电压的方法。半导体存储器件包括：控制器，被配置为当从外部施加有效命令时激活感测使能信号，当施加预充电命令时使感测使能信号失效，并输出感测使能信号;以及阵列内部电压发生器，被配置为当感测使能信号被激活时，输出有源阵列电源电压作为阵列电源电压，当感测使能信号被去激活时，输出外部阵列电源电压和备用阵列电源电压作为阵列电源电压;以及当感测使能信号在至少特定的时间段内被去激活时，单独输出备用阵列电源电压作为阵列电源电压。

7. 发明申请

US20080062790A1 BIT-LINE EQUALIZER, SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME, AND METHOD FOR MANUFACTURING BIT-LINE EQUALIZER 有权
标题翻译：位线均衡器，包括其的半导体存储器件以及制造位线均衡器的方法
公开(公告)号：US20080062790A1
公开(公告)日：2008-03-13
申请号：US11756725
申请日：2007-06-01
申请人： Soo-bong Chang , Jung-hwa Lee
发明人： Soo-bong Chang , Jung-hwa Lee
IPC分类号： G11C7/00 , H01L21/82
CPC分类号： H01L27/10897 , G11C7/12 , G11C11/4094 , H01L27/0207
摘要： A bit-line equalizer, a semiconductor memory device including the bit-line equalizer, and a method for manufacturing the bit-line equalizer, in which the bit-line equalizer includes: first and second polysilicon gates formed in a first direction in proximity to each other, the first and second polysilicon gates having a predetermined distance between them; and a plurality of equalizing transistors formed in a second direction along the first and second polysilicon gates, the equalizing transistors equalizing bit-line pairs, with the equalizing transistors being alternately formed in proximity to the first and second polysilicon gates. The bit-line equalizer can vary the widths of the equalizing transistors irrespective of a memory cell pitch in order to improve an equalizing time.
摘要翻译：位线均衡器，包括位线均衡器的半导体存储器件和用于制造位线均衡器的方法，其中位线均衡器包括：第一和第二多晶硅栅极，形成在靠近彼此之间，第一和第二多晶硅栅极之间具有预定的距离; 以及沿着第一和第二多晶硅栅极沿第二方向形成的多个均衡晶体管，均衡晶体管均衡位线对，均衡晶体管交替地形成在第一和第二多晶硅栅极附近。位线均衡器可以改变均衡晶体管的宽度，而与存储单元间距无关，以便改善均衡时间。

8. 发明申请

US20060163613A1 Layout structure for sub word line drivers and method thereof 有权
标题翻译：子字线驱动器的布局结构及其方法
公开(公告)号：US20060163613A1
公开(公告)日：2006-07-27
申请号：US11336831
申请日：2006-01-23
申请人： Soo-Bong Chang , In-Chul Jeong , Jun-Hyung Kim , Seung-Min Oh , Jung-Hwa Lee
发明人： Soo-Bong Chang , In-Chul Jeong , Jun-Hyung Kim , Seung-Min Oh , Jung-Hwa Lee
IPC分类号： H01L27/10
CPC分类号： H01L27/0207 , H01L27/105 , H01L27/11898
摘要： A layout structure for sub word line drivers and method thereof. The example layout structure may include at least one N-channel transistor arrangement having a cross sectional width and a cross sectional length, the N-channel transistor arrangement oriented such that the cross sectional length extends along a first direction, the first direction oriented along a sub word line driver from a first sub array block to a second sub array block. The example method may arrange the at least one N-channel transistor between the first and second sub array blocks.
摘要翻译：子字线驱动器的布局结构及其方法。示例性布局结构可以包括具有横截面宽度和横截面长度的至少一个N沟道晶体管布置，N沟道晶体管布置方向使得横截面长度沿着第一方向延伸，第一方向沿着第一方向子字线驱动器从第一子阵列块到第二子阵列块。该示例性方法可以在第一和第二子阵列块之间布置至少一个N沟道晶体管。

9. 发明授权

US06327190B1 Complementary differential input buffer for a semiconductor memory device 有权
标题翻译：用于半导体存储器件的互补差分输入缓冲器
公开(公告)号：US06327190B1
公开(公告)日：2001-12-04
申请号：US09521904
申请日：2000-03-09
申请人： Kyu-hyoun Kim , Soo-bong Chang
发明人： Kyu-hyoun Kim , Soo-bong Chang
IPC分类号： G11C700
CPC分类号： G11C7/1084 , G11C7/1078
摘要： An input buffer of a semiconductor memory device includes a first differential amplifying portion including a first MOS transistor for receiving a first external input signal and a second MOS transistor for receiving a second external input signal. The voltage difference between the first and second external input signals is amplified and output as a first intermediate output voltage. A second differential amplifying portion includes a third MOS transistor for receiving the first external input signal and a fourth MOS transistor for receiving the second external input signal. The voltage difference between the first and second external input signals are amplified and output as a second intermediate output voltage. The first intermediate output of the first amplifying portion is combined with the second intermediate output of the second amplifying portion and the combined result is output as an output signal. The input buffer is less susceptible to fluctuations in ground and supply voltage levels due to noise, and the set-up time and hold time margins of the output signal are improved.
摘要翻译：半导体存储器件的输入缓冲器包括：第一差分放大部分，包括用于接收第一外部输入信号的第一MOS晶体管和用于接收第二外部输入信号的第二MOS晶体管。第一和第二外部输入信号之间的电压差被放大并作为第一中间输出电压输出。第二差分放大部分包括用于接收第一外部输入信号的第三MOS晶体管和用于接收第二外部输入信号的第四MOS晶体管。第一和第二外部输入信号之间的电压差被放大并作为第二中间输出电压输出。第一放大部分的第一中间输出与第二放大部分的第二中间输出相结合，并且输出组合结果作为输出信号。输入缓冲器由于噪声而不易受到接地波动和电源电压的影响，并且输出信号的建立时间和保持时间余量得到改善。

10. 发明授权

US07864599B2 Device and method generating internal voltage in semiconductor memory device 有权
标题翻译：在半导体存储器件中产生内部电压的器件和方法
公开(公告)号：US07864599B2
公开(公告)日：2011-01-04
申请号：US12372290
申请日：2009-02-17
申请人： Soo-Bong Chang , Doo-Young Kim , Jung-Im Huh
发明人： Soo-Bong Chang , Doo-Young Kim , Jung-Im Huh
IPC分类号： G11C5/14
CPC分类号： G11C5/147
摘要： A semiconductor memory device and a method of generating an internal voltage in the semiconductor memory device are provided. The semiconductor memory device includes a controller configured to activate a sensing enable signal when an active command is applied from outside, inactivate the sensing enable signal when a precharge command is applied, and output the sensing enable signal, and an array internal voltage generator configured to output an active array power supply voltage as an array power supply voltage when the sensing enable signal is activated, output an external array power supply voltage and a standby array power supply voltage as the array power supply voltage when the sensing enable signal is inactivated, and output the standby array power supply voltage alone as the array power supply voltage when the sensing enable signal is inactivated for at least a specific period.
摘要翻译：提供半导体存储器件和在半导体存储器件中产生内部电压的方法。半导体存储器件包括：控制器，被配置为当从外部施加有效命令时激活感测使能信号，当施加预充电命令时使感测使能信号失效，并输出感测使能信号;以及阵列内部电压发生器，被配置为当感测使能信号被激活时，输出有源阵列电源电压作为阵列电源电压，当感测使能信号被去激活时，输出外部阵列电源电压和备用阵列电源电压作为阵列电源电压;以及当感测使能信号在至少特定的时间段内被去激活时，单独输出备用阵列电源电压作为阵列电源电压。

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