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1. 发明授权

US6111808A Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US6111808A
公开(公告)日：2000-08-29
申请号：US258795
申请日：1999-03-01
申请人： Chang Man Khang , Young Hyun Jun
发明人： Chang Man Khang , Young Hyun Jun
IPC分类号： G11C11/418 , G11C8/10 , G11C11/401 , G11C11/407 , G11C11/408 , G11C8/00
CPC分类号： G11C8/10 , G11C11/4087
摘要： Disclose is a semiconductor memory device including a plurality of memory cell arrays, row and column decoders for selecting/driving each memory cell, and a plurality of bit line sensing amplifier arrays for sensing data of each memory cell, the semiconductor memory device comprising: a plurality of sub word line driver sections for driving each memory cell with a sub word line enable selection signal (SWLE) decoded by LSB address and with a global word line signal (GWLb) decoded by MSB address in the row decoder; a row decoding precharge signal generating section (RDPRi/VBFi) for applying a precharge signal to the row decoder and a voltage Vbb to the GWLb signal by means of the MSB address PXb; a level shifting section for shifting and transmitting an output signal from the column decoder to column selection lines which connects the column decoder with the bit line sensing amplifier array in series; and a data input/output controlling section for selectively applying an active signal to the bit line sensing amplifier array according to a level of the column selection line.
摘要翻译： Disclose是包括多个存储单元阵列，用于选择/驱动每个存储单元的行和列解码器以及用于感测每个存储单元的数据的多位位线检测放大器阵列的半导体存储器件，该半导体存储器件包括：多个子字线驱动器部分，用于通过LSB地址解码的子字线使能选择信号（SWLE）和行解码器中由MSB地址解码的全局字线信号（GWLb）来驱动每个存储器单元; 用于通过MSB地址PXb向行解码器施加预充电信号的行解码预充电信号产生部分（RDPRi / VBFi）和对GWLb信号的电压Vbb; 电平移位部分，用于将来自列解码器的输出信号移位和发送到将列解码器与位线感测放大器阵列串联连接的列选择线; 以及数据输入/输出控制部分，用于根据列选择线的电平有选择地将有效信号施加到位线感测放大器阵列。

2. 发明授权

US6049503A Wordline driving circuit in semiconductor memory 有权
标题翻译：半导体存储器中的字线驱动电路
公开(公告)号：US6049503A
公开(公告)日：2000-04-11
申请号：US166075
申请日：1998-10-05
申请人： Chang Man Khang
发明人： Chang Man Khang
IPC分类号： G11C11/41 , G11C7/02 , G11C8/08 , G11C8/10 , G11C8/14 , G11C11/34 , G11C11/401 , G11C11/407 , G11C16/06 , G11C8/00
CPC分类号： G11C8/10 , G11C8/08 , G11C8/14
摘要： The wordline driving circuit includes a noise prevention circuit in each control circuit of a subwordline drive selector. When a row signal from a sub-row decoder indicates that the associated control circuits are not to drive wordlines associated therewith, the noise prevention circuit in each control circuit is triggered to remove noise from the wordline.
摘要翻译：字线驱动电路包括在字幕驱动选择器的每个控制电路中的噪声防止电路。当来自子行解码器的行信号指示相关联的控制电路不驱动与其相关联的字线时，每个控制电路中的噪声防止电路被触发以从字线中去除噪声。

3. 发明授权

US5883845A Semiconductor memory having bitline precharge circuit 失效
公开(公告)号：US5883845A
公开(公告)日：1999-03-16
申请号：US126600
申请日：1998-07-31
申请人： Chang-Man Khang
发明人： Chang-Man Khang
IPC分类号： H01L27/10 , G11C7/12 , H01L27/108 , G11C13/00
CPC分类号： H01L27/10805 , G11C7/12
摘要： A semiconductor device is provided having a symmetric bitline precharge circuit. Sizes of a parasitic devices near transistors lying symmetrically in the bitline precharge circuit are symmetrical to each other. Further, a layout area occupied by the bitline precharge circuit or a chip is reduced or minimized by the symmetric layout. The device can include a memory having first and second bitline extending in parallel a first direction a bitline precharge voltage supplying line and a bitline equalizing signal line extending in parallel in a second direction perpendicular to the first direction. A gate has at least a first part extending in the first direction, a second part having a first predetermined length extending in the second direction coupled to the first part and a third part having a second predetermined length extending in the second direction coupled to the first part with contact areas at uncoupled ends. An active region is on portions of the first and second bitline, the bitline precharge voltage supplying line, the first part and the second part of the gate. A first contact located between the first and second bitline to electrically couples the bitline precharge voltage supplying line and the active region. Second and third contacts electrically couple the gate to the bitline equalizing signal line, and fourth and firth contacts electrically couple the first and the second bitlines to the active region.

4. 发明申请

US20050024947A1 Data output circuits for synchronous integrated circuit memory devices 失效
标题翻译：同步集成电路存储器件的数据输出电路
公开(公告)号：US20050024947A1
公开(公告)日：2005-02-03
申请号：US10632439
申请日：2003-07-31
申请人： Chang-Man Khang , Joung-Yeal Kim
发明人： Chang-Man Khang , Joung-Yeal Kim
IPC分类号： G11C11/40 , G11C5/00 , G11C7/10 , G11C11/4093
CPC分类号： G11C7/1066 , G11C7/1012 , G11C7/1039 , G11C7/1051 , G11C7/1072
摘要： A data output circuit includes a plurality of registers and a plurality of register output selection switches that are respectively connected to the plurality of registers. Pairs of the plurality of register output selection switches are connected by respective common active regions. A first data group selection switch is connected to the common active regions of a first set of the plurality of register output selection switches. A second data group selection switch is connected to the common active regions of a second subset of the plurality of register output selection switches. An output driver is connected to the first and second data group selection switches.
摘要翻译：数据输出电路包括分别连接到多个寄存器的多个寄存器和多个寄存器输出选择开关。多个寄存器输出选择开关的对通过相应的公共有效区域连接。第一数据组选择开关连接到多个寄存器输出选择开关的第一组的公共有效区。第二数据组选择开关连接到多个寄存器输出选择开关的第二子集的公共有效区域。输出驱动器连接到第一和第二数据组选择开关。

5. 发明授权

US5889724A Word line driving circuit for semiconductor memory device and method 失效
标题翻译：半导体存储器件的字线驱动电路及方法
公开(公告)号：US5889724A
公开(公告)日：1999-03-30
申请号：US992572
申请日：1997-12-17
申请人： Chang-Man Khang , Chang-Jin Lee
发明人： Chang-Man Khang , Chang-Jin Lee
IPC分类号： G11C11/413 , G11C8/10 , G11C11/407 , G11C8/00 , G11C7/00
CPC分类号： G11C8/10
摘要： A word line driving circuit for a semiconductor memory is provided that drives a corresponding word line of a first number of word lines coupled to a plurality of memory cells based on a memory address signal generated from a more significant controller. The memory cells have a matrix form of rows and columns and the first number of word lines are divided into a second number of word line groups. The word line driving circuit includes a second number of word line group driving circuits each respectively coupled to one of the second number of word line groups to drive one of the word lines in the word line group selected by a control signal. A word line selecting circuit determines which of the second word line groups contain the corresponding word line to be driven using the memory address signal and generates the control signal for the corresponding word line group driving circuit.
摘要翻译：提供一种用于半导体存储器的字线驱动电路，其基于从更重要的控制器产生的存储器地址信号驱动耦合到多个存储器单元的第一数量字线的对应字线。存储单元具有行和列的矩阵形式，并且第一数量的字线被划分为第二数量的字线组。字线驱动电路包括第二数量的字线组驱动电路，每个字线组驱动电路分别耦合到第二数量的字线组中的一个，以驱动由控制信号选择的字线组中的一个字线。字线选择电路使用存储器地址信号确定哪个第二字线组包含要驱动的对应字线，并且产生对应的字线组驱动电路的控制信号。

6. 发明授权

US07002852B2 Data output circuits for synchronous integrated circuit memory devices 失效
标题翻译：同步集成电路存储器件的数据输出电路
公开(公告)号：US07002852B2
公开(公告)日：2006-02-21
申请号：US10632439
申请日：2003-07-31
申请人： Chang-Man Khang , Joung-Yeal Kim
发明人： Chang-Man Khang , Joung-Yeal Kim
IPC分类号： G11C16/04
CPC分类号： G11C7/1066 , G11C7/1012 , G11C7/1039 , G11C7/1051 , G11C7/1072
摘要： A data output circuit includes a plurality of registers and a plurality of register output selection switches that are respectively connected to the plurality of registers. Pairs of the plurality of register output selection switches are connected by respective common active regions. A first data group selection switch is connected to the common active regions of a first set of the plurality of register output selection switches. A second data group selection switch is connected to the common active regions of a second subset of the plurality of register output selection switches. An output driver is connected to the first and second data group selection switches.
摘要翻译：数据输出电路包括分别连接到多个寄存器的多个寄存器和多个寄存器输出选择开关。多个寄存器输出选择开关的对通过相应的公共有效区域连接。第一数据组选择开关连接到多个寄存器输出选择开关的第一组的公共有效区。第二数据组选择开关连接到多个寄存器输出选择开关的第二子集的公共有效区域。输出驱动器连接到第一和第二数据组选择开关。

7. 发明授权

US06856164B2 Semiconductor integrated circuit having on-chip termination 有权
标题翻译：具有片上终端的半导体集成电路
公开(公告)号：US06856164B2
公开(公告)日：2005-02-15
申请号：US10426687
申请日：2003-05-01
申请人： Youn-Sik Park , Chang-Man Khang
发明人： Youn-Sik Park , Chang-Man Khang
IPC分类号： G11C5/02 , H04L25/02 , H03K19/003
CPC分类号： H04L25/028 , H04L25/0278 , H04L25/0292
摘要： A semiconductor integrated circuit includes at least one pad coupled to a bus line, a transmitter for transmitting a signal from an internal circuit to the outside through the pad, and a termination circuit for terminating the bus line. The transmitter and the termination circuit are disposed to surround the pad, reducing a size of the semiconductor integrated circuit.
摘要翻译：半导体集成电路包括耦合到总线的至少一个焊盘，用于通过焊盘将信号从内部电路发送到外部的发射器，以及用于终止总线的终端电路。发射机和终端电路被设置成围绕焊盘，减小了半导体集成电路的尺寸。

8. 发明授权

US5963494A Semiconductor memory having bitline precharge circuit 有权
标题翻译：具有位线预充电电路的半导体存储器
公开(公告)号：US5963494A
公开(公告)日：1999-10-05
申请号：US258788
申请日：1999-03-01
申请人： Chang-Man Khang
发明人： Chang-Man Khang
IPC分类号： G11C7/12 , G11C11/4094 , H01L21/8242 , H01L27/108 , G11C13/00
CPC分类号： H01L27/10885 , G11C11/4094 , G11C7/12 , H01L27/10897
摘要： A semiconductor device is provided having a symmetric bitline precharge circuit. Sizes of a parasitic devices near transistors lying symmetrically in the bitline precharge circuit are symmetrical to each other. Further, a layout area occupied by the bitline precharge circuit or a chip is reduced or minimized by the symmetric layout. The device can include a memory having first and second bitline extending in parallel a first direction a bitline precharge voltage supplying line and a bitline equalizing signal line extending in parallel in a second direction perpendicular to the first direction. A gate has at least a first part extending in the first direction, a second part having a first predetermined length extending in the second direction coupled to the first part and a third part having a second predetermined length extending in the second direction coupled to the first part with contact areas at uncoupled ends. An active region is on portions of the first and second bitline, the bitline precharge voltage supplying line, the first part and the second part of the gate. A first contact located between the first and second bitline to electrically couples the bitline precharge voltage supplying line and the active region. Second and third contacts electrically couple the gate to the bitline equalizing signal line, and fourth and firth contacts electrically couple the first and the second bitlines to the active region.
摘要翻译：提供具有对称位线预充电电路的半导体器件。在位线预充电电路对称的晶体管附近的寄生器件的尺寸彼此对称。此外，由位线预充电电路或芯片占用的布局面积通过对称布局减小或最小化。该装置可以包括具有第一和第二位线的第一和第二位线的存储器，第一和第二位线在第一方向上平行延伸，位线预充电电压供应线和位于垂直于第一方向的第二方向上并行延伸的位线均衡信号线。门具有至少第一部分，其在第一方向上延伸，第二部分具有在耦合到第一部分的第二方向上延伸的第一预定长度，以及具有第二预定长度的第三部分，该第二预定长度在第二方向上延伸，部分与非耦合端的接触区域。有源区域位于第一和第二位线，位线预充电电压供给线，栅极的第一部分和第二部分的一部分上。位于第一和第二位线之间的第一触点，用于电耦合位线预充电电压线和有源区。第二和第三触点将栅极电耦合到位线均衡信号线，第四和第三触点将第一和第二位线电耦合到有源区。

9. 发明授权

US06765833B2 Integrated circuit devices including equalization/precharge circuits for improving signal transmission 失效
标题翻译：集成电路装置包括用于改善信号传输的均衡/预充电电路
公开(公告)号：US06765833B2
公开(公告)日：2004-07-20
申请号：US10617402
申请日：2003-07-10
申请人： Chang-man Khang
发明人： Chang-man Khang
IPC分类号： G11C700
CPC分类号： G11C7/1048 , G11C7/1006
摘要： An integrated circuit device includes first and second complementary data line pairs, e.g., global or local I/O data line pairs, disposed on a substrate and extending along a first direction, the first and second complementary data line pairs arranged such that first and second data lines of the first complementary data line pair have a first data line of the second complementary data line pair disposed therebetween. An equalization transistor includes respective first and second source/drain regions in the substrate that are coupled to respective ones of the first and second data lines of the first complementary data line pair and an equalization transistor gate electrode disposed on the substrate between the first and second data lines of the first complementary data line pair. A first precharge transistor includes the first source/drain region, a third source/drain region in the substrate displaced from the first source/drain region along the first direction, and a first precharge transistor gate electrode disposed on the substrate between the first and third source/drain regions. A second precharge transistor includes the second source/drain region, a fourth source/drain region in the substrate displaced from the second source/drain region along the first direction, and a second precharge transistor gate electrode disposed on the substrate between the second and fourth source/drain regions. A precharge voltage bus conductor is disposed on the substrate and is electrically coupled to the third and fourth source/drain regions.
摘要翻译：集成电路器件包括设置在衬底上并沿着第一方向延伸的第一和第二互补数据线对，例如全局或本地I / O数据线对，第一和第二互补数据线对布置成使得第一和第二互补数据线对第一互补数据线对的数据线具有设置在其间的第二互补数据线对的第一数据线。均衡晶体管包括：衬底中相应的第一和第二源/漏区，其耦合到第一互补数据线对的第一和第二数据线中的相应的第一和第二数据线，以及设置在第一和第二互补数据线对之间的衬底上的均衡晶体管栅电极第一互补数据线对的数据线。第一预充电晶体管包括第一源极/漏极区域，沿着第一方向从第一源极/漏极区域偏移的衬底中的第三源极/漏极区域和设置在第一和第三区域之间的衬底上的第一预充电晶体管栅电极源/漏区。第二预充电晶体管包括第二源极/漏极区域，沿着第一方向从第二源极/漏极区域移位的衬底中的第四源极/漏极区域和设置在第二和第四区域之间的衬底上的第二预充电晶体管栅极电极源/漏区。预充电电压总线导体设置在衬底上并且电耦合到第三和第四源极/漏极区域。

10. 发明授权

US06667895B2 Integrated circuit device and module with integrated circuits 失效
公开(公告)号：US06667895B2
公开(公告)日：2003-12-23
申请号：US10192901
申请日：2002-07-10
申请人： Seong-Jin Jang , Young-Hyun Jun , Chang-Man Khang
发明人： Seong-Jin Jang , Young-Hyun Jun , Chang-Man Khang
IPC分类号： G11C506
CPC分类号： G11C5/063 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit comprises a substrate having circuitry integrated with the substrate. Switching circuitry is selectably operable to configure signal paths to alternative mirrored pads over the substrate. At least one of the first and second signal paths may comprise a buffer in series between the switching circuit and its respective pad.

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