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1. 发明申请

US20130157452A1 SEMICONDUCTOR DEVICE INCLUDING POLYSILICON RESISTOR AND METAL GATE RESISTOR AND METHODS OF FABRICATING THEREOF 有权
标题翻译：包括多晶硅电阻和金属栅极电阻的半导体器件及其制造方法
公开(公告)号：US20130157452A1
公开(公告)日：2013-06-20
申请号：US13328875
申请日：2011-12-16
申请人： Jian-Hao Chen , Chia-Yu Lu , Tung-Heng Hsieh , Kuo-Feng Yu , Chin-Shan Hou , Hsien-Chin Lin , Shyue-Shyh Lin
发明人： Jian-Hao Chen , Chia-Yu Lu , Tung-Heng Hsieh , Kuo-Feng Yu , Chin-Shan Hou , Hsien-Chin Lin , Shyue-Shyh Lin
IPC分类号： H01L21/28
CPC分类号： H01L21/28123 , H01L27/0629 , H01L28/20 , H01L29/42376 , H01L29/66545 , H01L29/78
摘要： A described method includes providing a semiconductor substrate. A first gate structure is formed on the semiconductor substrate and a sacrificial gate structure formed adjacent the first gate structure. The sacrificial gate structure may be used to form a metal gate structure using a replacement gate methodology. A dielectric layer is formed overlying the first gate structure and the sacrificial gate structure. The dielectric layer has a first thickness above a top surface of the first gate structure and a second thickness, less than the first thickness, above a top surface of the sacrificial gate structure. (See, e.g., FIGS. 5, 15, 26). Thus, a subsequent planarization process of the dielectric layer may not contact the first gate structure.
摘要翻译：所述方法包括提供半导体衬底。第一栅极结构形成在半导体衬底上，并且邻近第一栅极结构形成牺牲栅极结构。牺牲栅极结构可以用于使用替代栅极方法形成金属栅极结构。覆盖第一栅极结构和牺牲栅极结构的介电层形成。电介质层在第一栅极结构的顶表面上方具有第一厚度，并且在牺牲栅极结构的顶表面上方具有小于第一厚度的第二厚度。（参见例如图5,15,26）。因此，电介质层的随后的平坦化处理可以不接触第一栅极结构。

2. 发明申请

US20120264281A1 METHOD OF FABRICATING A PLURALITY OF GATE STRUCTURES 有权
标题翻译：制造大量门结构的方法
公开(公告)号：US20120264281A1
公开(公告)日：2012-10-18
申请号：US13085029
申请日：2011-04-12
申请人： Jian-Hao CHEN , Wei-Yang LEE , Wei-Yeh TANG , Xiong-Fei YU , Kuang-Yuan HSU
发明人： Jian-Hao CHEN , Wei-Yang LEE , Wei-Yeh TANG , Xiong-Fei YU , Kuang-Yuan HSU
IPC分类号： H01L21/28
CPC分类号： H01L29/6659 , H01L21/02181 , H01L21/02186 , H01L21/02189 , H01L21/0228 , H01L21/32139 , H01L21/823437 , H01L21/823828 , H01L29/66545 , H01L29/7833
摘要： The invention relates to integrated circuit fabrication, and more particularly to a semiconductor device with a plurality of gate structures. An exemplary method of fabricating the plurality of gate structures comprises providing a silicon substrate; depositing a dummy oxide layer over the substrate; depositing a dummy gate electrode layer over the dummy oxide layer; patterning the layers to define a plurality of dummy gates; forming nitrogen-containing sidewall spacers on the plurality of dummy gates; forming an interlayer dielectric layer between the nitrogen-containing sidewall spacers; selectively depositing a hard mask layer on the interlayer dielectric layer by an atomic layer deposition (ALD) process; removing the dummy gate electrode layer; removing the dummy oxide layer; depositing a gate dielectric; and depositing a gate electrode.
摘要翻译：本发明涉及集成电路制造，更具体地涉及具有多个栅极结构的半导体器件。制造多个栅极结构的示例性方法包括提供硅衬底; 在衬底上沉积虚拟氧化物层; 在虚拟氧化物层上沉积虚拟栅电极层; 图案化层以限定多个虚拟门; 在所述多个虚拟栅极上形成含氮侧壁间隔物; 在所述含氮侧壁间隔件之间形成层间电介质层; 通过原子层沉积（ALD）工艺在层间介质层上选择性地沉积硬掩模层; 去除所述伪栅电极层; 去除虚拟氧化物层; 沉积栅极电介质; 并沉积栅电极。

3. 发明申请

US20110193180A1 METHOD AND APPARATUS OF FORMING A GATE 有权
标题翻译：形成门的方法和装置
公开(公告)号：US20110193180A1
公开(公告)日：2011-08-11
申请号：US12700901
申请日：2010-02-05
申请人： Jian-Hao Chen , Da-Yuan Lee , Kuang-Yuan Hsu
发明人： Jian-Hao Chen , Da-Yuan Lee , Kuang-Yuan Hsu
IPC分类号： H01L29/51 , H01L21/283
CPC分类号： H01L21/28194 , H01L21/02148 , H01L21/02181 , H01L21/022 , H01L21/0228 , H01L29/495 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/665
摘要： The present disclosure provides an apparatus that includes a semiconductor device. The semiconductor device includes a substrate. The semiconductor device also includes a first gate dielectric layer that is disposed over the substrate. The first gate dielectric layer includes a first material. The first gate dielectric layer has a first thickness that is less than a threshold thickness at which a portion of the first material of the first gate dielectric layer begins to crystallize. The semiconductor device also includes a second gate dielectric layer that is disposed over the first gate dielectric layer. The second gate dielectric layer includes a second material that is different from the first material. The second gate dielectric layer has a second thickness that is less than a threshold thickness at which a portion of the second material of the second gate dielectric layer begins to crystallize.
摘要翻译：本公开提供了一种包括半导体器件的装置。半导体器件包括衬底。半导体器件还包括设置在衬底上的第一栅极电介质层。第一栅介质层包括第一材料。第一栅极介电层具有小于第一栅极电介质层的第一材料的一部分开始结晶的阈值厚度的第一厚度。半导体器件还包括设置在第一栅极介电层上的第二栅极电介质层。第二栅极介电层包括与第一材料不同的第二材料。第二栅极电介质层具有小于第二栅极电介质层的第二材料的一部分开始结晶的阈值厚度的第二厚度。

4. 发明授权

US09070624B2 Semiconductor device including polysilicon resistor and metal gate resistor and methods of fabricating thereof 有权
标题翻译：包括多晶硅电阻器和金属栅极电阻器的半导体器件及其制造方法
公开(公告)号：US09070624B2
公开(公告)日：2015-06-30
申请号：US13328875
申请日：2011-12-16
申请人： Jian-Hao Chen , Chia-Yu Lu , Tung-Heng Hsieh , Kuo-Feng Yu , Chin-Shan Hou , Hsien-Chin Lin , Shyue-Shyh Lin
发明人： Jian-Hao Chen , Chia-Yu Lu , Tung-Heng Hsieh , Kuo-Feng Yu , Chin-Shan Hou , Hsien-Chin Lin , Shyue-Shyh Lin
IPC分类号： H01L21/28 , H01L49/02 , H01L27/06 , H01L29/78 , H01L29/66 , H01L29/423
CPC分类号： H01L21/28123 , H01L27/0629 , H01L28/20 , H01L29/42376 , H01L29/66545 , H01L29/78
摘要： A described method includes providing a semiconductor substrate. A first gate structure is formed on the semiconductor substrate and a sacrificial gate structure formed adjacent the first gate structure. The sacrificial gate structure may be used to form a metal gate structure using a replacement gate methodology. A dielectric layer is formed overlying the first gate structure and the sacrificial gate structure. The dielectric layer has a first thickness above a top surface of the first gate structure and a second thickness, less than the first thickness, above a top surface of the sacrificial gate structure. (See, e.g., FIGS. 5, 15, 26). Thus, a subsequent planarization process of the dielectric layer may not contact the first gate structure.
摘要翻译：所述方法包括提供半导体衬底。第一栅极结构形成在半导体衬底上，并且邻近第一栅极结构形成牺牲栅极结构。牺牲栅极结构可以用于使用替代栅极方法形成金属栅极结构。覆盖第一栅极结构和牺牲栅极结构的介电层形成。电介质层在第一栅极结构的顶表面上方具有第一厚度，并且在牺牲栅极结构的顶表面上方具有小于第一厚度的第二厚度。（参见例如图5,15,26）。因此，电介质层的随后的平坦化处理可能不接触第一栅极结构。

5. 发明申请

US20110256731A1 METHOD FOR FABRICATING A GATE DIELECTRIC LAYER 有权
标题翻译：用于制造栅极介电层的方法
公开(公告)号：US20110256731A1
公开(公告)日：2011-10-20
申请号：US12760297
申请日：2010-04-14
申请人： Wei-Yang LEE , Xiong-Fei YU , Jian-Hao CHEN , Cheng-Hao HOU , Da-Yuan LEE , Kuang-Yuan HSU
发明人： Wei-Yang LEE , Xiong-Fei YU , Jian-Hao CHEN , Cheng-Hao HOU , Da-Yuan LEE , Kuang-Yuan HSU
IPC分类号： H01L21/3105 , H01L21/316
CPC分类号： H01L29/517 , H01L21/02181 , H01L21/0228 , H01L21/02323 , H01L21/02337 , H01L21/0234 , H01L21/28194 , H01L29/495 , H01L29/4966 , H01L29/513 , H01L29/66545 , H01L29/6659
摘要： A method for fabricating the gate dielectric layer comprises forming a high-k dielectric layer over a substrate; forming an oxygen-containing layer on the high-k dielectric layer by an atomic layer deposition process; and performing an inert plasma treatment on the oxygen-containing layer.
摘要翻译：一种用于制造栅极电介质层的方法包括在衬底上形成高k电介质层; 通过原子层沉积工艺在高k电介质层上形成含氧层; 对含氧层进行惰性等离子体处理。

6. 发明授权

US08859386B2 Semiconductor devices, methods of manufacture thereof, and methods of forming resistors 有权
标题翻译：半导体器件，其制造方法以及形成电阻器的方法
公开(公告)号：US08859386B2
公开(公告)日：2014-10-14
申请号：US13492571
申请日：2012-06-08
申请人： Chia-Yu Lu , Jian-Hao Chen , Chih-Hung Wang , Tung-Heng Hsieh , Kuo-Feng Yu , Chin-Shan Hou , Shyue-Shyh Lin
发明人： Chia-Yu Lu , Jian-Hao Chen , Chih-Hung Wang , Tung-Heng Hsieh , Kuo-Feng Yu , Chin-Shan Hou , Shyue-Shyh Lin
IPC分类号： H01L27/06 , H01L21/70 , H01L49/02
CPC分类号： H01L27/0629 , H01L21/76811 , H01L23/485 , H01L23/5228 , H01L27/0688 , H01L28/20 , H01L28/24 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor devices, methods of manufacture thereof, and methods of forming resistors are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming a first insulating material over a workpiece, and forming a conductive chemical compound material over the first insulating material. The conductive chemical compound material is patterned to form a resistor. A second insulating material is formed over the resistor, and the second insulating material is patterned. The patterned second insulating material is filled with a conductive material to form a first contact coupled to a first end of the resistor and to form a second contact coupled to a second end of the resistor.
摘要翻译：公开了半导体器件，其制造方法和形成电阻器的方法。在一个实施例中，制造半导体器件的方法包括在工件上形成第一绝缘材料，并在第一绝缘材料上形成导电化合物材料。将导电化合物材料图案化以形成电阻器。第二绝缘材料形成在电阻器上，第二绝缘材料被图案化。图案化的第二绝缘材料填充有导电材料以形成耦合到电阻器的第一端的第一触点，并形成耦合到电阻器的第二端的第二触点。

7. 发明授权

US08334198B2 Method of fabricating a plurality of gate structures 有权
标题翻译：制造多个门结构的方法
公开(公告)号：US08334198B2
公开(公告)日：2012-12-18
申请号：US13085029
申请日：2011-04-12
申请人： Jian-Hao Chen , Wei-Yang Lee , Wei-Yeh Tang , Xiong-Fei Yu , Kuang-Yuan Hsu
发明人： Jian-Hao Chen , Wei-Yang Lee , Wei-Yeh Tang , Xiong-Fei Yu , Kuang-Yuan Hsu
IPC分类号： H01L21/4763
CPC分类号： H01L29/6659 , H01L21/02181 , H01L21/02186 , H01L21/02189 , H01L21/0228 , H01L21/32139 , H01L21/823437 , H01L21/823828 , H01L29/66545 , H01L29/7833
摘要： The invention relates to integrated circuit fabrication, and more particularly to a semiconductor device with a plurality of gate structures. An exemplary method of fabricating the plurality of gate structures comprises providing a silicon substrate; depositing a dummy oxide layer over the substrate; depositing a dummy gate electrode layer over the dummy oxide layer; patterning the layers to define a plurality of dummy gates; forming nitrogen-containing sidewall spacers on the plurality of dummy gates; forming an interlayer dielectric layer between the nitrogen-containing sidewall spacers; selectively depositing a hard mask layer on the interlayer dielectric layer by an atomic layer deposition (ALD) process; removing the dummy gate electrode layer; removing the dummy oxide layer; depositing a gate dielectric; and depositing a gate electrode.
摘要翻译：本发明涉及集成电路制造，更具体地涉及具有多个栅极结构的半导体器件。制造多个栅极结构的示例性方法包括提供硅衬底; 在衬底上沉积虚拟氧化物层; 在虚拟氧化物层上沉积虚拟栅电极层; 图案化层以限定多个虚拟门; 在所述多个虚拟栅极上形成含氮侧壁间隔物; 在所述含氮侧壁间隔件之间形成层间电介质层; 通过原子层沉积（ALD）工艺在层间介质层上选择性地沉积硬掩模层; 去除虚拟栅极电极层; 去除虚拟氧化物层; 沉积栅极电介质; 并沉积栅电极。

8. 发明申请

US20100124818A1 FABRICATING HIGH-K/METAL GATE DEVICES IN A GATE LAST PROCESS 有权
标题翻译：在门过程中制造高K /金属门装置
公开(公告)号：US20100124818A1
公开(公告)日：2010-05-20
申请号：US12567227
申请日：2009-09-25
申请人： Da-Yuan Lee , Jian-Hao Chen , Chi-Chun Chen , Matt Yeh , Hsing-Jui Lee
发明人： Da-Yuan Lee , Jian-Hao Chen , Chi-Chun Chen , Matt Yeh , Hsing-Jui Lee
IPC分类号： H01L21/8234
CPC分类号： H01L21/823814 , H01L21/823807 , H01L21/823842 , H01L21/823857 , H01L29/7848
摘要： The present disclosure provides a method that includes forming first and second gate structures over first and second regions, respectively, removing a first dummy gate and first dummy dielectric from the first gate structure thereby forming a first trench and removing a second dummy gate and second dummy dielectric from the second gate structure thereby forming a second trench, forming a gate layer to partially fill the first and second trenches, forming a material layer to fill the remainder of the first and second trenches, removing a portion of the material layer such that a remaining portion of the material layer protects a first portion of the gate layer located at a bottom portion of the first and second trenches, removing a second portion of the gate layer, removing the remaining portion of the material layer from the first and second trenches.
摘要翻译：本公开提供了一种方法，其包括分别在第一和第二区域上形成第一和第二栅极结构，从第一栅极结构去除第一伪栅极和第一虚设电介质，从而形成第一沟槽并且去除第二虚拟栅极和第二虚拟栅极从第二栅极结构的电介质，从而形成第二沟槽，形成栅极层以部分地填充第一和第二沟槽，形成材料层以填充第一和第二沟槽的其余部分，去除材料层的一部分，使得材料层的剩余部分保护位于第一和第二沟槽的底部的栅极层的第一部分，去除栅极层的第二部分，从第一和第二沟槽去除材料层的剩余部分。

9. 发明申请

US20130328131A1 Semiconductor Devices, Methods of Manufacture Thereof, and Methods of Forming Resistors 有权
公开(公告)号：US20130328131A1
公开(公告)日：2013-12-12
申请号：US13492571
申请日：2012-06-08
申请人： Chia-Yu Lu , Jian-Hao Chen , Chih-Hung Wang , Tung-Heng Hsieh , Kuo-Feng Yu , Chin-Shan Hou , Shyue-Shyh Lin
发明人： Chia-Yu Lu , Jian-Hao Chen , Chih-Hung Wang , Tung-Heng Hsieh , Kuo-Feng Yu , Chin-Shan Hou , Shyue-Shyh Lin
IPC分类号： H01L27/06 , H01L21/02
CPC分类号： H01L27/0629 , H01L21/76811 , H01L23/485 , H01L23/5228 , H01L27/0688 , H01L28/20 , H01L28/24 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor devices, methods of manufacture thereof, and methods of forming resistors are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming a first insulating material over a workpiece, and forming a conductive chemical compound material over the first insulating material. The conductive chemical compound material is patterned to form a resistor. A second insulating material is formed over the resistor, and the second insulating material is patterned. The patterned second insulating material is filled with a conductive material to form a first contact coupled to a first end of the resistor and to form a second contact coupled to a second end of the resistor.

10. 发明申请

US20130026637A1 METAL GATE ELECTRODE OF A FIELD EFFECT TRANSISTOR 有权
标题翻译：场效应晶体管的金属栅极电极
公开(公告)号：US20130026637A1
公开(公告)日：2013-01-31
申请号：US13189732
申请日：2011-07-25
申请人： Cheng-Hao HOU , Peng-Soon LIM , Da-Yuan LEE , Xiong-Fei YU , Chun-Yuan CHOU , Fan-Yi HSU , Jian-Hao CHEN , Kuang-Yuan HSU
发明人： Cheng-Hao HOU , Peng-Soon LIM , Da-Yuan LEE , Xiong-Fei YU , Chun-Yuan CHOU , Fan-Yi HSU , Jian-Hao CHEN , Kuang-Yuan HSU
IPC分类号： H01L23/48 , H01L21/28
CPC分类号： H01L21/28026 , H01L21/28088 , H01L29/401 , H01L29/4966 , H01L29/51 , H01L29/66477 , H01L29/66545 , H01L29/78 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit fabrication is disclosed, and more particularly a field effect transistor with a low resistance metal gate electrode is disclosed. An exemplary structure for a metal gate electrode of a field effect transistor comprises a lower portion formed of a first metal material, wherein the lower portion has a recess, a bottom portion and sidewall portions, wherein each of the sidewall portions has a first width; and an upper portion formed of a second metal material, wherein the upper portion has a protrusion and a bulk portion, wherein the bulk portion has a second width, wherein the protrusion extends into the recess, wherein a ratio of the second width to the first width is from about 5 to 10.
摘要翻译：公开了集成电路制造，更具体地说，公开了具有低电阻金属栅电极的场效应晶体管。场效应晶体管的金属栅电极的示例性结构包括由第一金属材料形成的下部，其中下部具有凹部，底部和侧壁部分，其中每个侧壁部分具有第一宽度; 以及由第二金属材料形成的上部，其中所述上部具有突起和主体部分，其中所述主体部分具有第二宽度，其中所述突起延伸到所述凹部中，其中所述第二宽度与所述第一宽度的比率宽度为约5至10。

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