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1. 发明授权

US08859386B2 Semiconductor devices, methods of manufacture thereof, and methods of forming resistors 有权
标题翻译：半导体器件，其制造方法以及形成电阻器的方法
公开(公告)号：US08859386B2
公开(公告)日：2014-10-14
申请号：US13492571
申请日：2012-06-08
申请人： Chia-Yu Lu , Jian-Hao Chen , Chih-Hung Wang , Tung-Heng Hsieh , Kuo-Feng Yu , Chin-Shan Hou , Shyue-Shyh Lin
发明人： Chia-Yu Lu , Jian-Hao Chen , Chih-Hung Wang , Tung-Heng Hsieh , Kuo-Feng Yu , Chin-Shan Hou , Shyue-Shyh Lin
IPC分类号： H01L27/06 , H01L21/70 , H01L49/02
CPC分类号： H01L27/0629 , H01L21/76811 , H01L23/485 , H01L23/5228 , H01L27/0688 , H01L28/20 , H01L28/24 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor devices, methods of manufacture thereof, and methods of forming resistors are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming a first insulating material over a workpiece, and forming a conductive chemical compound material over the first insulating material. The conductive chemical compound material is patterned to form a resistor. A second insulating material is formed over the resistor, and the second insulating material is patterned. The patterned second insulating material is filled with a conductive material to form a first contact coupled to a first end of the resistor and to form a second contact coupled to a second end of the resistor.
摘要翻译：公开了半导体器件，其制造方法和形成电阻器的方法。在一个实施例中，制造半导体器件的方法包括在工件上形成第一绝缘材料，并在第一绝缘材料上形成导电化合物材料。将导电化合物材料图案化以形成电阻器。第二绝缘材料形成在电阻器上，第二绝缘材料被图案化。图案化的第二绝缘材料填充有导电材料以形成耦合到电阻器的第一端的第一触点，并形成耦合到电阻器的第二端的第二触点。

2. 发明申请

US20130328131A1 Semiconductor Devices, Methods of Manufacture Thereof, and Methods of Forming Resistors 有权
公开(公告)号：US20130328131A1
公开(公告)日：2013-12-12
申请号：US13492571
申请日：2012-06-08
申请人： Chia-Yu Lu , Jian-Hao Chen , Chih-Hung Wang , Tung-Heng Hsieh , Kuo-Feng Yu , Chin-Shan Hou , Shyue-Shyh Lin
发明人： Chia-Yu Lu , Jian-Hao Chen , Chih-Hung Wang , Tung-Heng Hsieh , Kuo-Feng Yu , Chin-Shan Hou , Shyue-Shyh Lin
IPC分类号： H01L27/06 , H01L21/02
CPC分类号： H01L27/0629 , H01L21/76811 , H01L23/485 , H01L23/5228 , H01L27/0688 , H01L28/20 , H01L28/24 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor devices, methods of manufacture thereof, and methods of forming resistors are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming a first insulating material over a workpiece, and forming a conductive chemical compound material over the first insulating material. The conductive chemical compound material is patterned to form a resistor. A second insulating material is formed over the resistor, and the second insulating material is patterned. The patterned second insulating material is filled with a conductive material to form a first contact coupled to a first end of the resistor and to form a second contact coupled to a second end of the resistor.

3. 发明授权

US09070624B2 Semiconductor device including polysilicon resistor and metal gate resistor and methods of fabricating thereof 有权
标题翻译：包括多晶硅电阻器和金属栅极电阻器的半导体器件及其制造方法
公开(公告)号：US09070624B2
公开(公告)日：2015-06-30
申请号：US13328875
申请日：2011-12-16
申请人： Jian-Hao Chen , Chia-Yu Lu , Tung-Heng Hsieh , Kuo-Feng Yu , Chin-Shan Hou , Hsien-Chin Lin , Shyue-Shyh Lin
发明人： Jian-Hao Chen , Chia-Yu Lu , Tung-Heng Hsieh , Kuo-Feng Yu , Chin-Shan Hou , Hsien-Chin Lin , Shyue-Shyh Lin
IPC分类号： H01L21/28 , H01L49/02 , H01L27/06 , H01L29/78 , H01L29/66 , H01L29/423
CPC分类号： H01L21/28123 , H01L27/0629 , H01L28/20 , H01L29/42376 , H01L29/66545 , H01L29/78
摘要： A described method includes providing a semiconductor substrate. A first gate structure is formed on the semiconductor substrate and a sacrificial gate structure formed adjacent the first gate structure. The sacrificial gate structure may be used to form a metal gate structure using a replacement gate methodology. A dielectric layer is formed overlying the first gate structure and the sacrificial gate structure. The dielectric layer has a first thickness above a top surface of the first gate structure and a second thickness, less than the first thickness, above a top surface of the sacrificial gate structure. (See, e.g., FIGS. 5, 15, 26). Thus, a subsequent planarization process of the dielectric layer may not contact the first gate structure.
摘要翻译：所述方法包括提供半导体衬底。第一栅极结构形成在半导体衬底上，并且邻近第一栅极结构形成牺牲栅极结构。牺牲栅极结构可以用于使用替代栅极方法形成金属栅极结构。覆盖第一栅极结构和牺牲栅极结构的介电层形成。电介质层在第一栅极结构的顶表面上方具有第一厚度，并且在牺牲栅极结构的顶表面上方具有小于第一厚度的第二厚度。（参见例如图5,15,26）。因此，电介质层的随后的平坦化处理可能不接触第一栅极结构。

4. 发明申请

US20130157452A1 SEMICONDUCTOR DEVICE INCLUDING POLYSILICON RESISTOR AND METAL GATE RESISTOR AND METHODS OF FABRICATING THEREOF 有权
标题翻译：包括多晶硅电阻和金属栅极电阻的半导体器件及其制造方法
公开(公告)号：US20130157452A1
公开(公告)日：2013-06-20
申请号：US13328875
申请日：2011-12-16
申请人： Jian-Hao Chen , Chia-Yu Lu , Tung-Heng Hsieh , Kuo-Feng Yu , Chin-Shan Hou , Hsien-Chin Lin , Shyue-Shyh Lin
发明人： Jian-Hao Chen , Chia-Yu Lu , Tung-Heng Hsieh , Kuo-Feng Yu , Chin-Shan Hou , Hsien-Chin Lin , Shyue-Shyh Lin
IPC分类号： H01L21/28
CPC分类号： H01L21/28123 , H01L27/0629 , H01L28/20 , H01L29/42376 , H01L29/66545 , H01L29/78
摘要： A described method includes providing a semiconductor substrate. A first gate structure is formed on the semiconductor substrate and a sacrificial gate structure formed adjacent the first gate structure. The sacrificial gate structure may be used to form a metal gate structure using a replacement gate methodology. A dielectric layer is formed overlying the first gate structure and the sacrificial gate structure. The dielectric layer has a first thickness above a top surface of the first gate structure and a second thickness, less than the first thickness, above a top surface of the sacrificial gate structure. (See, e.g., FIGS. 5, 15, 26). Thus, a subsequent planarization process of the dielectric layer may not contact the first gate structure.
摘要翻译：所述方法包括提供半导体衬底。第一栅极结构形成在半导体衬底上，并且邻近第一栅极结构形成牺牲栅极结构。牺牲栅极结构可以用于使用替代栅极方法形成金属栅极结构。覆盖第一栅极结构和牺牲栅极结构的介电层形成。电介质层在第一栅极结构的顶表面上方具有第一厚度，并且在牺牲栅极结构的顶表面上方具有小于第一厚度的第二厚度。（参见例如图5,15,26）。因此，电介质层的随后的平坦化处理可以不接触第一栅极结构。

5. 发明授权

US07897501B2 Method of fabricating a field-effect transistor having robust sidewall spacers 有权
标题翻译：制造具有坚固侧壁间隔物的场效应晶体管的方法
公开(公告)号：US07897501B2
公开(公告)日：2011-03-01
申请号：US12013528
申请日：2008-01-14
申请人： Chien-Li Cheng , Sun-Jay Chang , Tung-Heng Hsieh , Yung-Shen Chen
发明人： Chien-Li Cheng , Sun-Jay Chang , Tung-Heng Hsieh , Yung-Shen Chen
IPC分类号： H01L21/4763
CPC分类号： H01L29/6656 , H01L29/665 , H01L29/6653
摘要： A method of fabricating a semiconductor device is disclosed. The method of fabricating a semiconductor device provides a semiconductor substrate; forming a gate stack overlying the semiconductor substrate; forming spacers each having a first inner spacer and a second outer spacer on sidewalls of the gate stack; forming a protective layer on sidewalls of the spacers, covering a part of the semiconductor substrate, wherein an etching selectivity of the protective layer is higher than that of the first inner spacer.
摘要翻译：公开了制造半导体器件的方法。制造半导体器件的方法提供半导体衬底; 形成覆盖在半导体衬底上的栅叠层; 每个在所述栅极叠层的侧壁上具有第一内隔离物和第二外隔离物的隔离物; 在所述间隔物的侧壁上形成保护层，覆盖所述半导体衬底的一部分，其中所述保护层的蚀刻选择性高于所述第一内衬垫的蚀刻选择性。

6. 发明授权

US09269833B2 Methods and apparatus for hybrid MOS capacitors in replacement gate process 有权
标题翻译：替代栅极工艺中混合MOS电容器的方法和装置
公开(公告)号：US09269833B2
公开(公告)日：2016-02-23
申请号：US13303096
申请日：2011-11-22
申请人： Pai-Chieh Wang , Tung-Heng Hsieh , Yimin Huang
发明人： Pai-Chieh Wang , Tung-Heng Hsieh , Yimin Huang
IPC分类号： H01L29/94 , H01L27/06 , H01L27/08 , H01L49/02
CPC分类号： H01L29/94 , H01L27/0629 , H01L27/0811 , H01L28/20
摘要： Methods and apparatus for hybrid MOS capacitors in replacement gate process. A method is disclosed including patterning a gate dielectric layer and a polysilicon gate layer to form a polysilicon gate region over a substrate; forming an inter-level dielectric layer over the substrate and surrounding the polysilicon gate region; defining polysilicon resistor regions each containing at least one portion of the polysilicon gate region and not containing at least one other portion of the polysilicon gate region, forming dummy gate regions removing the dummy gate regions and the gate dielectric layer underneath the dummy gate regions to leave trenches; and forming high-k metal gate devices in the trenches. A capacitor region including a high-k metal gate and a polysilicon gate next to the high-k metal gate is disclosed. Additional hybrid capacitor apparatuses are disclosed.
摘要翻译：替代栅极工艺中混合MOS电容器的方法和装置。公开了一种方法，其包括图案化栅极电介质层和多晶硅栅极层以在衬底上形成多晶硅栅极区域; 在所述衬底上形成层间电介质层并围绕所述多晶硅栅极区域; 限定多晶硅电阻器区域，每个多晶硅电阻器区域包含多晶硅栅极区域的至少一部分并且不包含多晶硅栅极区域的至少一个其他部分，形成伪栅极区域，去除伪栅极区域和伪栅极区域下方的栅极介电层，以留下沟渠并在沟槽中形成高k金属栅极器件。公开了一种包括高k金属栅极和与高k金属栅极相邻的多晶硅栅极的电容器区域。公开了另外的混合电容器装置。

7. 发明授权

US07382028B2 Method for forming silicide and semiconductor device formed thereby 有权
标题翻译：由此形成硅化物和半导体器件的方法
公开(公告)号：US07382028B2
公开(公告)日：2008-06-03
申请号：US11107625
申请日：2005-04-15
申请人： Tung-Heng Hsieh , Chien-Li Cheng , Yi-Shien Mor , Yung-Shun Chen
发明人： Tung-Heng Hsieh , Chien-Li Cheng , Yi-Shien Mor , Yung-Shun Chen
IPC分类号： H01L29/423
CPC分类号： H01L21/28052 , H01L29/665 , H01L29/6659
摘要： A method for forming silicide and a semiconductor device formed thereby. A Si-containing polycrystalline region is converted to an amorphous region, and annealed to form a regrown polycrystalline region having an increased grain size. A silicide layer is formed by reacting a metal and the regrown polycrystalline region having the increased grain size.
摘要翻译：一种形成硅化物的方法和由此形成的半导体器件。将含Si的多晶区域转变为非晶区域，并退火以形成具有增加的晶粒尺寸的再生长多晶区域。通过金属和具有增加的晶粒尺寸的再结晶多晶区域的反应形成硅化物层。

8. 发明申请

US20070224808A1 Silicided gates for CMOS devices 审中-公开
标题翻译： CMOS器件硅化栅
公开(公告)号：US20070224808A1
公开(公告)日：2007-09-27
申请号：US11387614
申请日：2006-03-23
申请人： Tsung-Hsien Chang , Tung-Heng Hsieh , Chung-Cheng Wu , Shou Chang
发明人： Tsung-Hsien Chang , Tung-Heng Hsieh , Chung-Cheng Wu , Shou Chang
IPC分类号： H01L21/4763
CPC分类号： H01L29/665 , H01L21/31111 , H01L29/6653
摘要： A silicided gate for CMOS transistors and a method of manufacture is provided. A gate electrode is formed on a substrate. A first dielectric layer is formed over the gate electrode and the substrate, and a second dielectric layer is formed over the first dielectric layer. The second dielectric layer is etched to form spacers adjacent the gate electrode. A treatment is performed on the first dielectric layer over the gate electrode, wherein the treatment increases the effective etch rate of the first dielectric layer as compared to untreated portions of the first dielectric layer. An etching procedure is then performed to expose the surface of the gate electrode, the etching procedure recessing the liner along sidewalls of the gate electrode. Thereafter, a silicide procedure is performed to silicide at least a portion of the gate electrode.
摘要翻译：提供了用于CMOS晶体管的硅化物栅极和制造方法。在基板上形成栅电极。在栅电极和衬底之上形成第一电介质层，并且在第一介电层上形成第二电介质层。蚀刻第二电介质层以形成邻近栅极的间隔物。在栅电极上的第一电介质层上进行处理，其中与第一介电层的未处理部分相比，处理增加了第一介电层的有效蚀刻速率。然后执行蚀刻过程以暴露栅电极的表面，蚀刻过程使衬垫沿着栅电极的侧壁凹陷。此后，执行硅化物步骤以对栅电极的至少一部分进行硅化。

9. 发明授权

US09412883B2 Methods and apparatus for MOS capacitors in replacement gate process 有权
标题翻译：替代栅极工艺中MOS电容器的方法和装置
公开(公告)号：US09412883B2
公开(公告)日：2016-08-09
申请号：US13303083
申请日：2011-11-22
申请人： Pai-Chieh Wang , Tung-Heng Hsieh , Yimin Huang , Chung-Hui Chen
发明人： Pai-Chieh Wang , Tung-Heng Hsieh , Yimin Huang , Chung-Hui Chen
IPC分类号： H01L29/94 , H01L27/06 , H01L27/08 , H01L49/02
CPC分类号： H01L21/822 , H01L27/0629 , H01L27/0811 , H01L28/20 , H01L29/401 , H01L29/94
摘要： Methods and apparatus for polysilicon MOS capacitors in a replacement gate process. A method includes disposing a gate dielectric layer over a semiconductor substrate; disposing a polysilicon gate layer over the dielectric layer; patterning the gate dielectric layer and the polysilicon gate layer to form a plurality of polysilicon gates spaced by at least a minimum polysilicon to polysilicon pitch; defining a polysilicon resistor region containing at least one of the polysilicon gates and not containing at least one other of the polysilicon gates, which form dummy gates; depositing a mask layer over an inter-level dielectric layer; patterning the mask layer to expose the dummy gates; removing the dummy gates and the gate dielectric layer underneath the dummy gates to leave trenches in the inter-level dielectric layer; and forming high-k metal gate devices in the trenches in the inter-level dielectric layer. An apparatus produced by the method is disclosed.
摘要翻译：替代栅极工艺中多晶硅MOS电容器的方法和装置。一种方法包括在半导体衬底上设置栅极电介质层; 在所述电介质层上设置多晶硅栅极层; 图案化栅介电层和多晶硅栅极层以形成由至少最小多晶硅与多晶硅间距隔开的多个多晶硅门; 限定包含至少一个所述多晶硅栅极并且不包含形成伪栅极的所述多晶硅栅极中的至少一个的多晶硅电阻器区域; 在层间电介质层上沉积掩模层; 图案化掩模层以暴露伪栅极; 去除虚拟栅极下面的伪栅极和栅极电介质层，以将沟槽留在层间电介质层中; 以及在层间电介质层的沟槽中形成高k金属栅极器件。公开了通过该方法制造的装置。

10. 发明申请

US20130126955A1 Methods and Apparatus for Hybrid MOS Capacitors in Replacement Gate Process 有权
标题翻译：混合MOS电容器在替代栅极工艺中的方法和装置
公开(公告)号：US20130126955A1
公开(公告)日：2013-05-23
申请号：US13303096
申请日：2011-11-22
申请人： Pai-Chieh Wang , Tung-Heng Hsieh , Yimin Huang
发明人： Pai-Chieh Wang , Tung-Heng Hsieh , Yimin Huang
IPC分类号： H01L29/94 , H01L21/02
CPC分类号： H01L29/94 , H01L27/0629 , H01L27/0811 , H01L28/20
摘要： Methods and apparatus for hybrid MOS capacitors in replacement gate process. A method is disclosed including patterning a gate dielectric layer and a polysilicon gate layer to form a polysilicon gate region over a substrate; forming an inter-level dielectric layer over the substrate and surrounding the polysilicon gate region; defining polysilicon resistor regions each containing at least one portion of the polysilicon gate region and not containing at least one other portion of the polysilicon gate region, forming dummy gate regions removing the dummy gate regions and the gate dielectric layer underneath the dummy gate regions to leave trenches; and forming high-k metal gate devices in the trenches. A capacitor region including a high-k metal gate and a polysilicon gate next to the high-k metal gate is disclosed. Additional hybrid capacitor apparatuses are disclosed.
摘要翻译：替代栅极工艺中混合MOS电容器的方法和装置。公开了一种方法，其包括图案化栅极电介质层和多晶硅栅极层以在衬底上形成多晶硅栅极区域; 在所述衬底上形成层间电介质层并围绕所述多晶硅栅极区域; 限定多晶硅电阻器区域，每个多晶硅电阻器区域包含多晶硅栅极区域的至少一部分并且不包含多晶硅栅极区域的至少一个其他部分，形成伪栅极区域，去除伪栅极区域和伪栅极区域下方的栅极介电层，以留下沟渠并在沟槽中形成高k金属栅极器件。公开了一种包括高k金属栅极和与高k金属栅极相邻的多晶硅栅极的电容器区域。公开了另外的混合电容器装置。

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