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1. 发明申请

US20130026637A1 METAL GATE ELECTRODE OF A FIELD EFFECT TRANSISTOR 有权
标题翻译：场效应晶体管的金属栅极电极
公开(公告)号：US20130026637A1
公开(公告)日：2013-01-31
申请号：US13189732
申请日：2011-07-25
申请人： Cheng-Hao HOU , Peng-Soon LIM , Da-Yuan LEE , Xiong-Fei YU , Chun-Yuan CHOU , Fan-Yi HSU , Jian-Hao CHEN , Kuang-Yuan HSU
发明人： Cheng-Hao HOU , Peng-Soon LIM , Da-Yuan LEE , Xiong-Fei YU , Chun-Yuan CHOU , Fan-Yi HSU , Jian-Hao CHEN , Kuang-Yuan HSU
IPC分类号： H01L23/48 , H01L21/28
CPC分类号： H01L21/28026 , H01L21/28088 , H01L29/401 , H01L29/4966 , H01L29/51 , H01L29/66477 , H01L29/66545 , H01L29/78 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit fabrication is disclosed, and more particularly a field effect transistor with a low resistance metal gate electrode is disclosed. An exemplary structure for a metal gate electrode of a field effect transistor comprises a lower portion formed of a first metal material, wherein the lower portion has a recess, a bottom portion and sidewall portions, wherein each of the sidewall portions has a first width; and an upper portion formed of a second metal material, wherein the upper portion has a protrusion and a bulk portion, wherein the bulk portion has a second width, wherein the protrusion extends into the recess, wherein a ratio of the second width to the first width is from about 5 to 10.
摘要翻译：公开了集成电路制造，更具体地说，公开了具有低电阻金属栅电极的场效应晶体管。场效应晶体管的金属栅电极的示例性结构包括由第一金属材料形成的下部，其中下部具有凹部，底部和侧壁部分，其中每个侧壁部分具有第一宽度; 以及由第二金属材料形成的上部，其中所述上部具有突起和主体部分，其中所述主体部分具有第二宽度，其中所述突起延伸到所述凹部中，其中所述第二宽度与所述第一宽度的比率宽度为约5至10。

2. 发明申请

US20130017678A1 METHODS OF ANNEAL AFTER DEPOSITION OF GATE LAYERS 有权
标题翻译：盖层沉积后的退火方法
公开(公告)号：US20130017678A1
公开(公告)日：2013-01-17
申请号：US13183909
申请日：2011-07-15
申请人： Chun Hsiung TSAI , Xiong-Fei YU , Yu-Lien HUANG , Da-Wen LIN
发明人： Chun Hsiung TSAI , Xiong-Fei YU , Yu-Lien HUANG , Da-Wen LIN
IPC分类号： H01L21/263
CPC分类号： H01L21/324 , H01L21/28088 , H01L21/28176 , H01L21/28185 , H01L29/401 , H01L29/4966 , H01L29/511 , H01L29/513 , H01L29/517 , H01L29/66545 , H01L29/7833
摘要： Multi-stage preheat high-temperature anneal processes after the deposition of the gate dielectric layer(s) reduce the number of interfacial sites and improve the negative bias temperature instability (NTBI) performance of a p-type metal-oxide-semiconductor transistor (PMOS). The gate dielectric layers may include an interfacial oxide layer and a high-k dielectric layer. The multi-stage preheat is designed to reduce dopant deactivation and to improve inter-mixing between the interfacial oxide layer and the high-k dielectric layer. The high-temperature anneal is used to reduce the number of interfacial sites at the interface between the silicon substrate and the interfacial oxide layer.
摘要翻译：在沉积栅极电介质层之后的多级预热高温退火工艺减少界面位置的数量并改善p型金属氧化物半导体晶体管（PMOS）的负偏压温度不稳定性（NTBI）性能）。栅极电介质层可以包括界面氧化物层和高k电介质层。多级预热设计用于减少掺杂剂失活并改善界面氧化物层和高k电介质层之间的相互混合。高温退火用于减少硅衬底和界面氧化物层之间界面处的界面位置数。

3. 发明申请

US20110081774A1 METHODS FOR A GATE REPLACEMENT PROCESS 有权
标题翻译：门更换过程的方法
公开(公告)号：US20110081774A1
公开(公告)日：2011-04-07
申请号：US12575280
申请日：2009-10-07
申请人： Matt Yeh , Hui Ouyang , Da-Yuan Lee , Kuang Yuan Hsu , Hun-Jan Tao , Xiong-Fei Yu
发明人： Matt Yeh , Hui Ouyang , Da-Yuan Lee , Kuang Yuan Hsu , Hun-Jan Tao , Xiong-Fei Yu
IPC分类号： H01L21/28
CPC分类号： H01L29/401 , H01L21/823828 , H01L21/823835 , H01L21/823842 , H01L29/66545
摘要： A method for fabricating a semiconductor device is disclosed. In one embodiment, the method may include providing a substrate; forming a gate structure including a first dummy gate over the substrate; removing the first dummy gate from the gate structure to form a trench; forming an interfacial layer, high-k dielectric layer, and capping layer to partially fill in the trench; forming a second dummy gate over the capping layer, wherein the second dummy gate fills the trench; and replacing the second dummy gate with a metal gate. In one embodiment, the method may include providing a substrate; forming an interfacial layer over the substrate; forming a high-k dielectric layer over the interfacial layer; forming an etch stop layer over the high-k dielectric layer; forming a capping layer including a low thermal budget silicon over the etch stop layer; forming a dummy gate layer over the capping layer; forming a gate structure; and performing a gate replacement process.
摘要翻译：公开了一种制造半导体器件的方法。在一个实施例中，该方法可以包括提供衬底; 在所述衬底上形成包括第一虚拟栅极的栅极结构; 从栅极结构去除第一伪栅极以形成沟槽; 形成界面层，高k电介质层和覆盖层以部分地填充在沟槽中; 在所述覆盖层上形成第二虚拟栅极，其中所述第二伪栅极填充所述沟槽; 并用金属栅极替换第二虚拟栅极。在一个实施例中，该方法可以包括提供衬底; 在衬底上形成界面层; 在界面层上形成高k电介质层; 在所述高k电介质层上形成蚀刻停止层; 在所述蚀刻停止层上形成包括低热预算硅的覆盖层; 在覆盖层上形成虚拟栅极层; 形成栅极结构; 并进行门更换处理。

4. 发明授权

US08809175B2 Methods of anneal after deposition of gate layers 有权
标题翻译：沉积栅极层后的退火方法
公开(公告)号：US08809175B2
公开(公告)日：2014-08-19
申请号：US13183909
申请日：2011-07-15
申请人： Chun Hsiung Tsai , Xiong-Fei Yu , Yu-Lien Huang , Da-Wen Lin
发明人： Chun Hsiung Tsai , Xiong-Fei Yu , Yu-Lien Huang , Da-Wen Lin
IPC分类号： H01L21/28
CPC分类号： H01L21/324 , H01L21/28088 , H01L21/28176 , H01L21/28185 , H01L29/401 , H01L29/4966 , H01L29/511 , H01L29/513 , H01L29/517 , H01L29/66545 , H01L29/7833
摘要： Multi-stage preheat high-temperature anneal processes after the deposition of the gate dielectric layer(s) reduce the number of interfacial sites and improve the negative bias temperature instability (NTBI) performance of a p-type metal-oxide-semiconductor transistor (PMOS). The gate dielectric layers may include an interfacial oxide layer and a high-k dielectric layer. The multi-stage preheat is designed to reduce dopant deactivation and to improve inter-mixing between the interfacial oxide layer and the high-k dielectric layer. The high-temperature anneal is used to reduce the number of interfacial sites at the interface between the silicon substrate and the interfacial oxide layer.
摘要翻译：在沉积栅极电介质层之后的多级预热高温退火工艺减少界面位置的数量并改善p型金属氧化物半导体晶体管（PMOS）的负偏压温度不稳定性（NTBI）性能）。栅极电介质层可以包括界面氧化物层和高k电介质层。多级预热设计用于减少掺杂剂失活并改善界面氧化物层和高k电介质层之间的相互混合。高温退火用于减少硅衬底和界面氧化物层之间界面处的界面位置数。

5. 发明申请

US20130056836A1 Techniques Providing Metal Gate Devices with Multiple Barrier Layers 有权
标题翻译：提供具有多个屏障层的金属栅极器件的技术
公开(公告)号：US20130056836A1
公开(公告)日：2013-03-07
申请号：US13224033
申请日：2011-09-01
申请人： Xiong-Fei Yu , Chun-Yuan Chou , Da-Yuan Lee , Kuan-Yuan Hsu , Jeff J. Xu
发明人： Xiong-Fei Yu , Chun-Yuan Chou , Da-Yuan Lee , Kuan-Yuan Hsu , Jeff J. Xu
IPC分类号： H01L29/772 , H01L21/336
CPC分类号： H01L27/092 , H01L21/28088 , H01L21/2855 , H01L21/28556 , H01L21/32051 , H01L21/76843 , H01L21/76846 , H01L21/823807 , H01L21/823814 , H01L21/823828 , H01L21/823842 , H01L29/165 , H01L29/4966 , H01L29/512 , H01L29/517 , H01L29/66545 , H01L29/6656 , H01L29/6659 , H01L29/7848
摘要： A semiconductor device with a metal gate is disclosed. An exemplary semiconductor device with a metal gate includes a semiconductor substrate, source and drain features on the semiconductor substrate, a gate stack over the semiconductor substrate and disposed between the source and drain features. The gate stack includes a HK dielectric layer formed over the semiconductor substrate, a plurality of barrier layers of a metal compound formed on top of the HK dielectric layer, wherein each of the barrier layers has a different chemical composition; and a stack of metals gate layers deposited over the plurality of barrier layers.
摘要翻译：公开了一种具有金属栅极的半导体器件。具有金属栅极的示例性半导体器件包括半导体衬底，半导体衬底上的源极和漏极特征，半导体衬底上的栅极堆叠并且设置在源极和漏极特征之间。所述栅堆叠包括形成在所述半导体衬底上的HK电介质层，形成在所述HK电介质层的顶部上的金属化合物的多个势垒层，其中每个所述阻挡层具有不同的化学组成; 以及沉积在所述多个阻挡层上的一叠金属栅极层。

6. 发明申请

US20130032900A1 BUFFER LAYER AND METHOD OF FORMING BUFFER LAYER 有权
标题翻译：缓冲层和形成缓冲层的方法
公开(公告)号：US20130032900A1
公开(公告)日：2013-02-07
申请号：US13195554
申请日：2011-08-01
申请人： Cheng-Hao HOU , Wei-Yang LEE , Xiong-Fei YU , Kuang-Yuan HSU
发明人： Cheng-Hao HOU , Wei-Yang LEE , Xiong-Fei YU , Kuang-Yuan HSU
IPC分类号： H01L21/288 , H01L29/78
CPC分类号： H01L29/517 , H01L21/28088 , H01L29/4966 , H01L29/7833
摘要： Buffer layer and method of forming the buffer layer, the method including forming a high-k dielectric layer, forming a titanium nitride layer over the high-k dielectric layer, forming a silicon layer on the titanium nitride layer, annealing the silicon layer into the titanium nitride layer to form an annealed silicon layer and forming an n-metal over the high-k dielectric layer.
摘要翻译：缓冲层和形成缓冲层的方法，所述方法包括形成高k电介质层，在高k电介质层上形成氮化钛层，在氮化钛层上形成硅层，将硅层退火成氮化钛层以形成退火的硅层，并在高k电介质层上形成n金属。

7. 发明授权

US08367563B2 Methods for a gate replacement process 有权
标题翻译：门更换过程的方法
公开(公告)号：US08367563B2
公开(公告)日：2013-02-05
申请号：US12575280
申请日：2009-10-07
申请人： Matt Yeh , Hui Ouyang , Da-Yuan Lee , Kuang Yuan Hsu , Hun-Jan Tao , Xiong-Fei Yu
发明人： Matt Yeh , Hui Ouyang , Da-Yuan Lee , Kuang Yuan Hsu , Hun-Jan Tao , Xiong-Fei Yu
IPC分类号： H01L21/3205
CPC分类号： H01L29/401 , H01L21/823828 , H01L21/823835 , H01L21/823842 , H01L29/66545
摘要： A method for fabricating a semiconductor device is disclosed. In one embodiment, the method may include providing a substrate; forming a gate structure including a first dummy gate over the substrate; removing the first dummy gate from the gate structure to form a trench; forming an interfacial layer, high-k dielectric layer, and capping layer to partially fill in the trench; forming a second dummy gate over the capping layer, wherein the second dummy gate fills the trench; and replacing the second dummy gate with a metal gate. In one embodiment, the method may include providing a substrate; forming an interfacial layer over the substrate; forming a high-k dielectric layer over the interfacial layer; forming an etch stop layer over the high-k dielectric layer; forming a capping layer including a low thermal budget silicon over the etch stop layer; forming a dummy gate layer over the capping layer; forming a gate structure; and performing a gate replacement process.
摘要翻译：公开了一种制造半导体器件的方法。在一个实施例中，该方法可以包括提供衬底; 在所述衬底上形成包括第一虚拟栅极的栅极结构; 从栅极结构去除第一伪栅极以形成沟槽; 形成界面层，高k电介质层和覆盖层以部分地填充在沟槽中; 在所述覆盖层上形成第二虚拟栅极，其中所述第二伪栅极填充所述沟槽; 并用金属栅极替换第二虚拟栅极。在一个实施例中，该方法可以包括提供衬底; 在衬底上形成界面层; 在界面层上形成高k电介质层; 在所述高k电介质层上形成蚀刻停止层; 在所述蚀刻停止层上形成包括低热预算硅的覆盖层; 在覆盖层上形成虚拟栅极层; 形成栅极结构; 并进行门更换处理。

8. 发明申请

US20110256731A1 METHOD FOR FABRICATING A GATE DIELECTRIC LAYER 有权
标题翻译：用于制造栅极介电层的方法
公开(公告)号：US20110256731A1
公开(公告)日：2011-10-20
申请号：US12760297
申请日：2010-04-14
申请人： Wei-Yang LEE , Xiong-Fei YU , Jian-Hao CHEN , Cheng-Hao HOU , Da-Yuan LEE , Kuang-Yuan HSU
发明人： Wei-Yang LEE , Xiong-Fei YU , Jian-Hao CHEN , Cheng-Hao HOU , Da-Yuan LEE , Kuang-Yuan HSU
IPC分类号： H01L21/3105 , H01L21/316
CPC分类号： H01L29/517 , H01L21/02181 , H01L21/0228 , H01L21/02323 , H01L21/02337 , H01L21/0234 , H01L21/28194 , H01L29/495 , H01L29/4966 , H01L29/513 , H01L29/66545 , H01L29/6659
摘要： A method for fabricating the gate dielectric layer comprises forming a high-k dielectric layer over a substrate; forming an oxygen-containing layer on the high-k dielectric layer by an atomic layer deposition process; and performing an inert plasma treatment on the oxygen-containing layer.
摘要翻译：一种用于制造栅极电介质层的方法包括在衬底上形成高k电介质层; 通过原子层沉积工艺在高k电介质层上形成含氧层; 对含氧层进行惰性等离子体处理。

9. 发明授权

US08952458B2 Gate dielectric layer having interfacial layer and high-K dielectric over the interfacial layer 有权
标题翻译：栅介质层在界面层上具有界面层和高K电介质
公开(公告)号：US08952458B2
公开(公告)日：2015-02-10
申请号：US13086491
申请日：2011-04-14
申请人： Wei-Yang Lee , Xiong-Fei Yu , Da-Yuan Lee , Kuang-Yuan Hsu
发明人： Wei-Yang Lee , Xiong-Fei Yu , Da-Yuan Lee , Kuang-Yuan Hsu
IPC分类号： H01L21/70 , H01L21/02 , H01L21/8238 , H01L29/423 , H01L21/28 , H01L29/51 , H01L29/66
CPC分类号： H01L29/66477 , H01L21/28185 , H01L21/823857 , H01L29/42368 , H01L29/513 , H01L29/66545
摘要： A semiconductor device includes a substrate having a first active region, a first gate structure over the first active region, wherein the first gate structure includes a first interfacial layer having a convex top surface, a first high-k dielectric over the first interfacial layer, and a first gate electrode over the first high-k dielectric.
摘要翻译：一种半导体器件包括具有第一有源区，第一有源区上的第一栅结构的衬底，其中第一栅结构包括具有凸顶表面的第一界面层，第一界面层上的第一高k电介质，以及在第一高k电介质上的第一栅电极。

10. 发明申请

US20120264281A1 METHOD OF FABRICATING A PLURALITY OF GATE STRUCTURES 有权
标题翻译：制造大量门结构的方法
公开(公告)号：US20120264281A1
公开(公告)日：2012-10-18
申请号：US13085029
申请日：2011-04-12
申请人： Jian-Hao CHEN , Wei-Yang LEE , Wei-Yeh TANG , Xiong-Fei YU , Kuang-Yuan HSU
发明人： Jian-Hao CHEN , Wei-Yang LEE , Wei-Yeh TANG , Xiong-Fei YU , Kuang-Yuan HSU
IPC分类号： H01L21/28
CPC分类号： H01L29/6659 , H01L21/02181 , H01L21/02186 , H01L21/02189 , H01L21/0228 , H01L21/32139 , H01L21/823437 , H01L21/823828 , H01L29/66545 , H01L29/7833
摘要： The invention relates to integrated circuit fabrication, and more particularly to a semiconductor device with a plurality of gate structures. An exemplary method of fabricating the plurality of gate structures comprises providing a silicon substrate; depositing a dummy oxide layer over the substrate; depositing a dummy gate electrode layer over the dummy oxide layer; patterning the layers to define a plurality of dummy gates; forming nitrogen-containing sidewall spacers on the plurality of dummy gates; forming an interlayer dielectric layer between the nitrogen-containing sidewall spacers; selectively depositing a hard mask layer on the interlayer dielectric layer by an atomic layer deposition (ALD) process; removing the dummy gate electrode layer; removing the dummy oxide layer; depositing a gate dielectric; and depositing a gate electrode.
摘要翻译：本发明涉及集成电路制造，更具体地涉及具有多个栅极结构的半导体器件。制造多个栅极结构的示例性方法包括提供硅衬底; 在衬底上沉积虚拟氧化物层; 在虚拟氧化物层上沉积虚拟栅电极层; 图案化层以限定多个虚拟门; 在所述多个虚拟栅极上形成含氮侧壁间隔物; 在所述含氮侧壁间隔件之间形成层间电介质层; 通过原子层沉积（ALD）工艺在层间介质层上选择性地沉积硬掩模层; 去除所述伪栅电极层; 去除虚拟氧化物层; 沉积栅极电介质; 并沉积栅电极。

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