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1. 发明授权

US08334197B2 Method of fabricating high-k/metal gate device 有权
标题翻译：制造高k /金属栅极器件的方法
公开(公告)号：US08334197B2
公开(公告)日：2012-12-18
申请号：US12639630
申请日：2009-12-16
申请人： Da-Yuan Lee , Kuang-Yuan Hsu , Xiong-Fei Yu , Wei-Yang Lee , Matt Yeh
发明人： Da-Yuan Lee , Kuang-Yuan Hsu , Xiong-Fei Yu , Wei-Yang Lee , Matt Yeh
IPC分类号： H01L21/4763
CPC分类号： H01L21/28185 , H01L21/28088 , H01L21/28194 , H01L29/4966 , H01L29/517 , H01L29/66545
摘要： The present disclosure provides a method that includes providing a semiconductor substrate; forming a gate structure over the semiconductor substrate, first gate structure including a dummy dielectric and a dummy gate disposed over the dummy dielectric; removing the dummy gate and the dummy dielectric from the gate structure thereby forming a trench; forming a high-k dielectric layer partially filling the trench; forming a barrier layer over the high-k dielectric layer partially filling the trench; forming an capping layer over the barrier layer partially filling the trench; performing an annealing process; removing the capping layer; forming a metal layer over the barrier layer filling in a remainder of the trench; and performing a chemical mechanical polishing (CMP) to remove the various layers outside the trench.
摘要翻译：本公开提供了一种方法，其包括提供半导体衬底; 在所述半导体衬底上形成栅极结构，所述第一栅极结构包括设置在所述虚拟电介质上的虚设电介质和虚设栅极; 从栅极结构去除伪栅极和虚设电介质，从而形成沟槽; 形成部分填充沟槽的高k电介质层; 在部分填充沟槽的高k电介质层上形成阻挡层; 在所述阻挡层上形成部分填充所述沟槽的覆盖层; 进行退火处理; 去除覆盖层; 在所述阻挡层上形成填充在所述沟槽的其余部分中的金属层; 并进行化学机械抛光（CMP）以去除沟槽外的各种层。

2. 发明授权

US08222132B2 Fabricating high-K/metal gate devices in a gate last process 有权
标题翻译：在最后一道工序中制造高K /金属栅极器件
公开(公告)号：US08222132B2
公开(公告)日：2012-07-17
申请号：US12567227
申请日：2009-09-25
申请人： Da-Yuan Lee , Jian-Hao Chen , Chi-Chun Chen , Matt Yeh , Hsing-Jui Lee
发明人： Da-Yuan Lee , Jian-Hao Chen , Chi-Chun Chen , Matt Yeh , Hsing-Jui Lee
IPC分类号： H01L21/3205
CPC分类号： H01L21/823814 , H01L21/823807 , H01L21/823842 , H01L21/823857 , H01L29/7848
摘要： The present disclosure provides a method that includes forming first and second gate structures over first and second regions, respectively, removing a first dummy gate and first dummy dielectric from the first gate structure thereby forming a first trench and removing a second dummy gate and second dummy dielectric from the second gate structure thereby forming a second trench, forming a gate layer to partially fill the first and second trenches, forming a material layer to fill the remainder of the first and second trenches, removing a portion of the material layer such that a remaining portion of the material layer protects a first portion of the gate layer located at a bottom portion of the first and second trenches, removing a second portion of the gate layer, removing the remaining portion of the material layer from the first and second trenches.
摘要翻译：本公开提供了一种方法，其包括分别在第一和第二区域上形成第一和第二栅极结构，从第一栅极结构去除第一伪栅极和第一虚设电介质，从而形成第一沟槽并且去除第二虚拟栅极和第二虚拟栅极从第二栅极结构的电介质，从而形成第二沟槽，形成栅极层以部分地填充第一和第二沟槽，形成材料层以填充第一和第二沟槽的其余部分，去除材料层的一部分，使得材料层的剩余部分保护位于第一和第二沟槽的底部的栅极层的第一部分，去除栅极层的第二部分，从第一和第二沟槽去除材料层的剩余部分。

3. 发明申请

US20110195548A1 METHOD OF FABRICATING GATE ELECTRODE USING A TREATED HARD MASK 有权
标题翻译：使用处理硬掩模制作门电极的方法
公开(公告)号：US20110195548A1
公开(公告)日：2011-08-11
申请号：US12700862
申请日：2010-02-05
申请人： Matt Yeh , Hui Ouyang , Han-Pin Chung , Shiang-Bau Wang
发明人： Matt Yeh , Hui Ouyang , Han-Pin Chung , Shiang-Bau Wang
IPC分类号： H01L21/8238 , H01L21/265 , H01L21/28
CPC分类号： H01L21/823807 , H01L21/26586 , H01L21/823814 , H01L21/823828 , H01L29/1083 , H01L29/165 , H01L29/66628 , H01L29/7834 , H01L29/7848
摘要： A method for fabricating an integrated device is disclosed. In an embodiment, a hard mask layer with a limited thickness is formed over a gate electrode layer. A treatment is provided to the hard mask layer to make the hard mask layer more resistant to a wet etch solution. Then, a patterning is provided on the treated hard mask layer and the gate electrode to from a gate structure.
摘要翻译：公开了一种用于制造集成器件的方法。在一个实施例中，在栅极电极层上形成具有有限厚度的硬掩模层。向硬掩模层提供处理以使硬掩模层对湿蚀刻溶液更具抗性。然后，在经处理的硬掩模层和栅电极上提供从栅极结构构图。

4. 发明申请

US20110143529A1 METHOD OF FABRICATING HIGH-K/METAL GATE DEVICE 有权
标题翻译：制造高K /金属栅极器件的方法
公开(公告)号：US20110143529A1
公开(公告)日：2011-06-16
申请号：US12639630
申请日：2009-12-16
申请人： Da-Yuan Lee , Kuang-Yuan Hsu , Xiong-Fei Yu , Wei-Yang Lee , Matt Yeh
发明人： Da-Yuan Lee , Kuang-Yuan Hsu , Xiong-Fei Yu , Wei-Yang Lee , Matt Yeh
IPC分类号： H01L21/28
CPC分类号： H01L21/28185 , H01L21/28088 , H01L21/28194 , H01L29/4966 , H01L29/517 , H01L29/66545
摘要： The present disclosure provides a method that includes providing a semiconductor substrate; forming a gate structure over the semiconductor substrate, first gate structure including a dummy dielectric and a dummy gate disposed over the dummy dielectric; removing the dummy gate and the dummy dielectric from the gate structure thereby forming a trench; forming a high-k dielectric layer partially filling the trench; forming a barrier layer over the high-k dielectric layer partially filling the trench; forming an capping layer over the barrier layer partially filling the trench; performing an annealing process; removing the capping layer; forming a metal layer over the barrier layer filling in a remainder of the trench; and performing a chemical mechanical polishing (CMP) to remove the various layers outside the trench.
摘要翻译：本公开提供了一种方法，其包括提供半导体衬底; 在所述半导体衬底上形成栅极结构，所述第一栅极结构包括设置在所述虚拟电介质上的虚设电介质和虚设栅极; 从栅极结构去除伪栅极和虚设电介质，从而形成沟槽; 形成部分填充沟槽的高k电介质层; 在部分填充沟槽的高k电介质层上形成阻挡层; 在所述阻挡层上形成部分填充所述沟槽的覆盖层; 进行退火处理; 去除覆盖层; 在所述阻挡层上形成填充在所述沟槽的其余部分中的金属层; 并进行化学机械抛光（CMP）以去除沟槽外的各种层。

5. 发明申请

US20110143510A1 METHOD OF CONTROLLING GATE THICKNESS IN FORMING FINFET DEVICES 有权
标题翻译：控制栅极厚度在形成FinFET器件中的方法
公开(公告)号：US20110143510A1
公开(公告)日：2011-06-16
申请号：US12638958
申请日：2009-12-15
申请人： Shun Wu LIN , Peng-Soon Lim , Matt Yeh , Ouyang Hui
发明人： Shun Wu LIN , Peng-Soon Lim , Matt Yeh , Ouyang Hui
IPC分类号： H01L21/336
CPC分类号： H01L29/66795 , H01L29/785
摘要： A method of forming a FinFET device is provided. In one embodiment, a fin is formed on a substrate. A gate structure is formed over the fin, the gate structure having a dielectric layer and a conformal first polysilicon layer formed above the dielectric layer. An etch stop layer is formed above the first polysilicon layer and thereafter a second polysilicon layer is formed above the etch stop layer. The second polysilicon layer and the etch stop layer are removed. A metal layer is formed above the first polysilicon layer. The first polysilicon layer is reacted with the metal layer to silicide the first polysilicon layer. Any un-reacted metal layer is thereafter removed and source and drain regions are formed on opposite sides of the fin.
摘要翻译：提供了一种形成FinFET器件的方法。在一个实施例中，在衬底上形成翅片。栅极结构形成在鳍片上，栅极结构具有介电层和形成在电介质层上方的共形第一多晶硅层。在第一多晶硅层上方形成蚀刻停止层，此后在蚀刻停止层上方形成第二多晶硅层。去除第二多晶硅层和蚀刻停止层。金属层形成在第一多晶硅层的上方。第一多晶硅层与金属层反应以使第一多晶硅层硅化。此后除去任何未反应的金属层，并且在鳍的相对侧上形成源区和漏区。

6. 发明申请

US20110097867A1 METHOD OF CONTROLLING GATE THICKNESSES IN FORMING FUSI GATES 审中-公开
标题翻译：控制浇口厚度的方法
公开(公告)号：US20110097867A1
公开(公告)日：2011-04-28
申请号：US12819701
申请日：2010-06-21
申请人： Shun Wu LIN , Matt YEH
发明人： Shun Wu LIN , Matt YEH
IPC分类号： H01L21/8234 , H01L21/336
CPC分类号： H01L21/823835 , H01L21/28097 , H01L29/4975 , H01L29/66545 , H01L29/7833
摘要： A method of fabricating a semiconductor device is provided. In one embodiment, a gate structure is formed on a substrate, the gate structure having a gate dielectric layer and a first polysilicon layer formed above the gate dielectric layer. A passivation layer is formed above the first polysilicon layer. A second polysilicon layer is formed above the passivation layer. The second polysilicon layer and the passivation layer are removed. A metal layer is formed above the first polysilicon layer. The first polysilicon layer is reacted with the metal layer to silicide the first polysilicon layer. Any un-reacted metal layer is thereafter removed.
摘要翻译：提供一种制造半导体器件的方法。在一个实施例中，栅极结构形成在衬底上，栅极结构具有形成在栅极介电层上的栅极电介质层和第一多晶硅层。在第一多晶硅层上方形成钝化层。在钝化层上方形成第二多晶硅层。去除第二多晶硅层和钝化层。金属层形成在第一多晶硅层的上方。第一多晶硅层与金属层反应以使第一多晶硅层硅化。此后除去任何未反应的金属层。

7. 发明申请

US20100124823A1 NOVEL METHOD FOR REMOVING DUMMY POLY IN A GATE LAST PROCESS 有权
标题翻译：用于在门过程中去除多余聚合物的新方法
公开(公告)号：US20100124823A1
公开(公告)日：2010-05-20
申请号：US12275082
申请日：2008-11-20
申请人： Matt Yeh , Fan-Yi Hsu , Shun Wu Lin , Shu-Yuan Ku , Hui Ouyang
发明人： Matt Yeh , Fan-Yi Hsu , Shun Wu Lin , Shu-Yuan Ku , Hui Ouyang
IPC分类号： H01L21/302 , H01L21/71
CPC分类号： H01L21/32134 , H01L21/02071 , H01L21/28035 , H01L21/823828 , H01L21/82385 , H01L27/11 , H01L29/66583
摘要： A method is provided for fabricating a semiconductor device. The method includes removing a silicon material from a gate structure located on a substrate through a cycle including: etching the silicon material to remove a portion thereof, where the substrate is spun at a spin rate, applying a cleaning agent to the substrate, and drying the substrate; and repeating the cycle, where a subsequent cycle includes a subsequent spin rate for spinning the substrate during the etching and where the subsequent spin rate does not exceed the spin rate of the previous cycle.
摘要翻译：提供了制造半导体器件的方法。该方法包括通过循环从位于衬底上的栅极结构去除硅材料，包括：蚀刻硅材料以除去其中的一部分，其中衬底以旋转速率纺丝，向衬底施加清洁剂，并干燥基材; 并重复该循环，其中随后的循环包括用于在蚀刻期间旋转衬底的随后旋转速率，并且其中随后的旋转速率不超过先前循环的旋转速率。

8. 发明申请

US20100112811A1 METHOD FOR PATTERNING A METAL GATE 有权
标题翻译：用于绘制金属门的方法
公开(公告)号：US20100112811A1
公开(公告)日：2010-05-06
申请号：US12431838
申请日：2009-04-29
申请人： Matt Yeh , Shun Wu Lin , Chung-Ming Wang , Chi-Chun Chen
发明人： Matt Yeh , Shun Wu Lin , Chung-Ming Wang , Chi-Chun Chen
IPC分类号： H01L21/28
CPC分类号： H01L21/823842 , H01L21/823828 , H01L21/82385 , H01L27/0207 , H01L29/66545
摘要： The present disclosure provides a method for fabricating a semiconductor device. The method includes forming first, second, third, and fourth gate structures on a semiconductor substrate, each gate structure having a dummy gate, removing the dummy gate from the first, second, third, and fourth gate structures, thereby forming first, second, third, and fourth trenches, respectively, forming a metal layer to partially fill in the first, second, third, and fourth trenches, forming a first photoresist layer over the first, second, and third trenches, etching a portion of the metal layer in the fourth trench, removing the first photoresist layer, forming a second photoresist layer over the second and third trenches, etching the metal layer in the first trench and the remaining portion of the metal layer in the fourth trench, and removing the second photoresist layer.
摘要翻译：本公开提供了一种用于制造半导体器件的方法。该方法包括在半导体衬底上形成第一，第二，第三和第四栅极结构，每个栅极结构具有虚拟栅极，从第一，第二，第三和第四栅极结构去除伪栅极，从而形成第一，第三沟槽和第四沟槽，分别形成金属层以部分地填充在第一，第二，第三和第四沟槽中，在第一，第二和第三沟槽上形成第一光致抗蚀剂层，蚀刻金属层的一部分第四沟槽，去除第一光致抗蚀剂层，在第二和第三沟槽上形成第二光致抗蚀剂层，蚀刻第一沟槽中的金属层和第四沟槽中金属层的剩余部分，以及去除第二光致抗蚀剂层。

9. 发明申请

US20100048011A1 METHOD OF PATTERNING A METAL GATE OF SEMICONDUCTOR DEVICE 有权
标题翻译：图案化半导体器件金属栅的方法
公开(公告)号：US20100048011A1
公开(公告)日：2010-02-25
申请号：US12371672
申请日：2009-02-16
申请人： Matt Yeh , Shun Wu Lin , Chi-Chun Chen , Ryan Chia-Jen Chen , Yi-Hsing Chen , Chien-Hao Chen , Donald Y. Chao , Kuo-Bin Huang
发明人： Matt Yeh , Shun Wu Lin , Chi-Chun Chen , Ryan Chia-Jen Chen , Yi-Hsing Chen , Chien-Hao Chen , Donald Y. Chao , Kuo-Bin Huang
IPC分类号： H01L21/3205
CPC分类号： H01L21/28105 , H01L21/28123 , H01L21/28158 , H01L21/31111 , H01L21/32139 , H01L29/401
摘要： Provided are methods of patterning metal gate structures including a high-k gate dielectric. In an embodiment, a soluble hard mask layer may be used to provide a masking element to pattern a metal gate. The soluble hard mask layer may be removed from the substrate by water or a photoresist developer. In an embodiment, a hard mask including a high-k dielectric is formed. In a further embodiment, a protection layer is formed underlying a photoresist pattern. The protection layer may protect one or more layers formed on the substrate from a photoresist stripping process.
摘要翻译：提供了包括高k栅极电介质的金属栅极结构的图案化方法。在一个实施方案中，可以使用可溶性硬掩模层来提供掩模元件以对金属栅极进行图案化。可溶性硬掩模层可以通过水或光致抗蚀剂显影剂从基底上去除。在一个实施例中，形成包括高k电介质的硬掩模。在另一个实施例中，保护层形成在光致抗蚀剂图案下面。保护层可以保护形成在衬底上的一个或多个层与光致抗蚀剂剥离工艺。

10. 发明申请

US20080096394A1 GATE DIELECTRIC LAYERS AND METHODS OF FABRICATING GATE DIELECTRIC LAYERS 有权
标题翻译：门电介质层和制造栅介质层的方法
公开(公告)号：US20080096394A1
公开(公告)日：2008-04-24
申请号：US11551577
申请日：2006-10-20
申请人： Chi-Chun Chen , Matt Yeh , Shih-Chang Chen , Mong-Song Liang , Jennifer Chen , Da-Yuan Lee
发明人： Chi-Chun Chen , Matt Yeh , Shih-Chang Chen , Mong-Song Liang , Jennifer Chen , Da-Yuan Lee
IPC分类号： H01L21/31
CPC分类号： H01L21/31155 , H01L21/02126 , H01L21/02211 , H01L21/02238 , H01L21/02255 , H01L21/02271 , H01L21/02321 , H01L21/0234 , H01L21/02351 , H01L21/26506 , H01L21/28185 , H01L21/2822 , H01L21/3141 , H01L21/31633 , H01L21/31662 , H01L21/823462
摘要： A method of forming a gate dielectric layer includes forming a gate dielectric layer over a substrate. The gate dielectric layer is processed with carbon-containing ions. The gate dielectric layer is thermally processed, thereby providing the gate dielectric layer with a level of carbon between about 1 atomic % and about 20 atomic %.
摘要翻译：形成栅极电介质层的方法包括在衬底上形成栅极电介质层。用含碳离子处理栅介质层。栅极电介质层被热处理，从而为栅极电介质层提供约1原子％至约20原子％之间的碳含量。

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