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1. 发明申请

US20130328131A1 Semiconductor Devices, Methods of Manufacture Thereof, and Methods of Forming Resistors 有权
公开(公告)号：US20130328131A1
公开(公告)日：2013-12-12
申请号：US13492571
申请日：2012-06-08
申请人： Chia-Yu Lu , Jian-Hao Chen , Chih-Hung Wang , Tung-Heng Hsieh , Kuo-Feng Yu , Chin-Shan Hou , Shyue-Shyh Lin
发明人： Chia-Yu Lu , Jian-Hao Chen , Chih-Hung Wang , Tung-Heng Hsieh , Kuo-Feng Yu , Chin-Shan Hou , Shyue-Shyh Lin
IPC分类号： H01L27/06 , H01L21/02
CPC分类号： H01L27/0629 , H01L21/76811 , H01L23/485 , H01L23/5228 , H01L27/0688 , H01L28/20 , H01L28/24 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor devices, methods of manufacture thereof, and methods of forming resistors are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming a first insulating material over a workpiece, and forming a conductive chemical compound material over the first insulating material. The conductive chemical compound material is patterned to form a resistor. A second insulating material is formed over the resistor, and the second insulating material is patterned. The patterned second insulating material is filled with a conductive material to form a first contact coupled to a first end of the resistor and to form a second contact coupled to a second end of the resistor.

2. 发明授权

US08859386B2 Semiconductor devices, methods of manufacture thereof, and methods of forming resistors 有权
标题翻译：半导体器件，其制造方法以及形成电阻器的方法
公开(公告)号：US08859386B2
公开(公告)日：2014-10-14
申请号：US13492571
申请日：2012-06-08
申请人： Chia-Yu Lu , Jian-Hao Chen , Chih-Hung Wang , Tung-Heng Hsieh , Kuo-Feng Yu , Chin-Shan Hou , Shyue-Shyh Lin
发明人： Chia-Yu Lu , Jian-Hao Chen , Chih-Hung Wang , Tung-Heng Hsieh , Kuo-Feng Yu , Chin-Shan Hou , Shyue-Shyh Lin
IPC分类号： H01L27/06 , H01L21/70 , H01L49/02
CPC分类号： H01L27/0629 , H01L21/76811 , H01L23/485 , H01L23/5228 , H01L27/0688 , H01L28/20 , H01L28/24 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor devices, methods of manufacture thereof, and methods of forming resistors are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming a first insulating material over a workpiece, and forming a conductive chemical compound material over the first insulating material. The conductive chemical compound material is patterned to form a resistor. A second insulating material is formed over the resistor, and the second insulating material is patterned. The patterned second insulating material is filled with a conductive material to form a first contact coupled to a first end of the resistor and to form a second contact coupled to a second end of the resistor.
摘要翻译：公开了半导体器件，其制造方法和形成电阻器的方法。在一个实施例中，制造半导体器件的方法包括在工件上形成第一绝缘材料，并在第一绝缘材料上形成导电化合物材料。将导电化合物材料图案化以形成电阻器。第二绝缘材料形成在电阻器上，第二绝缘材料被图案化。图案化的第二绝缘材料填充有导电材料以形成耦合到电阻器的第一端的第一触点，并形成耦合到电阻器的第二端的第二触点。

3. 发明申请

US20130157452A1 SEMICONDUCTOR DEVICE INCLUDING POLYSILICON RESISTOR AND METAL GATE RESISTOR AND METHODS OF FABRICATING THEREOF 有权
标题翻译：包括多晶硅电阻和金属栅极电阻的半导体器件及其制造方法
公开(公告)号：US20130157452A1
公开(公告)日：2013-06-20
申请号：US13328875
申请日：2011-12-16
申请人： Jian-Hao Chen , Chia-Yu Lu , Tung-Heng Hsieh , Kuo-Feng Yu , Chin-Shan Hou , Hsien-Chin Lin , Shyue-Shyh Lin
发明人： Jian-Hao Chen , Chia-Yu Lu , Tung-Heng Hsieh , Kuo-Feng Yu , Chin-Shan Hou , Hsien-Chin Lin , Shyue-Shyh Lin
IPC分类号： H01L21/28
CPC分类号： H01L21/28123 , H01L27/0629 , H01L28/20 , H01L29/42376 , H01L29/66545 , H01L29/78
摘要： A described method includes providing a semiconductor substrate. A first gate structure is formed on the semiconductor substrate and a sacrificial gate structure formed adjacent the first gate structure. The sacrificial gate structure may be used to form a metal gate structure using a replacement gate methodology. A dielectric layer is formed overlying the first gate structure and the sacrificial gate structure. The dielectric layer has a first thickness above a top surface of the first gate structure and a second thickness, less than the first thickness, above a top surface of the sacrificial gate structure. (See, e.g., FIGS. 5, 15, 26). Thus, a subsequent planarization process of the dielectric layer may not contact the first gate structure.
摘要翻译：所述方法包括提供半导体衬底。第一栅极结构形成在半导体衬底上，并且邻近第一栅极结构形成牺牲栅极结构。牺牲栅极结构可以用于使用替代栅极方法形成金属栅极结构。覆盖第一栅极结构和牺牲栅极结构的介电层形成。电介质层在第一栅极结构的顶表面上方具有第一厚度，并且在牺牲栅极结构的顶表面上方具有小于第一厚度的第二厚度。（参见例如图5,15,26）。因此，电介质层的随后的平坦化处理可以不接触第一栅极结构。

4. 发明授权

US09070624B2 Semiconductor device including polysilicon resistor and metal gate resistor and methods of fabricating thereof 有权
标题翻译：包括多晶硅电阻器和金属栅极电阻器的半导体器件及其制造方法
公开(公告)号：US09070624B2
公开(公告)日：2015-06-30
申请号：US13328875
申请日：2011-12-16
申请人： Jian-Hao Chen , Chia-Yu Lu , Tung-Heng Hsieh , Kuo-Feng Yu , Chin-Shan Hou , Hsien-Chin Lin , Shyue-Shyh Lin
发明人： Jian-Hao Chen , Chia-Yu Lu , Tung-Heng Hsieh , Kuo-Feng Yu , Chin-Shan Hou , Hsien-Chin Lin , Shyue-Shyh Lin
IPC分类号： H01L21/28 , H01L49/02 , H01L27/06 , H01L29/78 , H01L29/66 , H01L29/423
CPC分类号： H01L21/28123 , H01L27/0629 , H01L28/20 , H01L29/42376 , H01L29/66545 , H01L29/78
摘要： A described method includes providing a semiconductor substrate. A first gate structure is formed on the semiconductor substrate and a sacrificial gate structure formed adjacent the first gate structure. The sacrificial gate structure may be used to form a metal gate structure using a replacement gate methodology. A dielectric layer is formed overlying the first gate structure and the sacrificial gate structure. The dielectric layer has a first thickness above a top surface of the first gate structure and a second thickness, less than the first thickness, above a top surface of the sacrificial gate structure. (See, e.g., FIGS. 5, 15, 26). Thus, a subsequent planarization process of the dielectric layer may not contact the first gate structure.
摘要翻译：所述方法包括提供半导体衬底。第一栅极结构形成在半导体衬底上，并且邻近第一栅极结构形成牺牲栅极结构。牺牲栅极结构可以用于使用替代栅极方法形成金属栅极结构。覆盖第一栅极结构和牺牲栅极结构的介电层形成。电介质层在第一栅极结构的顶表面上方具有第一厚度，并且在牺牲栅极结构的顶表面上方具有小于第一厚度的第二厚度。（参见例如图5,15,26）。因此，电介质层的随后的平坦化处理可能不接触第一栅极结构。

5. 发明授权

US08373219B2 Method of fabricating a gate stack integration of complementary MOS device 有权
标题翻译：制造互补MOS器件栅极堆叠集成的方法
公开(公告)号：US08373219B2
公开(公告)日：2013-02-12
申请号：US13460359
申请日：2012-04-30
申请人： Shu-Wei Chung , Kuo-Feng Yu , Shyue-Shyh Lin
发明人： Shu-Wei Chung , Kuo-Feng Yu , Shyue-Shyh Lin
IPC分类号： H01L29/788 , H01L21/8238
CPC分类号： H01L21/823842 , H01L21/823821 , H01L21/823857
摘要： A method includes providing a substrate comprising a first device region and a second device region; forming an oxide cap over the substrate and in the first device region and the second device region; forming a first metal layer over the oxide cap, wherein the first metal layer has a first portion in the first device region and a second portion in the second device region; forming a mask to cover the second portion of the first metal layer, wherein the first portion of the first metal layer is exposed; removing the first portion of the first metal layer and the oxide cap from the first device region; removing the mask; and forming a second metal layer in the first device region and the second device region, wherein the second metal layer in the second device region is over the second portion of the first metal layer.
摘要翻译：一种方法包括提供包括第一器件区域和第二器件区域的衬底; 在所述基板上和所述第一器件区域和所述第二器件区域中形成氧化物盖; 在所述氧化物盖上形成第一金属层，其中所述第一金属层具有所述第一器件区域中的第一部分和所述第二器件区域中的第二部分; 形成掩模以覆盖第一金属层的第二部分，其中暴露第一金属层的第一部分; 从第一装置区域去除第一金属层和氧化物盖的第一部分; 去除面膜; 以及在第一器件区域和第二器件区域中形成第二金属层，其中第二器件区域中的第二金属层位于第一金属层的第二部分之上。

6. 发明申请

US20100317181A1 Gate Stack Integration of Complementary MOS Devices 有权
标题翻译：互补MOS器件的栅极堆栈集成
公开(公告)号：US20100317181A1
公开(公告)日：2010-12-16
申请号：US12750413
申请日：2010-03-30
申请人： Shu-Wei Chung , Kuo-Feng Yu , Shyue-Shyh Lin
发明人： Shu-Wei Chung , Kuo-Feng Yu , Shyue-Shyh Lin
IPC分类号： H01L21/28
CPC分类号： H01L21/823842 , H01L21/823821 , H01L21/823857
摘要： A method of forming an integrated circuit structure includes providing a substrate comprising a first device region and a second device region; forming an oxide cap over the substrate and in the first device region and the second device region; forming a first metal layer over the oxide cap, wherein the first metal layer has a first portion in the first device region and a second portion in the second device region; forming a mask to cover the second portion of the first metal layer, wherein the first portion of the first metal layer is exposed; removing the first portion of the first metal layer and the oxide cap from the first device region; removing the mask; and forming a second metal layer in the first device region and the second device region, wherein the second metal layer in the second device region is over the second portion of the first metal layer.
摘要翻译：形成集成电路结构的方法包括提供包括第一器件区域和第二器件区域的衬底; 在所述基板上和所述第一器件区域和所述第二器件区域中形成氧化物盖; 在所述氧化物盖上方形成第一金属层，其中所述第一金属层具有所述第一器件区域中的第一部分和所述第二器件区域中的第二部分; 形成掩模以覆盖第一金属层的第二部分，其中暴露第一金属层的第一部分; 从第一装置区域去除第一金属层和氧化物盖的第一部分; 去除面膜; 以及在第一器件区域和第二器件区域中形成第二金属层，其中第二器件区域中的第二金属层位于第一金属层的第二部分之上。

7. 发明授权

US08173499B2 Method of fabricating a gate stack integration of complementary MOS device 有权
标题翻译：制造互补MOS器件栅极堆叠集成的方法
公开(公告)号：US08173499B2
公开(公告)日：2012-05-08
申请号：US12750413
申请日：2010-03-30
申请人： Shu-Wei Chung , Kuo-Feng Yu , Shyue-Shyh Lin
发明人： Shu-Wei Chung , Kuo-Feng Yu , Shyue-Shyh Lin
IPC分类号： H01L21/8238 , H01L29/788
CPC分类号： H01L21/823842 , H01L21/823821 , H01L21/823857
摘要： A method of forming an integrated circuit structure includes providing a substrate comprising a first device region and a second device region; forming an oxide cap over the substrate and in the first device region and the second device region; forming a first metal layer over the oxide cap, wherein the first metal layer has a first portion in the first device region and a second portion in the second device region; forming a mask to cover the second portion of the first metal layer, wherein the first portion of the first metal layer is exposed; removing the first portion of the first metal layer and the oxide cap from the first device region; removing the mask; and forming a second metal layer in the first device region and the second device region, wherein the second metal layer in the second device region is over the second portion of the first metal layer.
摘要翻译：形成集成电路结构的方法包括提供包括第一器件区域和第二器件区域的衬底; 在所述基板上和所述第一器件区域和所述第二器件区域中形成氧化物盖; 在所述氧化物盖上方形成第一金属层，其中所述第一金属层具有所述第一器件区域中的第一部分和所述第二器件区域中的第二部分; 形成掩模以覆盖第一金属层的第二部分，其中暴露第一金属层的第一部分; 从第一装置区域去除第一金属层和氧化物盖的第一部分; 去除面膜; 以及在第一器件区域和第二器件区域中形成第二金属层，其中第二器件区域中的第二金属层位于第一金属层的第二部分之上。

8. 发明申请

US20120273890A1 Method of Fabricating a Gate Stack Integration of Complementary MOS Device 有权
标题翻译：制造互补MOS器件的栅极堆栈集成的方法
公开(公告)号：US20120273890A1
公开(公告)日：2012-11-01
申请号：US13460359
申请日：2012-04-30
申请人： Shu-Wei Chung , Kuo-Feng Yu , Shyue-Shyh Lin
发明人： Shu-Wei Chung , Kuo-Feng Yu , Shyue-Shyh Lin
IPC分类号： H01L27/12
CPC分类号： H01L21/823842 , H01L21/823821 , H01L21/823857
摘要： A method includes providing a substrate comprising a first device region and a second device region; forming an oxide cap over the substrate and in the first device region and the second device region; forming a first metal layer over the oxide cap, wherein the first metal layer has a first portion in the first device region and a second portion in the second device region; forming a mask to cover the second portion of the first metal layer, wherein the first portion of the first metal layer is exposed; removing the first portion of the first metal layer and the oxide cap from the first device region; removing the mask; and forming a second metal layer in the first device region and the second device region, wherein the second metal layer in the second device region is over the second portion of the first metal layer.
摘要翻译：一种方法包括提供包括第一器件区域和第二器件区域的衬底; 在所述基板上和所述第一器件区域和所述第二器件区域中形成氧化物盖; 在所述氧化物盖上形成第一金属层，其中所述第一金属层具有所述第一器件区域中的第一部分和所述第二器件区域中的第二部分; 形成掩模以覆盖第一金属层的第二部分，其中暴露第一金属层的第一部分; 从第一装置区域去除第一金属层和氧化物盖的第一部分; 去除面膜; 以及在第一器件区域和第二器件区域中形成第二金属层，其中第二器件区域中的第二金属层位于第一金属层的第二部分之上。

9. 发明授权

US08507957B2 Integrated circuit layouts with power rails under bottom metal layer 有权
标题翻译：集成电路布局与底部金属层下的电源轨
公开(公告)号：US08507957B2
公开(公告)日：2013-08-13
申请号：US13098925
申请日：2011-05-02
申请人： Yung-Chin Hou , Shyue-Shyh Lin , Li-Chun Tien , Shu-Min Chen , Pin-Dai Sue
发明人： Yung-Chin Hou , Shyue-Shyh Lin , Li-Chun Tien , Shu-Min Chen , Pin-Dai Sue
IPC分类号： H01L23/48 , H01L21/768 , H01L29/41
CPC分类号： H01L27/11807 , H01L23/5286 , H01L27/0207 , H01L2027/11881 , H01L2924/0002 , H01L2924/00
摘要： A circuit includes a semiconductor substrate; a bottom metal layer over the semiconductor substrate, wherein no additional metal layer is between the semiconductor substrate and the bottom metal layer; and a cell including a plug-level power rail under the bottom metal layer.
摘要翻译：电路包括半导体衬底; 半导体衬底上的底部金属层，其中在半导体衬底和底部金属层之间没有附加的金属层; 以及在底部金属层下方包括插头级电源轨的电池。

10. 发明授权

US07663237B2 Butted contact structure 失效
标题翻译：对接接触结构
公开(公告)号：US07663237B2
公开(公告)日：2010-02-16
申请号：US11320512
申请日：2005-12-27
申请人： Yuan-Ching Peng , Chloe Hsin-yi Chen , David Hsu-Wei Lwu , Shyue-Shyh Lin , Wei-Ming Chen
发明人： Yuan-Ching Peng , Chloe Hsin-yi Chen , David Hsu-Wei Lwu , Shyue-Shyh Lin , Wei-Ming Chen
IPC分类号： H01L23/48
CPC分类号： H01L27/11 , H01L21/76895 , H01L21/76897 , H01L21/823475 , H01L21/823481 , H01L27/1104 , H01L29/495 , H01L29/66545 , H01L29/7833
摘要： A semiconductor structure and a method of forming the same using replacement gate processes are provided. The semiconductor structure includes a butted contact coupling a source/drain region, or a silicide on the source/drain region, of a first transistor and a gate extension. The semiconductor structure further includes a contact pad over the source/drain region of the first transistor and electrically coupled to the source/drain region. The addition of the contact pad reduces the contact resistance and the possibility that an open circuit is formed between the butted contact and the source/drain region. The contact pad preferably has a top surface substantially leveled with a top surface of the gate extension.
摘要翻译：提供半导体结构及其使用替代栅极工艺的方法。半导体结构包括耦合第一晶体管和栅极延伸的源极/漏极区域或源极/漏极区域上的硅化物的对接触点。半导体结构还包括在第一晶体管的源极/漏极区域上的电连接到源极/漏极区域的接触焊盘。接触焊盘的添加减小了接触电阻以及在对接触点和源极/漏极区域之间形成开路的可能性。接触垫优选地具有基本上与门延伸部的顶表面平齐的顶表面。

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