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1. 发明申请

WO0059016A3 METHOD FOR PRODUCING THIN, UNIFORM OXIDE LAYERS ON SILICON SURFACES 审中-公开
标题翻译： METHOD FOR硅表面上生产薄均匀的氧化物层
公开(公告)号：WO0059016A3
公开(公告)日：2001-04-26
申请号：PCT/DE0000799
申请日：2000-03-11
申请人： INST HALBLEITERPHYSIK GMBH , MUESSIG HANS JOACHIM , DABROWSKI JAROSLAW
发明人： MUESSIG HANS-JOACHIM , DABROWSKI JAROSLAW
IPC分类号： C30B33/00 , H01L21/28 , H01L21/316 , H01L29/04
CPC分类号： C30B29/06 , C30B33/005 , H01L21/02238 , H01L21/02255 , H01L21/02299 , H01L21/28167 , H01L21/31662 , H01L29/045
摘要： The invention relates to a method for producing thin, uniform oxide layers on silicon surfaces. Within the next 10 years, the lateral dimensions of silicon components will be reduced to an interatomic distance of approximately 200 and the vertical extensions of the doping concentration profile to an interatomic distance of approximately 50. This requires, among other things, atomically smooth ultra-thin oxide layers on silicon surfaces, for example, gate-oxide layers. The invention thereby aims to provide a method for producing thin, uniform oxide layers on silicon surfaces which provides oxides with a thickness of less than 6 nm. This is achieved by oxidising a silicon surface of increased evenness using an increased tensile stress.
摘要翻译：本发明涉及一种用于在硅表面产生薄的均匀的氧化层的处理。在接下来的10年中，硅器件的至约200原子间距和垂直掺杂分布的区段的横向尺寸可以减小到约50个原子的距离。这要求在硅表面其他事情原子级平滑的超薄氧化层中，例如栅极氧化物。发明内容本发明的一个目的是提出一种用于在硅表面上，氧化物的厚度实现小于6纳米，它是合适的产生薄的均匀的氧化层的方法。根据该目的是这样实现的具有增加的拉伸强度和高平滑性的硅表面被氧化的本发明。

2. 发明申请

WO0017423A2 METHOD FOR PRODUCING AN AMORPHOUS OR POLYCRYSTALLINE LAYER ON AN INSULATING REGION 审中-公开
标题翻译：用于生产无定形的或多晶的层上的场绝缘体
公开(公告)号：WO0017423A2
公开(公告)日：2000-03-30
申请号：PCT/DE9903069
申请日：1999-09-20
申请人： INST HALBLEITERPHYSIK GMBH , TILLACK BERND , HEINEMANN BERND , KNOLL DIETER , EHWALD KARL ERNST , WOLANSKY DIRK
发明人： TILLACK BERND , HEINEMANN BERND , KNOLL DIETER , EHWALD KARL-ERNST , WOLANSKY DIRK
IPC分类号： H01L21/285 , H01L21/20 , H01L21/28 , H01L21/3205 , H01L21/331 , H01L29/732 , C30B29/06
CPC分类号： H01L21/32055 , H01L21/02381 , H01L21/02532 , H01L21/02639
摘要： The invention aims to provide a method for producing an amorphous or polycrystalline layer on an insulating area which in relation to known methods increases the thickness of the amorphous or polycrystalline layer and improves the homogeneity of the deposition, thus resulting in reduced surface roughness while at least maintaining the insulating properties of the insulating area. To this end a suitable seeding layer (28, 29), preferably silicon nitride, is deposited so that the seeding capacity and insulating properties of the SiO2 insulating area (14, 31) during deposition of the amorphous or polycrystalline Si or SiGe layers (15, 16, 17, 33) are improved.
摘要翻译：本发明的目的是提出一种用于在绝缘体区，其中相比于以前的方法中，无定形的或多晶的层的厚度越大，则沉积的均匀性得到提高，因此，表面粗糙度被降低生产无定形的或多晶的层的方法。在这种情况下，应该至少保持该绝缘体区的绝缘性能。根据本发明，这个目的是通过将合适的（28，29）籽晶层，优选氮化硅，Bekeimungsvermögen和绝缘在非晶或多晶层（15，16的沉积由SiO 2制成的绝缘区域（14，31）的特性，17这样来实现，33）由Si或SiGe的提高。

3. 发明申请

WO0014806A9 VERTICAL BIPOLAR TRANSISTOR AND METHOD FOR THE PRODUCTION THEREOF 审中-公开
标题翻译：用于制造垂直双极晶体管AND PROCESS
公开(公告)号：WO0014806A9
公开(公告)日：2000-08-17
申请号：PCT/DE9902884
申请日：1999-09-08
申请人： INST HALBLEITERPHYSIK GMBH , EHWALD KARL ERNST , KNOLL DIETER , HEINEMANN BERND
发明人： EHWALD KARL-ERNST , KNOLL DIETER , HEINEMANN BERND
IPC分类号： H01L21/28 , H01L21/331 , H01L21/8222 , H01L21/8248 , H01L21/8249 , H01L27/06 , H01L29/08 , H01L29/732 , H01L29/737 , H01L29/10
CPC分类号： H01L29/66242 , H01L21/8249 , H01L29/0821 , H01L29/7378
摘要： The invention relates to a vertical bipolar transistor and a method for the production thereof. The aim of the invention is to produce a vertical bipolar transistor and to disclose a method for the production thereof, whereby excellent high frequency properties can be obtained for said transistor using the simplest possible production technology involving an implanted epitaxy-free collector and only one polysilicon layer spread over a large surface and which can be easily integrated into a conventional mainstream CMOS process without epitaxially produced trough areas. It is possible to simplify technology, while at the same time improving the high frequency parameters of vertical bipolar transistors by reducing the parasitic lateral and vertical components of the resistance of the collector, by means of a self-adjusting transistor construction in conjunction with a special method of production, whereby a highly doped monocrystalline base connection area surrounding the active base in a ring-like manner is removed in the region of the collector connection by reactive ion etching, together with the underlying less doped area of the collector or a part thereof.
摘要翻译：本发明涉及一种纵向双极晶体管及其制备方法。本发明的目的是提供一种垂直双极型晶体管及其制备方法，其中所述晶体管的高频特性优良可与最简单的可能的制造技术来实现，其与植入epitaxiefreien集电极管理和只有一个大面积沉积的多晶硅层且容易地在传统的“主流的方法 “CMOS工艺可以在没有外延制造阱区被集成。制造工艺的简化，同时提高在降低的寄生横向和垂直集电极电阻器部件的垂直双极型晶体管的高频参数是根据本发明通过自晶体管结构结合一特殊的制造方法，其中活性基环状由围绕高掺杂单晶硅基极连接区域在集电端子的区域实现反应离子蚀刻去除相同与更弱掺杂集电极的底层区域一起或与一部分。

4. 发明申请

WO0013206A3 METHOD FOR DOPING EXTERNAL BASE CONNECTION AREAS OF Si-BASED SINGLE POLYSILICON NPN BI-POLAR TRANSISTORS 审中-公开
标题翻译：法使用兴奋剂外部连接根据地Si系单独多晶硅NPN双极晶体管
公开(公告)号：WO0013206A3
公开(公告)日：2000-06-02
申请号：PCT/DE9902789
申请日：1999-08-30
申请人： INST HALBLEITERPHYSIK GMBH , SCHMUNDT HOLGER , KNOLL DIETER , HEINEMANN BERND
发明人： SCHMUNDT HOLGER , KNOLL DIETER , HEINEMANN BERND
IPC分类号： H01L21/225 , H01L21/3215 , H01L21/331 , H01L29/737
CPC分类号： H01L29/66242 , H01L21/2252 , H01L21/32155
摘要： The invention relates to a method for doping external base connection areas of Si-based single polysilicon NPN bi-polar transistors. The aim of the invention is to provide a method for doping the external base connection areas of Si-based single polysilicon NPN bi-polar transistors, whereby said method, in addition to meeting requirements that can also be fulfilled by using ion implementation, i.e. providing a high surface concentration of doping atoms with a low thermal budget, low penetration depths and an absence of defects, guarantees extensive avoidance of TED in the inner area of the transistors. This is achieved by employing a BBr3 pre-coating process as a diffusion process. The doping of base connection areas of single polysilicon technology NPN bi-polar transistors is therefore carried out in a diffusion step, as opposed to ionic implantation.
摘要翻译：本发明涉及一种用于掺杂Si系单多晶硅npn双极晶体管的外部基极连接区域的方法。本发明的目的是提出的外部基极连接区域的掺杂的方法Si系单多晶硅npn双极晶体管，其中，上的要求，这也可以通过离子注入来实现，即，掺杂剂原子的高表面浓度具有低的热预算低的穿透深度和免于缺陷，确保尽可能避免TED在内部晶体管区域。根据本发明，此目的是通过一种的BBr 3-Vorbelegungsprozess地方作为Eindiffusionsprozess应用来实现的。在单多晶硅技术npn双极晶体管的基极连接区域的掺杂不是由离子注入而是由扩散步骤的手段这样进行。

5. 发明申请

WO0008617A3 METHOD FOR DETERMINING DYNAMIC TRAFFIC INFORMATION 审中-公开
标题翻译：确定动态运输信息的方法
公开(公告)号：WO0008617A3
公开(公告)日：2000-05-11
申请号：PCT/DE9902379
申请日：1999-07-30
申请人： INST HALBLEITERPHYSIK GMBH , LIPPERT GUNTHER
发明人： LIPPERT GUNTHER
IPC分类号： G08G1/0962 , G08G1/09 , G08G1/01
CPC分类号： G08G1/096716 , G08G1/096775
摘要： The invention relates to a method for determining dynamic traffic information. Said method makes use of the change in the transmitting power of a moving mobile telephone which occurs as the distance between a mobile telephone and a base station changes. The position of a mobile station is accordingly determined via the base station in whose coverage the mobile telephone is located and via the mobile telephone transmitting power received by said base station. On the basis of the change in transmitting power, i.e. change in the mobile telephone's position in relation to the base station, a change in the position of the mobile telephone can be detected. The number of moving and stationary mobile telephones is identified in a base station. Two adjacent base stations which are involved in a communication calculate the position of the mobile telephone from changes in transmitting power. The data are processed by the individual base stations or by a central unit. The evaluated data are retransmitted to existing traffic guidance systems or transmitted via traffic radio.
摘要翻译：本发明涉及一种确定动态交通信息的方法。本发明基于利用移动电话的传输功率，移动电话随移动电话与基站之间的距离变化而变化。因此，移动电话的位置通过基站，在移动电话所处的范围内以及从该基站接收的移动电话的发射功率。由于发射功率的改变或者改变到基站的位置，检测到移动电话位置的改变。在基站中，识别移动和站立的移动电话的数量。通信管理中涉及的两个相邻基站通过传输功率的变化来计算移动电话的位置。数据由各个基站或中心局处理。评估的数据被转发到现有的交通控制系统或通过交通广播进行广播。

6. 发明申请

WO9933114A2 SEMICONDUCTOR SUBSTRATE WITH EMBEDDED ISOLATING LAYER FOR INTEGRATED CIRCUITS 审中-公开
标题翻译：具有凹陷隔离层用于集成电路的半导体衬底
公开(公告)号：WO9933114A2
公开(公告)日：1999-07-01
申请号：PCT/DE9803794
申请日：1998-12-18
申请人： INST HALBLEITERPHYSIK GMBH , ERZGRAEBER HEIDE B , BOLZE KLAUS DETLEF , GRABOLLA THOMAS , WOLFF ANDRE
发明人： ERZGRAEBER HEIDE B , BOLZE KLAUS-DETLEF , GRABOLLA THOMAS , WOLFF ANDRE
IPC分类号： H01L21/822 , H01L21/02 , H01L23/522 , H01L27/04 , H01L27/06 , H01L27/12
CPC分类号： H01L28/10 , H01L23/522 , H01L27/0688 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： The invention relates to an integrated circuit with reduced parasitic capacitive influences and a method for producing same. The aim of the invention is to provide an integrated circuit with reduced parasitic capacitive influences and a method for producing same, in which the parasitic capacitive influences on individual elements of the integrated circuit are reduced. A further aim of the invention is for the technological process for producing the contact and printed circuit system of modern CMOS technology not to be adversely influenced during production and, in particular, to ensure that no additional planarising steps are required. To this end the invention provides for a partial isolating layer which is at least 5 mu m thick, is locally restricted to the area of the elements of the integrated circuit and is embedded in the semiconductor substrate. Those losses caused by parasitic influences which are affected by the specific electric resistance of the silicon substrate used are reduced markedly so that, for example, the quality of an integrated inductor can be raised by approximately 40 %, depending on the chosen thickness of the embedded isolating layer, and in relation to planar inductors based on conventional CMOS.
摘要翻译：本发明涉及一种具有减小的寄生电容效应的集成电路以及用于它们的制备方法。本发明的目的是提供一种具有降低的寄生电容效应的集成电路和其制备方法，其中，所述寄生电容效应被降低到集成电路的各个元件的处理。继续在技术序列的准备需要实现的接触和Leitbahnsystems现代CMOS技术不会受到不利影响，尤其是没有额外的平坦化的步骤。这个目的是通过部分，至少5微米厚的绝缘层，其被定位于集成电路的元件的面积和在该半导体衬底沉没实现。由于其是依赖于所使用大大降低硅衬底的电阻率的寄生损失的影响，使得例如在埋入绝缘膜的选定厚度依赖性的集成电感器的约40％的质量，并且可以超越常规CMOS技术相反平面电感被增加。

7. 发明申请

WO0076057A8 VOLTAGE-CONTROLLED OSCILLATOR WITH LC RESONANT CIRCUIT 审中-公开
标题翻译：采用LC谐振电路中的电压控制振荡器
公开(公告)号：WO0076057A8
公开(公告)日：2001-04-12
申请号：PCT/DE0001385
申请日：2000-04-26
申请人： INST HALBLEITERPHYSIK GMBH , HERZEL FRANK , WEGER PETER
发明人： HERZEL FRANK , WEGER PETER
IPC分类号： H03B1/00 , H03B5/12 , H03K3/354 , H03L7/099
CPC分类号： H03L7/099 , H03B5/1215 , H03B5/1228 , H03B5/1253 , H03B5/1268 , H03B5/1293 , H03B2201/0216 , H03K3/354 , H03L2207/06
摘要： The invention relates to a voltage-controlled oscillator with an LC resonant circuit, especially for producing integrated voltage-controlled oscillators for the lower GHz range. The aim of the invention is to provide a voltage-controlled oscillator with an LC resonant circuit with which a continuous frequency tuning across a wide range of frequencies can be achieved with only little phase noise or phase jitter. To this end, the voltage-controlled oscillator with an LC resonant circuit with at least one inductivity can be connected to a further inductivity in periodic parallel and/or in series via a switch device that is actuated by the oscillator frequency, one control input of the switch device being connected to a variable DC voltage. The ratio of the duration of the conductive state and the duration of the non-conductive state of the switch devices can be modified within an oscillation period of the oscillator depending on the value of the control voltage. Corresponding to the ratio of the duration of the conductive state and the duration of the non-conductive state of the switch devices within one oscillation period of the oscillator the time-averaged, effective inductivity can be modified depending on the value of the control voltage.
摘要翻译：本发明涉及一种具有LC谐振电路的电压控制振荡器，特别是用于实现集成压控振荡器的用于较低GHz范围内。发明内容本发明的一个目的是提供一种具有LC谐振电路，其特别具有低相位噪声和连续Frequenzdurchstimmbarkeit的相位抖动在一个宽的范围内实现的电压控制振荡器。根据本发明，该目的在于，在电压控制振荡器实现具有具有经与所述振荡器频率切换装置致动的至少一个电感的LC谐振电路包括另一电感器是在并行周期性和/或串联连接，并且使开关装置的控制输入到可变DC电压连接。导通状态的持续时间和所述开关装置的非导通状态的控制电压的值依赖振荡器的振荡周期内的持续时间的比率被改变。因此，导通状态的持续时间的和的比率的开关装置的非导通状态的所述振荡器的振荡周期内的持续时间，在该控制电压的值的依赖性的时间平均，有效电感发生变化。

8. 发明申请

WO9933075A3 DIGITALLY ADJUSTABLE ELECTRONIC CAPACITOR 审中-公开
标题翻译：数字调谐的电子能力
公开(公告)号：WO9933075A3
公开(公告)日：1999-08-26
申请号：PCT/DE9803797
申请日：1998-12-22
申请人： INST HALBLEITERPHYSIK GMBH , MEHR WOLFGANG
发明人： MEHR WOLFGANG
IPC分类号： H01G7/00 , H01G4/255
CPC分类号： H01G7/00
摘要： The invention relates to a digitally adjustable electronic capacitor which can be digitally controlled, tuned in a large capacity range across several magnitudes independently of the voltage available, integrated into circuits and produced economically without requiring the use of monolithic semiconductor crystals. The invention consists of a support and printed conductor levels which are isolated from each other, turned towards each other at a certain angle, preferably 90 DEG , and within each level have conductive printed conductors which are isolated from each other. A capacitor is configured between the printed conductors of the different levels. A digital electronic control element is assigned to each printed conductor level. The printed conductors of each printed conductor level can be connected independently of each other to an electrode via the digital electronic control element assigned to each printed conductor level. At least two printed conductors situated on different conductor levels are linked to the corresponding electrodes by means of the digital electronic control element. The selected capacitor is available at the level of the electrodes.
摘要翻译：本发明涉及一种数字可调谐电子容量，数字控制，在一个大的容量范围在几个数量级的不依赖于可用的电压可调的，如可以产生既作为分立元件，也可以集成在电路和廉价地制备可在不使用单片半导体晶体是必要的。它由在衬底的且彼此并以一定的角度，优选90°相绝缘，一个具有一个平面内相互隔离的导电迹线另一个绞合导体轨道平面。在不同层次互连之间，形成容量。每个导体轨道平面与数字控制电子相关联。的导体轨道平面的互连是对连接在一起的电极互连平面数字电子控制独立的相关联的一个。，它们位于不同的导体轨道的平面的至少两个导电线由相应的控制电子设备的相应电极相连接。在电极处是所选择的能力。

9. 发明专利

DE10013633A1 Static frequency divider with switchable division ratio prevents metastable states using two D=type flip-flops with alternately activatable inputs 未知
公开(公告)号：DE10013633A1
公开(公告)日：2001-09-20
申请号：DE10013633
申请日：2000-03-18
申请人： INST HALBLEITERPHYSIK GMBH
发明人： PIERSCHEL MICHAEL , GUSTAT HANS
IPC分类号： H03K3/356 , H03K23/66 , H03K23/00
摘要： The frequency divider includes two D-type divider flip-flops each having two alternately activatable inputs. The two divider flip-flops are connected behind sequentially connected synchronous D-type flip-flops. The control inputs of the divider flip-flops are connected to separate switching devices, such as the control outputs (Q,Q') of the sequentially connected synchronous D-type flip-flops.

10. 发明专利

DE19944925A1 Vertical layer structure for silicon-based bipolar transistors contains one or more monolayers consisting of doping atoms 未知
公开(公告)号：DE19944925A1
公开(公告)日：2001-03-15
申请号：DE19944925
申请日：1999-09-13
申请人： INST HALBLEITERPHYSIK GMBH
发明人： KRUEGER DIETMAR , MORGENSTERN THOMAS , EHWALD KARL-ERNST , BUGIEL EBERHARD , HEINEMANN BERND , KNOLL DIETER , TILLACK BERND
IPC分类号： H01L21/331 , H01L29/737 , H01L29/732
摘要： Vertical layer structure contains one or more monolayers consisting of doping atoms. An Independent claim is also included for a process for the production of the vertical layer structure comprising producing the monolayers by interrupting the growth of an epitaxial layer stack and adsorption of gaseous doping material compounds. Preferred Features: The monolayers can be inserted into SiGe heterolayers.

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