专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US09252019B2 Semiconductor device and method for forming the same 有权
标题翻译：半导体装置及其形成方法
公开(公告)号：US09252019B2
公开(公告)日：2016-02-02
申请号：US13222502
申请日：2011-08-31
申请人： Wen-Chi Tsai , Chia-Han Lai , Yung-Chung Chen , Mei-Yun Wang , Chii-Ming Wu , Fang-Cheng Chen , Huang-Ming Chen , Ming-Ta Lei
发明人： Wen-Chi Tsai , Chia-Han Lai , Yung-Chung Chen , Mei-Yun Wang , Chii-Ming Wu , Fang-Cheng Chen , Huang-Ming Chen , Ming-Ta Lei
IPC分类号： H01L21/768 , H01L21/285 , H01L29/417 , H01L21/02 , H01L29/66
CPC分类号： H01L29/78 , H01L21/02063 , H01L21/28512 , H01L21/28518 , H01L21/76802 , H01L21/76805 , H01L21/76814 , H01L21/76825 , H01L21/76831 , H01L21/76844 , H01L21/76855 , H01L23/485 , H01L23/535 , H01L29/41775 , H01L29/45 , H01L29/6659 , H01L2924/0002 , H01L2924/00
摘要： A system and method for forming and using a liner is provided. An embodiment comprises forming an opening in an inter-layer dielectric over a substrate and forming the liner along the sidewalls of the opening. A portion of the liner is removed from a bottom of the opening, and a cleaning process may be performed through the liner. By using the liner, damage to the sidewalls of the opening from the cleaning process may be reduced or eliminated. Additionally, the liner may be used to help implantation of ions within the substrate.
摘要翻译：提供了一种用于形成和使用衬套的系统和方法。一个实施例包括在衬底之上的层间电介质中形成开口，并沿着开口的侧壁形成衬垫。衬套的一部分从开口的底部移除，并且可以通过衬套执行清洁过程。通过使用衬垫，可以减少或消除从清洁过程对开口侧壁的损坏。另外，衬垫可用于帮助衬底内的离子注入。

2. 发明授权

US07307009B2 Phosphoric acid free process for polysilicon gate definition 有权
标题翻译：多晶硅栅极定义的无磷酸工艺
公开(公告)号：US07307009B2
公开(公告)日：2007-12-11
申请号：US10999270
申请日：2004-11-29
申请人： Li-Te S. Lin , Fang-Cheng Chen , Huin-Jer Lin , Yuan-Hung Chiu , Hun-Jan Tao
发明人： Li-Te S. Lin , Fang-Cheng Chen , Huin-Jer Lin , Yuan-Hung Chiu , Hun-Jan Tao
IPC分类号： H01L21/00
CPC分类号： H01L21/31116 , H01L21/32137 , H01L21/32139
摘要： A method of defining a patterned, conductive gate structure for a MOSFET device on a semiconductor substrate includes forming a conductive layer over the semiconductor substrate and forming a capping insulator layer over the conductive layer. An anti-reflective coating (ARC) layer is formed over the capping insulator layer and a patterned photoresist shape is formed on the ARC layer. A first etch procedure using the photoresist shape as an etch mask defines a stack comprised of an ARC shape and a capping insulator shape. A second etch procedure using the stack as an etch mask defines the patterned, conductive gate structure in the conductive layer.
摘要翻译：在半导体衬底上限定用于MOSFET器件的图案化导电栅极结构的方法包括在半导体衬底上形成导电层并在导电层上形成覆盖绝缘体层。在覆盖绝缘体层上形成抗反射涂层（ARC）层，并且在ARC层上形成图案化的光刻胶形状。使用光致抗蚀剂形状作为蚀刻掩模的第一蚀刻步骤限定了由ARC形状和封盖绝缘体形状组成的堆叠。使用堆叠作为蚀刻掩模的第二蚀刻步骤限定了导电层中的图案化的导电栅极结构。

3. 发明申请

US20070040188A1 Contact or via hole structure with enlarged bottom critical dimension 有权
标题翻译：接触或通孔结构，扩大底部临界尺寸
公开(公告)号：US20070040188A1
公开(公告)日：2007-02-22
申请号：US11207450
申请日：2005-08-19
申请人： Ming-Huan Tsai , Fang-Cheng Chen , Chao-Cheng Chen , Syun-Ming Jang
发明人： Ming-Huan Tsai , Fang-Cheng Chen , Chao-Cheng Chen , Syun-Ming Jang
IPC分类号： H01L31/00
CPC分类号： H01L21/76897 , H01L21/76804 , H01L23/485 , H01L23/5226 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit chip includes a buffer layer, an underlying layer, a dielectric layer, a hole, and barrier layer. The buffer layer is over the underlying layer. The dielectric layer is over the buffer layer. The hole is formed in and extending through the dielectric layer and the buffer layer, and opens to the underlying layer. The hole includes a buffer layer portion at the buffer layer and a dielectric layer portion at the dielectric layer. At least part of the buffer layer portion of the hole has a larger cross-section area than a smallest cross-section area of the dielectric layer portion of the hole. The conformal barrier layer covers surfaces of the dielectric layer and the buffer layer in the hole. The hole is a via hole or a contact hole that is later filled with a conductive material to form a conductive via or a conductive contact.
摘要翻译：集成电路芯片包括缓冲层，下层，电介质层，空穴和阻挡层。缓冲层位于底层之上。电介质层在缓冲层之上。孔形成并延伸穿过介电层和缓冲层，并向下层开放。该孔包括在缓冲层处的缓冲层部分和介电层处的电介质层部分。孔的缓冲层部分的至少一部分具有比孔的电介质层部分的最小横截面面积更大的横截面面积。保形阻挡层覆盖孔中的介电层和缓冲层的表面。孔是通孔或接触孔，其后面填充有导电材料以形成导电通孔或导电接触。

4. 发明申请

US20050167397A1 Critical dimension control in a semiconductor fabrication process 有权
标题翻译：半导体制造工艺中的关键尺寸控制
公开(公告)号：US20050167397A1
公开(公告)日：2005-08-04
申请号：US10768455
申请日：2004-01-30
申请人： Fang-Cheng Chen , Li Hsu , I Tseng , Hsu Wen , Tsung Chen , Pin Su
发明人： Fang-Cheng Chen , Li Hsu , I Tseng , Hsu Wen , Tsung Chen , Pin Su
IPC分类号： G01L21/30 , G01R31/00 , H01L21/311 , H01L21/3213 , H01L21/66
CPC分类号： H01L21/31144 , H01L21/31116 , H01L21/31138 , H01L21/32137 , H01L22/20
摘要： A method for controlling a critical dimension in an etched structure comprises the steps of: forming a hard mask above a substrate, measuring a critical dimension of the hard mask, and using the measured hard mask critical dimension to control a critical dimension trim operation performed on a circuit trace above the substrate.
摘要翻译：用于控制蚀刻结构中的临界尺寸的方法包括以下步骤：在衬底上形成硬掩模，测量硬掩模的临界尺寸，并使用测量的硬掩模临界尺寸来控制对衬底上方的电路迹线。

5. 发明授权

US06869868B2 Method of fabricating a MOSFET device with metal containing gate structures 有权
标题翻译：制造具有含金属栅极结构的MOSFET器件的方法
公开(公告)号：US06869868B2
公开(公告)日：2005-03-22
申请号：US10318459
申请日：2002-12-13
申请人： Hsien-Kuang Chiu , Fang-Cheng Chen , Haur-Ywh Chen , Hun-Jan Tao , Yuan-Hung Chiu
发明人： Hsien-Kuang Chiu , Fang-Cheng Chen , Haur-Ywh Chen , Hun-Jan Tao , Yuan-Hung Chiu
IPC分类号： H01L21/28 , H01L21/336 , H01L29/423 , H01L29/49 , H01L29/786 , H01L21/4763
CPC分类号： H01L29/785 , H01L21/28088 , H01L29/42384 , H01L29/4966 , H01L29/665 , H01L29/66795
摘要： A method of forming a composite gate structure for a planar MOSFET device, as well as for vertical, double gate, FINFET device, has been developed. The method features a composite gate structure comprised of an overlying silicon gate structure shape, and an underlying titanium nitride gate structure shape. The titanium nitride component allows a lower work function, and thus lower device operating voltages to be realized when compared to counterpart gate structures formed with only polysilicon. A novel, two step gate structure definition procedure, featuring an anisotropic first etch procedure for definition of the polysilicon gate structure shape, followed by a wet or dry isotopic second etch procedure for definition of the titanium nitride gate structure shape, is employed.
摘要翻译：已经开发了形成用于平面MOSFET器件的复合栅极结构以及用于垂直双栅极FINFET器件的方法。该方法具有由上覆硅栅极结构形状和下面的氮化钛栅极结构形状组成的复合栅极结构。与仅由多晶硅形成的对应栅极结构相比，氮化钛部件允许较低的功函数，因此降低器件工作电压。采用新颖的两步栅极结构定义方法，其特征在于用于定义多晶硅栅极结构形状的各向异性第一蚀刻工艺，随后是用于定义氮化钛栅极结构形状的湿式或干式同位素第二蚀刻工艺。

6. 发明授权

US6051505A Plasma etch method for forming metal-fluoropolymer residue free vias through silicon containing dielectric layers 失效
标题翻译：用于通过含硅介电层形成金属 - 氟聚合物无残余通孔的等离子体蚀刻方法
公开(公告)号：US6051505A
公开(公告)日：2000-04-18
申请号：US35052
申请日：1998-03-05
申请人： Po-Tao Chu , Ming-Chieh Yeh , Fang-Cheng Chen , Ting-Yih Lu
发明人： Po-Tao Chu , Ming-Chieh Yeh , Fang-Cheng Chen , Ting-Yih Lu
IPC分类号： H01L21/311 , H01L21/768 , H01L21/302 , H01L21/461
CPC分类号： H01L21/31116 , H01L21/76802
摘要： A plasma etch method for forming a patterned silicon containing dielectric layer within a microelectronics fabrication. There is first provided a plasma reactor chamber. There is then fixed within the plasma reactor chamber a microelectronics fabrication. The microelectronics fabrication comprises: (1) a substrate employed within the microelectronics fabrication; (2) a metal layer formed over the substrate; (3) a silicon containing dielectric layer formed upon the metal layer; and (4) a patterned photoresist layer formed upon the silicon containing dielectric layer. There is then etched through use of a plasma etch method at a first plasma reactor chamber pressure while employing the patterned photoresist layer as a photoresist etch mask layer the silicon containing dielectric layer to form a patterned silicon containing dielectric layer while reaching and etching the metal layer to form an etched metal layer. The plasma etch method employs an etchant gas composition comprising a fluorine containing etchant gas. Finally, there is pumped the plasma reactor chamber to a second plasma reactor chamber pressure lower than the first plasma reactor chamber pressure for a time sufficient to attenuate formation of a metal-fluoropolymer residue layer upon the etched metal layer.
摘要翻译：一种用于在微电子制造中形成图案化含硅介电层的等离子体蚀刻方法。首先提供了等离子体反应室。然后在等离子体反应器室内固定微电子制造。微电子制造包括：（1）在微电子制造中使用的衬底; （2）在所述基板上形成的金属层; （3）形成在所述金属层上的含硅电介质层; 和（4）形成在含硅介电层上的图案化光致抗蚀剂层。然后通过使用等离子体蚀刻方法在第一等离子体反应器室压力下蚀刻，同时使用图案化的光致抗蚀剂层作为光致抗蚀剂蚀刻掩模层，含硅介电层以形成图案化的含硅介电层，同时到达并蚀刻金属层以形成蚀刻的金属层。等离子体蚀刻方法采用包含含氟蚀刻剂气体的蚀刻剂气体组合物。最后，将等离子体反应室泵送到低于第一等离子体反应器室压力的第二等离子体反应器室的压力足以减少蚀刻金属层上的金属 - 含氟聚合物残余物层的形成。

7. 发明授权

US07511349B2 Contact or via hole structure with enlarged bottom critical dimension 有权
标题翻译：接触或通孔结构，扩大底部临界尺寸
公开(公告)号：US07511349B2
公开(公告)日：2009-03-31
申请号：US11207450
申请日：2005-08-19
申请人： Ming-Huan Tsai , Fang-Cheng Chen , Chao-Cheng Chen , Syun-Ming Jang
发明人： Ming-Huan Tsai , Fang-Cheng Chen , Chao-Cheng Chen , Syun-Ming Jang
IPC分类号： H01L29/76 , H01L29/94 , H01L31/00 , H01L23/52 , H01L29/40
CPC分类号： H01L21/76897 , H01L21/76804 , H01L23/485 , H01L23/5226 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit chip includes a buffer layer, an underlying layer, a dielectric layer, a hole, and barrier layer. The buffer layer is over the underlying layer. The dielectric layer is over the buffer layer. The hole is formed in and extending through the dielectric layer and the buffer layer, and opens to the underlying layer. The hole includes a buffer layer portion at the buffer layer and a dielectric layer portion at the dielectric layer. At least part of the buffer layer portion of the hole has a larger cross-section area than a smallest cross-section area of the dielectric layer portion of the hole. The conformal barrier layer covers surfaces of the dielectric layer and the buffer layer in the hole. The hole is a via hole or a contact hole that is later filled with a conductive material to form a conductive via or a conductive contact.
摘要翻译：集成电路芯片包括缓冲层，下层，电介质层，空穴和阻挡层。缓冲层位于底层之上。电介质层在缓冲层之上。孔形成并延伸穿过介电层和缓冲层，并向下层开放。该孔包括在缓冲层处的缓冲层部分和介电层处的电介质层部分。孔的缓冲层部分的至少一部分具有比孔的电介质层部分的最小横截面面积更大的横截面面积。保形阻挡层覆盖孔中的介电层和缓冲层的表面。孔是通孔或接触孔，其后面填充有导电材料以形成导电通孔或导电接触。

8. 发明申请

US20060054597A1 Wet etchant composition and method for etching HfO2 and ZrO2 审中-公开
标题翻译：湿蚀刻剂组成和蚀刻HfO2和ZrO2的方法
公开(公告)号：US20060054597A1
公开(公告)日：2006-03-16
申请号：US11230349
申请日：2005-09-20
申请人： Baw-Ching Perng , Fang-Cheng Chen , Hun-Jan Tao , Peng-Fu Hsu , Yue-Ho Hsieh , Chih-Cheng Wang , Shih-Yi Hsiao
发明人： Baw-Ching Perng , Fang-Cheng Chen , Hun-Jan Tao , Peng-Fu Hsu , Yue-Ho Hsieh , Chih-Cheng Wang , Shih-Yi Hsiao
IPC分类号： C09K13/00 , H01L21/302 , B44C1/22 , C25F3/00
CPC分类号： H01L21/31111
摘要： A wet etchant solution composition and method for etching oxides of hafnium and zirconium including at least one solvent present at greater than about 50 weight percent with respect to an arbitrary volume of the wet etchant solution; at least one chelating agent present at about 0.1 weight percent to about 10 weight percent with respect to an arbitrary volume of the wet etchant solution; and, at least one halogen containing acid present from about 0.0001 weight percent to about 10 weight percent with respect to an arbitrary volume of the wet etchant solution.
摘要翻译：用于蚀刻铪和锆的氧化物的湿蚀刻剂溶液组合物和方法，其包括相对于任意体积的湿蚀刻剂溶液以大于约50重量％存在的至少一种溶剂; 相对于任意体积的湿蚀刻溶液，至少一种螯合剂以约0.1重量％至约10重量％存在; 并且相对于任意体积的湿蚀刻剂溶液，至少一种含卤素的酸的存在量为约0.0001重量％至约10重量％。

9. 发明申请

US20050127459A1 Novel gate structure and method of forming the gate dielectric with mini-spacer 审中-公开
标题翻译：具有微型间隔物形成栅极电介质的新型栅极结构和方法
公开(公告)号：US20050127459A1
公开(公告)日：2005-06-16
申请号：US11048205
申请日：2005-02-01
申请人： Yuan-Hung Chiu , Ming-Huan Tsai , Fang-Cheng Chen , Hun-Jan Tao
发明人： Yuan-Hung Chiu , Ming-Huan Tsai , Fang-Cheng Chen , Hun-Jan Tao
IPC分类号： H01L21/265 , H01L21/8238 , H01L29/78 , H01L29/80
CPC分类号： H01L21/2652 , H01L29/517 , H01L29/518 , H01L29/78
摘要： A field effect transistor gate structure and a method of fabricating the gate structure with a high-k gate dielectric material and high-k spacer are described. A gate pattern or trench is first etched in a dummy organic or inorganic film deposited over a silicon substrate with source/drain regions. A high-k dielectric material liner is then deposited on all exposed surfaces. Excess poly-silicon gate conductor film is then deposited within and over the trench to provide adequate overburden. Poly-silicon is then planarized with chemical mechanical polishing or etch-back methods such that the high-k material film on top of the dummy film surface is removed during this step. In the final step, the dummy film is disposed off, leaving the final transistor gate structure with high-k gate dielectric and high-k spacer surrounding the gate conductor poly-silicon, with the entire gate structure fabricated to form an FET device on a silicon substrate.
摘要翻译：描述了场效应晶体管栅极结构和制造具有高k栅极介电材料和高k隔离物的栅极结构的方法。首先在具有源极/漏极区域的硅衬底上沉积的虚拟有机或无机膜中蚀刻栅极图案或沟槽。然后将高k电介质材料衬垫沉积在所有暴露的表面上。然后将过多的多晶硅栅极导体膜沉积在沟槽内和沟槽上，以提供足够的覆盖层。然后通过化学机械抛光或蚀刻方法对多晶硅进行平面化，使得在该步骤期间去除虚拟膜表面顶部的高k材料膜。在最后的步骤中，将虚设薄膜放开，留下最终的晶体管栅极结构，其中高k栅极电介质和围绕栅极导体多晶硅的高k隔离层，整个栅极结构被制成以形成FET器件硅衬底。

10. 发明授权

US06900104B1 Method of forming offset spacer manufacturing for critical dimension precision 失效
标题翻译：形成临界尺寸精度的偏移间隔件制造方法
公开(公告)号：US06900104B1
公开(公告)日：2005-05-31
申请号：US10788754
申请日：2004-02-27
申请人： Ryan Chia-Jen Chen , Fang-Cheng Chen , Yuan-Hung Chiu
发明人： Ryan Chia-Jen Chen , Fang-Cheng Chen , Yuan-Hung Chiu
IPC分类号： H01L21/311 , H01L21/336 , H01L21/8238 , H01L21/302 , H01L21/3205 , H01L21/461 , H01L21/4763
CPC分类号： H01L29/6653 , H01L21/31111 , H01L21/31116 , H01L21/823864 , H01L29/6659
摘要： A method for forming an offset spacer adjacent a CMOS gate structure with improved critical dimension control including providing a substrate that has a gate structure; forming at least one oxide layer over the substrate; forming at least one nitride layer over the at least one oxide layer; dry etching the at least one nitride layer in a first dry etching process to expose a first portion of the at least one oxide layer; carrying out a wet etching process to remove the first portion of the at least one oxide layer; and, dry etching the at least one nitride layer in a second dry etching process to remove the at least one nitride layer leaving a second portion of the at least one oxide layer to form an oxide offset spacer along sidewalls of the gate structure.
摘要翻译：一种用于在具有改进的临界尺寸控制的CMOS栅极结构附近形成偏移间隔物的方法，包括提供具有栅极结构的衬底; 在衬底上形成至少一个氧化物层; 在所述至少一个氧化物层上形成至少一个氮化物层; 在第一干蚀刻工艺中干蚀刻所述至少一个氮化物层以暴露所述至少一个氧化物层的第一部分; 执行湿蚀刻工艺以去除所述至少一个氧化物层的第一部分; 并且在第二干蚀刻工艺中干蚀刻所述至少一个氮化物层以移除所述至少一个氮化物层，留下所述至少一个氧化物层的第二部分，以在所述栅极结构的侧壁上形成氧化物偏置间隔物。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式